DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claimed elements “first metallization layer”, “second metallization layer”, and “third metallization layer” of claim 1 and dependent claims are not explicitly disclosed in the specification. It is the examiner’s opinion that the terminology used in the claims is misleading due to the differences in nomenclature and numbering with respect to terms in the specification, resulting in a confusing variety of terms for the same thing (MPEP 608.01(o)). The examiner suggests amending the claims to clearly and accurately reflect the features within the specification to which these elements are intended to refer. For the purpose of examination, the examiner interprets “first metallization layer”, “second metallization layer”, and “third metallization layer” as referring to the first, third, and fifth metallization levels of the specification, respectively.
The disclosure is objected to because of the following informalities:
Paragraph [0003] states “Sometimes the etch process may results CD blow-up, adequate lateral spacing must be maintained…”. This sentence uses the incorrect tense of “result”, is missing a preposition such as “in” between “results” and “CD blow-up”, and improperly joins independent clauses “Sometimes the etch process may results CD blow-up” and “adequate lateral spacing must be maintained…” without a conjunction. Examiner suggests correction to “Sometimes the etch process may result in CD blow-up, therefore adequate lateral spacing must be maintained…” or similar.
Paragraph [00038] states “the sacrificial layer 126 may comprise, for example, a-SiGe, a-Si, SeGe or TiO2”. SeGe may refer to germanium selenide, which is not commonly known in the art for use as a sacrificial material. Additionally, germanium selenide is more typically written as GeSe and a-SiGe is also named. For these reasons, it is the examiner’s opinion that “SeGe” is a typographical error which should be corrected to “SiGe”.
Appropriate correction is required.
Claim Objections
Claims 16 is objected to because of the following informalities:
Claim 16 states “the sacrificial layer includes at least one of a-SiGe, a-Si, SeGe or TiO2”. SeGe may refer to germanium selenide, which is not commonly known in the art for use as a sacrificial material. Additionally, germanium selenide is more typically written as GeSe and a-SiGe is also named. For these reasons, it is the examiner’s opinion that “SeGe” is a typographical error which should be corrected to “SiGe”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 15 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 15 states “…forming a second cap layer between the Vx layer and the Mx+1 layer.” However, the claimed position of the cap layer between the Vx layer and the Mx+1 layer is not described in the specification or drawings, therefore the subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventors had possession of the claimed invention of a cap layer in the claimed position. It is the examiner’s opinion that the claim contains a typographical error, and should read “…forming a second cap layer between the Vx layer and the Mx layer,” because the amended claim would then be supported in the specification and drawings. For the purpose of examination, the examiner interprets claim 15 as “…forming a second cap layer between the Vx layer and the Mx layer.”
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 5 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 5 states “the first metallization layer is a Mx-1 layer, the second metallization layer is a Mx layer, and the third metallization layer is a Mx+1 layer”. “Mx-1 layer”, “Mx layer”, and “M-x+1 layer” are not explicitly defined in the specification. However, as interpreted in light of the specification and broadest reasonable interpretation, the terms refer to metallization layers with relative positional indicators, therefore e.g. “the second metallization layer is a Mx layer” is interpreted as “the second metallization layer is a metallization layer on/above the first metallization layer/M-x-1 layer”, which fails to further limit the subject matter of claim 1 on which it depends because the second metallization layer is already limited to a metallization layer on the first metallization layer. Similar reasoning applies to the limitations on the first and third metallization layers. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of Briggs et al. (U.S. Patent No. 10083905, hereinafter Briggs) in view of Lin et al. (US 10026687 B1, hereinafter Lin) and Shinde et al. (US 9190392 B1, hereinafter Shinde).
Regarding independent claim 1, Briggs claims, in Briggs claim 1, a semiconductor device comprising: a first metallization layer (“a first metallization layer”); a second metallization layer formed on the first metallization layer (“a second metallization layer on the first dielectric layer”, where the first dielectric layer is previously claimed to be on the first metallization layer, thereby making the second layer on the first metallization layer); a super via extending from the first metallization layer (“the skip-via extending through the second dielectric layer, second metallization layer”); and an inner spacer layer from the second metallization layer (“ an insulating, dielectric collar in the second metallization layer around the skip-via”). Briggs does not explicitly claim a third metallization layer formed on the second metallization layer; that the super via extends to the third metallization layer; or that the inner spacer layer is formed on sidewalls of the super via to the first metallization layer.
However, in the same field of endeavor, Lin discloses in Lin FIG. 3 and associated text a third metallization layer (top half of insulator layer 26, including conductive material 40) formed on the second metallization layer (top half of insulator layer 18, including wiring structures 20); a super via (skip via 32a) extending from the first metallization layer (insulator material 12 including wiring structure 14) to the third metallization layer (skip via 32a connects wiring structure 14 to conductive material 40).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Briggs and Lin to provide a super via extending from a first metallization layer to a third metallization layer because doing so would connect the via to functional structures in the third metallization layer with “improved resistance characteristics… [and] efficiency in the chip manufacturing process” (Lin paragraph (3)).
Additionally, in the same field of endeavor, Shinde discloses in Shinde FIG. 3 and associated text an inner spacer layer formed on sidewalls of a via and that the inner spacer layer extends to the first metallization layer (Shinde paragraph (26): through-silicon via (TSV) 180 includes an SiO2 insulator layer surrounding its circumference along its entire length, which ends with back-side contact pad 190 as a first metallization layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Briggs, Lin, and Shinde to provide a super via with an inner spacer layer formed on sidewalls of the super via from the second metallization layer to the first metallization layer because doing so would isolate the super via from intervening layers (as the insulator layer does with layers 130, 140, and 150 in Shinde FIG. 3 and associated text).
Regarding dependent claim 2, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text the super via has a stepped profile (visible steps in skip via 32a near top of capping layer 24 and bottom of conductive material 40).
Regarding dependent claim 3, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text a first cap layer (capping layer 16) formed between the first metallization layer and the inner spacer layer (the references as combined would have the claimed arrangement).
Regarding dependent claim 4, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, a Vx-1 layer between the first metallization layer and the second metallization layer (Briggs claim 1, “a first dielectric layer on the first metallization layer”); and a Vx layer between the third metallization layer and the second metallization layer (Briggs claim 1, “a second dielectric layer on the second metallization layer”, which is between said second metallization layer and the third metallization layer disclosed by Lin and previously combined). Applicant should also note that Lin uses substantially similar terminology “V0, V1, etc.” in reference to a lower portion of insulating layer 18.
Regarding dependent claim 5, Briggs, as modified by Lin and Shinde, further discloses the first metallization layer is a Mx-1 layer, the second metallization layer is a Mx layer, and the third metallization layer is a Mx+1 layer (by the aforementioned interpretation of this claim, the first, second, and third metallization layers are inherently Mx-1, Mx, and Mx-1 layers because they are metallization layers). Applicant should also note that Lin uses substantially similar terminology “M0”, “M1”, and “M2” in reference to wiring structures 14 and 20 and to anticipated wiring structures in trench 36 which corresponds to the conductive material 40 respectively.
Regarding dependent claim 6, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, the super via includes portions of the Vx layer, the Mx layer and the Vx-1 layer (“the skip-via extending through the second dielectric layer, second metallization layer, and first dielectric layer”).
Regarding dependent claim 7, Briggs, as modified by Lin and Shinde, further discloses in Shinde FIG. 3 the super via has a stepped profile at an interface between the Vx layer and the Mx layer (a step is visible in the via between M1 (corresponding to Mx) and the via layer (corresponding to Vx) on it within metal-1 layer 121). Please refer to the following figure:
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Regarding dependent claim 8, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text a second cap layer formed between the second metallization layer and the third metallization layer (capping layer 24 is between wiring structure 20 and conductive material 40).
Regarding dependent claim 9, Briggs, as modified by Lin and Shinde, further discloses the inner spacer layer comprising a dielectric material (Shinde paragraph (26): the insulator layer is SiO2, which is well-known in the art to be a dielectric material), the inner spacer layer electrically isolating the super via from an interlayer dielectric layer (the insulator layer of Shinde isolates the via from buried oxide layer 140, which is an oxide layer in a silicon-on-insulator wafer, making it a silicon oxide layer, which is a dielectric layer). Applicant should also note that the references as combined would include the inner spacer layer of Shinde in the super via of Lin and Briggs, both of which include interlayer dielectric layers which would be isolated from the super via by the inner spacer layer (Lin paragraphs (8) and (11): upper insulator layer 18, which can be made of a dielectric material; Briggs, claim 1: “a first dielectric layer”).
Regarding dependent claim 10, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, the first metallization layer, the second metallization layer and the third metallization layer are part of a back end of line (BEOL) structure of the semiconductor device (Briggs claim 1 begins: “A back-end-of-line interconnect structure having a skip-via, comprising…”, therefore the first, second, and third metallization layers disclosed in the combination of references would be a part of a BEOL structure).
Regarding independent claim 11, Briggs claims, in Briggs claim 1, forming an Mx-1 layer (“a first metallization layer”); forming a Vx-1 layer on the Mx-1 layer (“a first dielectric layer on the first metallization layer”); forming a Mx layer on the Vx-1 layer (“a second metallization layer on the first dielectric layer; a second dielectric layer on the second metallization layer”); etching a trench in the Mx layer and the Vx-1 layer; forming an inner spacer layer (“an insulating, dielectric collar in the second metallization layer around the skip-via”); forming a Vx layer on the Mx layer (“a second dielectric layer on the second metallization layer”); and forming a super via that extends from the Vx layer to the Mx-1 layer (“the skip-via extending through the second dielectric layer, second metallization layer, and first dielectric layer to the first metallization layer”). Briggs does not explicitly claim etching a trench in the Mx layer and the Vx-1 layer; that the inner spacer layer is on sidewalls of an interlayer dielectric layer in the Mx layer and the Vx-1 layer; forming a sacrificial layer in the Mx layer and the Vx-1 layer between the inner spacer layer; forming a Mx+1 layer on the Vx layer; and removing the sacrificial layer.
However, in the same field of endeavor, Lin discloses, in Lin FIG. 1-3 and associated text, etching a trench in the Mx layer and the Vx-1 layer (via opening 32a goes through the upper and lower portions of insulator material 18, corresponding to Mx and Vx-1 layers respectively), an interlayer dielectric layer in the Mx layer and the Vx-1 layer (insulator material 18 may be an interlayer dielectric material (paragraphs (8) and (11)), and is present in both of the regions corresponding to Mx and Vx-1 layers), and forming a Mx+1 layer on the Vx layer (top half of insulator layer 26, including conductive material 40 (Mx+1 layer) is formed on the lower half of insulator layer 26 (Vx layer)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Briggs and Lin to provide a super via extending from a first metallization layer to a third metallization layer because doing so would connect the via to functional structures in the third metallization layer with “improved resistance characteristics… [and] efficiency in the chip manufacturing process” (Lin paragraph (3)). It would also provide an insulating dielectric layer between the super via and features within the Mx and Vx-1 layers, preventing unwanted shorts and improving reliability of the semiconductor device made by the referenced method. Finally, it would provide a trench which can be filled to form the super via in a dual damascene process (Lin paragraph (12)), reducing the number of metal deposition steps required, making the method more efficient.
Additionally, in the same field of endeavor, Shinde discloses in Shinde FIG. 7 and associated text forming an inner spacer layer on sidewalls of a via (step 405, oxidization of TSV sidewalls forms the inner spacer layer), forming a sacrificial layer in the Mx layer and the Vx-1 layer between the inner spacer layer (step 405, TSV is filled with amorphous silicon), and removing the sacrificial layer (step 408, amorphous silicon is removed from TSV).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Briggs, Lin, and Shinde to provide an inner spacer layer on sidewalls of the aforementioned insulating dielectric layer in the Mx and Vx-1 layers to insulate these layers from the super via. Additionally, it would provide a method of making a semiconductor device that uses a sacrificial layer filling the via to enable processing steps on the top surface of the via such as Shinde step 407 before removal of the sacrificial layer to allow subsequent filling of the via with conductive material such as in Shinde step 409.
Regarding dependent claim 12, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text the super via has a stepped profile (visible steps in skip via 32a near top of capping layer 24 and bottom of conductive material 40).
Regarding dependent claim 13, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text forming a first cap layer (capping layer 16) between the first metallization layer and the inner spacer layer (the references as combined would have the claimed arrangement).
Regarding dependent claim 14, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 1 and associated text forming an opening in the first cap layer to expose a portion of the Mx-1 layer (a portion of capping layer 16 is removed and wiring structures 14 are exposed).
Regarding dependent claim 15, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text forming a second cap layer between the Vx layer and the Mx layer (capping layer 24 is between the lower region of insulator layer 26 (Vx) and the upper region of insulator layer 18 (Mx)).
Regarding dependent claim 16, Briggs, as modified by Lin and Shinde, further discloses in Shinde FIG. 7 and associated text the sacrificial layer includes at least one of a-SiGe, a-Si, SeGe or TiO2 (step 405, the sacrificial layer is amorphous silicon or a-Si).
Regarding dependent claim 17, Briggs, as modified by Lin and Shinde, further discloses in Shinde FIG. 3 the super via has a stepped profile at an interface between the Vx layer and the Mx layer (a step is visible in the via between M1 (corresponding to Mx) and the via layer (corresponding to Vx) on it within metal-1 layer 121). Please refer to the following figure:
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Regarding dependent claim 18, Briggs, as modified by Lin and Shinde, further discloses a top surface of the inner spacer layer is coplanar with the top surface of the second cap layer (the references as combined would have the claimed arrangement of inner spacer layer and second cap layer).
Further, before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to form the inner spacer layer in various arrangements with the second cap layer including those in which its top surface would be coplanar to the top surface of the second cap layer because Applicant has not disclosed that the coplanar relationship between the top surfaces of the two features provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with the top surface of the inner spacer layer at any other position above the top surface of the Mx layer because the inner spacer layer’s only function, as disclosed, is to insulate and protect the dielectric layers in the Mx and Vx-1 layers during etching processes, which can be accomplished without the claimed arrangement. Therefore, it would have been an obvious matter of design choice to form these features such that a top surface of the inner spacer layer is coplanar with the top surface of the second cap layer.
Regarding dependent claim 19, Briggs, as modified by Lin and Shinde, further discloses the inner spacer layer comprises a dielectric material (Shinde paragraph (26): the insulator layer is SiO2, which is well-known in the art to be a dielectric material), the inner spacer layer electrically isolating the super via from an interlayer dielectric layer (the insulator layer of Shinde isolates the via from buried oxide layer 140, which is an oxide layer in a silicon-on-insulator wafer, making it a silicon oxide layer, which is a dielectric layer). Applicant should also note that the references as combined would include the inner spacer layer of Shinde in the super via of Lin and Briggs, both of which include interlayer dielectric layers which would be isolated from the super via by the inner spacer layer (Lin paragraphs (8) and (11): upper insulator layer 18, which can be made of a dielectric material; Briggs claim 1: “a first dielectric layer”).
Regarding dependent claim 20, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, the Mx-1 layer, the Vx-1 layer, the Mx layer, the Vx layer and the Mx+1 layer are part of a back end of line (BEOL) structure of the semiconductor device (Briggs claim 1 begins: “A back-end-of-line interconnect structure having a skip-via, comprising…”, therefore the first, second, and third metallization layers disclosed in the combination of references would be a part of a BEOL structure).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Briggs et al. (U.S. Patent No. 10083905, hereinafter Briggs), and further in view of Lin et al. (US 10026687 B1, hereinafter Lin) and Shinde et al. (US 9190392 B1, hereinafter Shinde).
Regarding independent claim 1, Briggs discloses, in Briggs claim 1, a semiconductor device comprising: a first metallization layer (“a first metallization layer”); a second metallization layer formed on the first metallization layer (“a second metallization layer on the first dielectric layer”, where the first dielectric layer is previously claimed to be on the first metallization layer, thereby making the second layer on the first metallization layer); a super via extending from the first metallization layer (“the skip-via extending through the second dielectric layer, second metallization layer”); and an inner spacer layer from the second metallization layer (“ an insulating, dielectric collar in the second metallization layer around the skip-via”). Briggs does not explicitly disclose a third metallization layer formed on the second metallization layer; that the super via extends to the third metallization layer; or that the inner spacer layer is formed on sidewalls of the super via to the first metallization layer.
However, in the same field of endeavor, Lin discloses in Lin FIG. 3 and associated text a third metallization layer (top half of insulator layer 26, including conductive material 40) formed on the second metallization layer (top half of insulator layer 18, including wiring structures 20); a super via (skip via 32a) extending from the first metallization layer (insulator material 12 including wiring structure 14) to the third metallization layer (skip via 32a connects wiring structure 14 to conductive material 40).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Briggs and Lin to provide a super via extending from a first metallization layer to a third metallization layer because doing so would connect the via to functional structures in the third metallization layer with “improved resistance characteristics… [and] efficiency in the chip manufacturing process” (Lin paragraph (3)).
Additionally, in the same field of endeavor, Shinde discloses in Shinde FIG. 3 and associated text an inner spacer layer formed on sidewalls of a via and that the inner spacer layer extends to the first metallization layer (Shinde paragraph (26): through-silicon via (TSV) 180 includes an SiO2 insulator layer surrounding its circumference along its entire length, which ends with back-side contact pad 190 as a first metallization layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Briggs, Lin, and Shinde to provide a super via with an inner spacer layer formed on sidewalls of the super via from the second metallization layer to the first metallization layer because doing so would isolate the super via from intervening layers (as the insulator layer does with layers 130, 140, and 150 in Shinde FIG. 3 and associated text).
Regarding dependent claim 2, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text the super via has a stepped profile (visible steps in skip via 32a near top of capping layer 24 and bottom of conductive material 40).
Regarding dependent claim 3, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text a first cap layer (capping layer 16) formed between the first metallization layer and the inner spacer layer (the references as combined would have the claimed arrangement).
Regarding dependent claim 4, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, a Vx-1 layer between the first metallization layer and the second metallization layer (Briggs claim 1, “a first dielectric layer on the first metallization layer”); and a Vx layer between the third metallization layer and the second metallization layer (Briggs claim 1, “a second dielectric layer on the second metallization layer”, which is between said second metallization layer and the third metallization layer disclosed by Lin and previously combined). Applicant should also note that Lin uses substantially similar terminology “V0, V1, etc.” in reference to a lower portion of insulating layer 18.
Regarding dependent claim 5, Briggs, as modified by Lin and Shinde, further discloses the first metallization layer is a Mx-1 layer, the second metallization layer is a Mx layer, and the third metallization layer is a Mx+1 layer (by the aforementioned interpretation of this claim, the first, second, and third metallization layers are inherently Mx-1, Mx, and Mx-1 layers because they are metallization layers). Applicant should also note that Lin uses substantially similar terminology “M0”, “M1”, and “M2” in reference to wiring structures 14 and 20 and to anticipated wiring structures in trench 36 which corresponds to the conductive material 40 respectively.
Regarding dependent claim 6, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, the super via includes portions of the Vx layer, the Mx layer and the Vx-1 layer (“the skip-via extending through the second dielectric layer, second metallization layer, and first dielectric layer”).
Regarding dependent claim 7, Briggs, as modified by Lin and Shinde, further discloses in Shinde FIG. 3 the super via has a stepped profile at an interface between the Vx layer and the Mx layer (a step is visible in the via between M1 (corresponding to Mx) and the via layer (corresponding to Vx) on it within metal-1 layer 121). Please refer to the following figure:
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Regarding dependent claim 8, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text a second cap layer formed between the second metallization layer and the third metallization layer (capping layer 24 is between wiring structure 20 and conductive material 40).
Regarding dependent claim 9, Briggs, as modified by Lin and Shinde, further discloses the inner spacer layer comprising a dielectric material (Shinde paragraph (26): the insulator layer is SiO2, which is well-known in the art to be a dielectric material), the inner spacer layer electrically isolating the super via from an interlayer dielectric layer (the insulator layer of Shinde isolates the via from buried oxide layer 140, which is an oxide layer in a silicon-on-insulator wafer, making it a silicon oxide layer, which is a dielectric layer). Applicant should also note that the references as combined would include the inner spacer layer of Shinde in the super via of Lin and Briggs, both of which include interlayer dielectric layers which would be isolated from the super via by the inner spacer layer (Lin paragraphs (8) and (11): upper insulator layer 18, which can be made of a dielectric material; Briggs, claim 1: “a first dielectric layer”).
Regarding dependent claim 10, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, the first metallization layer, the second metallization layer and the third metallization layer are part of a back end of line (BEOL) structure of the semiconductor device (Briggs claim 1 begins: “A back-end-of-line interconnect structure having a skip-via, comprising…”, therefore the first, second, and third metallization layers disclosed in the combination of references would be a part of a BEOL structure).
Regarding independent claim 11, Briggs discloses, in Briggs claim 1, forming an Mx-1 layer (“a first metallization layer); forming a Vx-1 layer on the Mx-1 layer (“a first dielectric layer on the first metallization layer”); forming a Mx layer on the Vx-1 layer (“a second metallization layer on the first dielectric layer; a second dielectric layer on the second metallization layer”); etching a trench in the Mx layer and the Vx-1 layer; forming an inner spacer layer (“an insulating, dielectric collar in the second metallization layer around the skip-via”); forming a Vx layer on the Mx layer (“a second dielectric layer on the second metallization layer”); and forming a super via that extends from the Vx layer to the Mx-1 layer (“the skip-via extending through the second dielectric layer, second metallization layer, and first dielectric layer to the first metallization layer”). Briggs does not explicitly disclose etching a trench in the Mx layer and the Vx-1 layer; that the inner spacer layer is on sidewalls of an interlayer dielectric layer in the Mx layer and the Vx-1 layer; forming a sacrificial layer in the Mx layer and the Vx-1 layer between the inner spacer layer; forming a Mx+1 layer on the Vx layer; and removing the sacrificial layer.
However, in the same field of endeavor, Lin discloses, in Lin FIG. 1-3 and associated text, etching a trench in the Mx layer and the Vx-1 layer (via opening 32a goes through the upper and lower portions of insulator material 18, corresponding to Mx and Vx-1 layers respectively), an interlayer dielectric layer in the Mx layer and the Vx-1 layer (insulator material 18 may be an interlayer dielectric material (paragraphs (8) and (11)), and is present in both of the regions corresponding to Mx and Vx-1 layers), and forming a Mx+1 layer on the Vx layer (top half of insulator layer 26, including conductive material 40 (Mx+1 layer) is formed on the lower half of insulator layer 26 (Vx layer)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Briggs and Lin to provide a super via extending from a first metallization layer to a third metallization layer because doing so would connect the via to functional structures in the third metallization layer with “improved resistance characteristics… [and] efficiency in the chip manufacturing process” (Lin paragraph (3)). It would also provide an insulating dielectric layer between the super via and features within the Mx and Vx-1 layers, preventing unwanted shorts and improving reliability of the semiconductor device made by the referenced method. Finally, it would provide a trench which can be filled to form the super via in a dual damascene process (Lin paragraph (12)), reducing the number of metal deposition steps required, making the method more efficient.
Additionally, in the same field of endeavor, Shinde discloses in Shinde FIG. 7 and associated text forming an inner spacer layer on sidewalls of a via (step 405, oxidization of TSV sidewalls forms the inner spacer layer), forming a sacrificial layer in the Mx layer and the Vx-1 layer between the inner spacer layer (step 405, TSV is filled with amorphous silicon), and removing the sacrificial layer (step 408, amorphous silicon is removed from TSV).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Briggs, Lin, and Shinde to provide an inner spacer layer on sidewalls of the aforementioned insulating dielectric layer in the Mx and Vx-1 layers to insulate these layers from the super via. Additionally, it would provide a method of making a semiconductor device that uses a sacrificial layer filling the via to enable processing steps on the top surface of the via such as Shinde step 407 before removal of the sacrificial layer to allow subsequent filling of the via with conductive material such as in Shinde step 409.
Regarding dependent claim 12, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text the super via has a stepped profile (visible steps in skip via 32a near top of capping layer 24 and bottom of conductive material 40).
Regarding dependent claim 13, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text forming a first cap layer (capping layer 16) between the first metallization layer and the inner spacer layer (the references as combined would have the claimed arrangement).
Regarding dependent claim 14, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 1 and associated text forming an opening in the first cap layer to expose a portion of the Mx-1 layer (a portion of capping layer 16 is removed and wiring structures 14 are exposed).
Regarding dependent claim 15, Briggs, as modified by Lin and Shinde, further discloses in Lin FIG. 3 and associated text forming a second cap layer between the Vx layer and the Mx layer (capping layer 24 is between the lower region of insulator layer 26 (Vx) and the upper region of insulator layer 18 (Mx)).
Regarding dependent claim 16, Briggs, as modified by Lin and Shinde, further discloses in Shinde FIG. 7 and associated text the sacrificial layer includes at least one of a-SiGe, a-Si, SeGe or TiO2 (step 405, the sacrificial layer is amorphous silicon or a-Si).
Regarding dependent claim 17, Briggs, as modified by Lin and Shinde, further discloses in Shinde FIG. 3 the super via has a stepped profile at an interface between the Vx layer and the Mx layer (a step is visible in the via between M1 (corresponding to Mx) and the via layer (corresponding to Vx) on it within metal-1 layer 121). Please refer to the following figure:
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Regarding dependent claim 18, Briggs, as modified by Lin and Shinde, further discloses a top surface of the inner spacer layer is coplanar with the top surface of the second cap layer (the references as combined would have the claimed arrangement of inner spacer layer and second cap layer).
Further, before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to form the inner spacer layer in various arrangements with the second cap layer including those in which its top surface would be coplanar to the top surface of the second cap layer because Applicant has not disclosed that the coplanar relationship between the top surfaces of the two features provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with the top surface of the inner spacer layer at any other position above the top surface of the Mx layer because the inner spacer layer’s only function, as disclosed, is to insulate and protect the dielectric layers in the Mx and Vx-1 layers during etching processes, which can be accomplished without the claimed arrangement. Therefore, it would have been an obvious matter of design choice to form these features such that a top surface of the inner spacer layer is coplanar with the top surface of the second cap layer.
Regarding dependent claim 19, Briggs, as modified by Lin and Shinde, further discloses the inner spacer layer comprises a dielectric material (Shinde paragraph (26): the insulator layer is SiO2, which is well-known in the art to be a dielectric material), the inner spacer layer electrically isolating the super via from an interlayer dielectric layer (the insulator layer of Shinde isolates the via from buried oxide layer 140, which is an oxide layer in a silicon-on-insulator wafer, making it a silicon oxide layer, which is a dielectric layer). Applicant should also note that the references as combined would include the inner spacer layer of Shinde in the super via of Lin and Briggs, both of which include interlayer dielectric layers which would be isolated from the super via by the inner spacer layer (Lin paragraphs (8) and (11): upper insulator layer 18, which can be made of a dielectric material; Briggs claim 1: “a first dielectric layer”).
Regarding dependent claim 20, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, the Mx-1 layer, the Vx-1 layer, the Mx layer, the Vx layer and the Mx+1 layer are part of a back end of line (BEOL) structure of the semiconductor device (Briggs claim 1 begins: “A back-end-of-line interconnect structure having a skip-via, comprising…”, therefore the first, second, and third metallization layers disclosed in the combination of references would be a part of a BEOL structure).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20120080795 A1, a patent application disclosing via openings with a spacer layer formed within and on the sidewalls of an interlayer dielectric layer.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897