DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 5/10/2026, in which: claim(s) 1, 11, 15, and 16 is/are amended; and the rejection of the claims are traversed. Claim(s) 1-20 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed 5/10/2026, with respect to the rejection(s) of claim(s) 5 have been fully considered but they are not persuasive.
Regarding claim 5, Applicant’s remarks claim that the previous rejection of claim 5 alleges that the limitations are not supported by the specification (page 3, para 1). Examiner believes this to be a misinterpretation of the rejection. Claim 5 is rejected on the basis of 35 U.S.C. 112(d) as being improper for failing to further limit the subject matter of the claim on which it depends, not for lack of support in the specification. The use of terms “Mx-1 layer”, “Mx layer”, and “M-x+1 layer” to refer to their corresponding metallization levels/layers is supported in the specification in [0031], [0034], and [0039], as stated in Applicant’s remarks. Rather, the rejection, as previously set forth, states “‘Mx-1 layer’, ‘Mx layer’, and ‘M-x+1 layer’ are not explicitly defined in the specification”, not to indicate a lack of support for said terms or their claimed relation to the claimed first through third metallization layers, but to indicate that no explicit definition is given to these terms, which are therefore interpreted according to their plain meaning. "Since there is a presumption that claim terms are given their plain meaning, and the use of special definitions is an exception, the applicant must point to where the specification as filed provides a clear and intentional use of a special definition for the claim term to be treated as having a special definition" (MPEP 2173.01). In light of this interpretation, “Mx-1 layer”, “Mx layer”, and “M-x+1 layer” appear only to be terminology without any structural limitations, referring back to their corresponding metallization levels/layers and their positional relationship, which is already limited in claim 1 on which claim 5 depends. The limitations of claim 5 only provide new labels for the first through third metallization layers and do not further limit the subject matter of the claims on which claim 5 depends. Therefore, the rejection is proper and maintained as previously set forth.
Applicant’s arguments with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lin et al. (US 10026687 B1, hereinafter Lin), and further in view of Wang et al. (US 10170539 B2, hereinafter Wang).
Claim Objections
Claims 1, 11, 15, and 16 are objected to because of the following informalities: each of claims 1, 11, 15, and 16 are presented as “currently amended”. However, no markings have been made to indicate the changes. Per MPEP 1893.01(a)(4): all "currently amended" claims must include markings to indicate the changes made relative to the immediate prior version of the claims: underlining to indicate additions, strike-through or double brackets for deletions (see 37 CFR 1.121(c) for further details regarding the format of claim amendments). Please indicate changes accordingly in amended claims submitted henceforth.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "the interlayer dielectric layer". There is insufficient antecedent basis for this limitation in the claim. Claim 11, on which claim 19 depends, claims first through third interlayer dielectric layers, making it unclear as to which ILD “the interlayer dielectric layer” refers without an ordinal number to indicate or whether it is intended to refer to a separate element entirely. For the purpose of examination, the examiner interprets the claim as reciting “[[the]] --an interlayer dielectric layer”.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 5 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 5 states “the first metallization layer is a Mx-1 layer, the second metallization layer is a Mx layer, and the third metallization layer is a Mx+1 layer”. “Mx-1 layer”, “Mx layer”, and “M-x+1 layer” are not explicitly defined in the specification. However, as interpreted in light of the specification and broadest reasonable interpretation, the terms refer to metallization layers with relative positional indicators, therefore e.g. “the second metallization layer is a Mx layer” is interpreted as “the second metallization layer is a metallization layer on/above the first metallization layer/M-x-1 layer”, which fails to further limit the subject matter of claim 1 on which it depends because the second metallization layer is already limited to a metallization layer on the first metallization layer. Similar reasoning applies to the limitations on the first and third metallization layers. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Briggs et al. (U.S. Patent No. 10083905, hereinafter Briggs), and further in view of Lin et al. (US 10026687 B1, hereinafter Lin) and Shinde et al. (US 9190392 B1, hereinafter Shinde).
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 10026687 B1, hereinafter Lin), and further in view of Wang et al. (US 10170539 B2, hereinafter Wang).
Regarding independent claim 1, Lin discloses, in Lin FIG. 3 and associated text, a semiconductor device comprising: a first metallization layer (wiring structures 14 provided in an insulator material 12), the first metallization layer including a first interlayer dielectric layer (ILD) (insulator material 12) and at least one first metallization (wiring structures 14); a second metallization layer formed on the first metallization layer (top half of insulator layer 18, including wiring structures 20), the second metallization layer including a second ILD (insulator layer 18) and at least one second metallization (wiring structures 20); a third metallization layer formed on the second metallization layer (top half of insulator layer 26, including conductive material 40), the third metallization layer including a third ILD (insulator layer 26) and at least one third metallization (conductive material 40); a super via (skip via 32a) extending from the first metallization layer (insulator material 12 including wiring structure 14) to the third metallization layer (skip via 32a connects wiring structure 14 to conductive material 40). Lin does not explicitly disclose an inner spacer layer formed in contact with the second ILD and the super via and extending from the second metallization layer to the first metallization layer.
However, in the same field of endeavor, Wang discloses in Wang FIG. 2G and associated text an inner spacer layer formed in contact with the super via and extending from the second metallization layer to the first metallization layer (first spacer 32 contacts via hole 24 and extends from second conductive layer 16 - an upper portion of which is interpreted as corresponding to the second metallization layer – to first conductive layer 12, corresponding to the first metallization layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Lin with the inner spacer of Wang to provide isolation between the second metallization layer and the super via (Wang (25)), where the combined structure would be such that the spacer layer is formed in contact with the second ILD since a portion of Lin’s insulator layer 18 is exposed by the via and would thus make contact with Wang’s first spacer 32 when formed in the via of the combined invention.
Regarding dependent claim 2, Lin, as modified by Wang, further discloses in Lin FIG. 3 and associated text the super via has a stepped profile (visible steps in skip via 32a near top of capping layer 24 and bottom of conductive material 40).
Regarding dependent claim 3, Lin, as modified by Wang, further discloses in Lin FIG. 3 and associated text a first cap layer (capping layer 16) formed between the first metallization layer and the inner spacer layer (the references as combined would have the claimed arrangement, similar to annotated Wang FIG. 2G below).
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Regarding dependent claim 4, Lin, as modified by Wang, further discloses, in FIG. 3 and associated text, a Vx-1 layer between the first metallization layer and the second metallization layer (lower portion of insulator layer 18); and a Vx layer between the third metallization layer and the second metallization layer (lower portion of insulator layer 26).
Regarding dependent claim 5, Lin, as modified by Wang, further discloses the first metallization layer is a Mx-1 layer, the second metallization layer is a Mx layer, and the third metallization layer is a Mx+1 layer (by the aforementioned interpretation of this claim, the first, second, and third metallization layers are inherently Mx-1, Mx, and Mx-1 layers because they are metallization layers). Applicant should also note that Lin uses substantially similar terminology “M0”, “M1”, and “M2” in reference to wiring structures 14 and 20 and to anticipated wiring structures in trench 36 which corresponds to the conductive material 40 respectively (Lin (10), (12)).
Regarding dependent claim 6, Lin, as modified by Wang, further discloses, in Lin FIG. 3 and associated text, the super via includes portions of the Vx layer, the Mx layer and the Vx-1 layer (skip via 32a is through (“includes”) portions of 26, 20, and 18, corresponding to the Vx layer, the Mx layer and the Vx-1 layer, respectively).
Regarding dependent claim 7, Lin, as modified by Wang, further discloses in Lin FIG. 3 the super via has a stepped profile at an interface between the Vx layer and the Mx layer (a step is visible in the corresponding portion of the figure as shown in the annotated Lin FIG. 3 below)
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Regarding dependent claim 8, Lin, as modified by Wang, further discloses in Lin FIG. 3 and associated text a second cap layer formed between the second metallization layer and the third metallization layer (capping layer 24 is between wiring structure 20 and conductive material 40).
Regarding dependent claim 9, Lin, as modified by Wang, further discloses the inner spacer layer comprising a dielectric material (Wang paragraph (24): the insulative layer 30, which makes up first spacer 32, is SiO2, which is well-known in the art to be a dielectric material), the inner spacer layer electrically isolating the super via from an interlayer dielectric layer (as interpreted above, the references as combined include Wang’s first spacer 32 on the sidewalls of Lin’s skip via 32a, electrically isolating skip via 32a from interlaying dielectric layers including at least portions of Lin’s insulator layer 18).
Regarding dependent claim 10, Lin, as modified by Wang, further discloses, in Lin, the first metallization layer, the second metallization layer and the third metallization layer are part of a back end of line (BEOL) structure of the semiconductor device (structure 10 can be a BEOL structure (Lin (7))).
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, and further in view of Wang and Shinde et al. (US 9190392 B1, hereinafter Shinde).
Regarding independent claim 11, Lin discloses, in Lin FIG. 3 and associated text, forming an Mx-1 layer, the Mx-1 layer including a first interlayer dielectric layer (ILD) and at least one first metallization (wiring structures 14 provided in an insulator material 12); forming a Vx-1 layer on the Mx-1 layer, the Vx-1 layer including a second ILD and at least one second metallization (lower portion of insulator layer 18 and cobalt 38); forming a Mx layer on the Vx-1 layer, the Mx layer including a third ILD and at least one third metallization (upper portion of insulator layer 18 and cobalt 38 and wiring structures 20); etching a trench in the Mx layer and the Vx-1 layer (skip via 32a is a trench through the portions of 18 corresponding to the Mx and Vx-1 layers formed by an etching process (Lin (12))); forming a Vx layer on the Mx layer (lower portion of insulator layer 26); forming a Mx+1 layer on the Vx layer (upper portion of insulator layer 26 and conductive material 40); and forming a super via that extends from the Vx layer to the Mx-1 layer (skip via 32a). Lin does not explicitly disclose forming an inner spacer layer in contact with the third ILD in the Mx layer and the second ILD in the Vx-1 layer; forming a sacrificial layer in the Mx layer and the Vx-1 layer between the inner spacer layer; removing the sacrificial layer; or wherein the inner spacer layer is in contact with the super via, and extends from the Vx-1 layer to the Vx layer.
However, in the same field of endeavor, Wang discloses in Wang FIG. 2G and associated text forming an inner spacer layer in the Mx layer and the Vx-1 layer, wherein the inner spacer layer is in contact with the super via- (first spacer 32 contacts via hole 24 and extends from second conductive layer 16 - an upper portion of which is interpreted as corresponding to the Mx layer – to first conductive layer 12, corresponding to the first metallization layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Lin with the inner spacer of Wang to provide isolation between the second metallization layer and the super via (Wang (25)). The combined structure would be such that the spacer layer extends from the Vx-1 layer to the Vx layer and, since the structure of Wang’s first spacer 32 extends from the bottom of dielectric layer 14 to the top of cap layer 18, corresponding to Lin’s capping layers 16 and 24 which are adjacent to the structures previously interpreted as corresponding to the Vx-1 and Vx layers, and one of ordinary skill in the art would be motivated to preserve the structure of Wang’s first spacer 32 as much as possible when forming it in Lin’s skip via 32a. Additionally, as combined the spacer layer is formed in contact with the third ILD in the Mx layer and the second ILD in the Vx-1 layer since a portion of Lin’s insulator layer 18 is exposed by the via and would thus make contact with Wang’s first spacer 32.
Additionally, in the same field of endeavor, Shinde discloses in Shinde FIG. 7 and associated text forming a sacrificial layer in the Mx layer and the Vx-1 layer between the inner spacer layer (step 405, TSV, which has oxidized sidewalls corresponding to an inner spacer layer, is filled with amorphous silicon), and removing the sacrificial layer (step 408, amorphous silicon is removed from TSV).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Lin, as modified by Wang, to provide a method of making a semiconductor device that uses a sacrificial layer filling the via to enable processing steps on the top surface of the via such as Shinde step 407 before removal of the sacrificial layer to allow subsequent filling of the via with conductive material such as in Shinde step 409.
Regarding dependent claim 12, Lin, as modified by Wang and Shinde, further discloses in Lin FIG. 3 and associated text the super via has a stepped profile (visible steps in skip via 32a near top of capping layer 24 and bottom of conductive material 40, as shown in the annotated Lin FIG. 3 below).
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Regarding dependent claim 13, Lin, as modified by Wang and Shinde, further discloses in Lin FIG. 3 and associated text forming a first cap layer (capping layer 16) between the first metallization layer and the inner spacer layer (the references as combined would have the claimed arrangement, similar to annotated Wang FIG. 2G below).
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Regarding dependent claim 14, Lin, as modified by Wang and Shinde, further discloses in Lin FIG. 1 and associated text forming an opening in the first cap layer to expose a portion of the Mx-1 layer (a portion of capping layer 16 is removed and wiring structures 14 are exposed).
Regarding dependent claim 15, Lin, as modified by Wang and Shinde, further discloses in Lin FIG. 3 and associated text forming a second cap layer between the Vx layer and the Mx layer (capping layer 24 is between the lower region of insulator layer 26 (Vx) and the upper region of insulator layer 18 (Mx)).
Regarding dependent claim 16, Lin, as modified by Wang and Shinde, further discloses in Shinde FIG. 7 and associated text the sacrificial layer includes at least one of a-SiGe, a-Si, SiGe or TiO2 (step 405, the sacrificial layer is amorphous silicon or a-Si).
Regarding dependent claim 17, Lin, as modified by Wang and Shinde, further discloses in Shinde FIG. 3 the super via has a stepped profile at an interface between the Vx layer and the Mx layer (visible steps in skip via 32a near top of capping layer 24 and bottom of conductive material 40, as shown in the annotated Lin FIG. 3 below).
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Regarding dependent claim 18, Lin, as modified by Wang and Shinde, further discloses in Wang FIG. 2G and associated text, a top surface of the inner spacer layer is coplanar with the top surface of the second cap layer (first spacer 32 is coplanar with capping layer 18).
Further, before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to form the inner spacer layer in various arrangements with the second cap layer including those in which its top surface would be coplanar to the top surface of the second cap layer because Applicant has not disclosed that the coplanar relationship between the top surfaces of the two features provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with the top surface of the inner spacer layer at any other position above the top surface of the Mx layer because the inner spacer layer’s only function, as disclosed, is to insulate and protect the dielectric layers in the Mx and Vx-1 layers during etching processes, which can be accomplished without the claimed arrangement. Therefore, it would have been an obvious matter of design choice to form these features such that a top surface of the inner spacer layer is coplanar with the top surface of the second cap layer.
Regarding dependent claim 19, Lin, as modified by Wang and Shinde, further discloses the inner spacer layer comprises a dielectric material (Wang paragraph (24): the insulative layer 30, which makes up first spacer 32, is SiO2, which is well-known in the art to be a dielectric material), the inner spacer layer electrically isolating the super via from an interlayer dielectric layer (as interpreted above, the references as combined include Wang’s first spacer 32 on the sidewalls of Lin’s skip via 32a, electrically isolating skip via 32a from interlaying dielectric layers including at least portions of Lin’s insulator layer 18).
Regarding dependent claim 20, Briggs, as modified by Lin and Shinde, further discloses, in Briggs claim 1, the Mx-1 layer, the Vx-1 layer, the Mx layer, the Vx layer and the Mx+1 layer are part of a back end of line (BEOL) structure of the semiconductor device (structure 10 can be a BEOL structure (Lin (7))).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20120080795 A1, a patent application disclosing via openings with a spacer layer formed within and on the sidewalls of an interlayer dielectric layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Fri 7:30 a.m. - 5:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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