DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12, and 15 are rejected under 35 U.S.C. 102 as being anticipated by Yu et al.; (US 2023/0178632 A1; hereinafter Yu )
Regarding claim 1, Yu teaches a method for forming a precursor semiconductor device structure, the method comprising: forming, on a substrate ( Fig. 1 substrate #104), an initial layer stack comprising a sacrificial layer ( [0034] the initial stages of fabrication by alternatively growing silicon and silicon germanium layers) of a first semiconductor material ( [0034] One of the Si or SiGe layers are sacrificial layers) and, over the sacrificial layer ( Fig. 1 first sacrificial layers #106 ) , a channel layer ( Fig. 4A semiconductor layers #402) of a second semiconductor material ( [0035] The final channel is grown later, after removing the silicon germanium sacrificial layers); forming a set of fin structures ( [0045] Fig. 2A, portions of the nanosheet stacks #102 can be removed to expose a surface of the substrate #104 and to define the nanosheet stack width. This process is sometimes referred to as a fin cut. ) by patterning trenches in the initial layer stack (Fig. 7A a shallow trench isolation (STI) #704), each fin structure ( [0045] a fin cut ) comprising a respective sacrificial layer of the first semiconductor material ( Fig. 2A #106 ) and a respective channel layer of the second semiconductor material ( [0048] semiconductor layers #402 (also referred to as channel layers) are formed on the exposed surfaces (top and bottom surfaces) of the second sacrificial layers #108 ) ; forming at least one anchoring structure ( Fig. 2B #202 ) extending across the set of fin structures ( Fig. 3B #102 ), and while the channel layers ( Fig. 3B #108 ) are anchored by the at least one anchoring structure ( Fig. 3B #202 ): removing the sacrificial layers ( Fig. 1 first sacrificial layer #106 ) of each fin structure ( [0045] a fin cut ) by a selective etching ( [0047] The first sacrificial layer #106 and the thick sacrificial layer #110 can be selectively removed using a wet etch, a dry etch, or a combination of wet and/or dry etches) of the first semiconductor material ( [0034] One of the Si or SiGe layers are sacrificial layers ), thereby forming a longitudinal cavity ( Fig. 4B cavity is under #402 ) underneath the channel layer (Fig. 4B #402 ) of each fin structure ( [0045] a fin cut ), and depositing an insulating material to fill the cavities ( Fig. 6B a dielectric layer #602 ), wherein the insulating material is formed of a flowable dielectric ( [0046] Any known manner of forming the dielectric layer #202 can be utilized, such as, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD ); and subsequently recessing the at least one anchoring structure ( Fig. 8 no anchoring structures present) and the insulating material ( Fig. 8 #602) to a level below the cavities such that the insulating material ( Fig. 8 #602 ) remains in the cavities to form insulating layers underneath the channel layers ( Fig. 8 insulating material #602 fills cavity underneath the channel layers #402) of each fin structure ( [0045] a fin cut ).
Regarding claim 2, Yu teaches the method of claim 1 (as discussed above), wherein forming the at least one anchoring structure ( Fig. 2B #202 ) comprises depositing an anchoring material layer structure ( Fig. 2B #202 ) of one or more layers on the set of fin structures ( Fig. 2B fin structures #106, #108, and #110 layers ) and in the trenches ( Fig. 7A a shallow trench isolation (STI) #704 ), and patterning the anchoring material layer structure ( Fig. 7B #202 ) to form the at least one anchoring structure ( Fig. 7B #202 ).
Regarding claim 3, Yu teaches the method of claim 2 (as discussed above), wherein patterning the anchoring material layer structure ( [0046] Any known manner of forming the dielectric layer #202 can be utilized, such as, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD) comprises forming at least one mask line extending across the set of fin structures ( flowable CVD utilizes a mask ) and etching the anchoring material layer structure using the at least one mask line as an etch mask ( flowable CVD utilizes a mask for patterning ) such that fin structure side surface portions not masked by the at least one mask line are exposed ( [0056] sidewalls of the nanosheet stacks #102 are revealed (exposed) ), wherein removing the sacrificial layers comprises etching the first semiconductor material from the exposed side surface portions of each fin structure ( [0047] The first sacrificial layers #106 and the thick sacrificial layer #110 can be selectively removed using a wet etch, a dry etch, or a combination of wet and/or dry etches. ), and wherein depositing the insulating material ( Fig. 8 #602 ) comprises depositing the insulating material such that the trenches between the fin structures and the cavities ( Fig. 4B cavity is under #402 ) are filled with the insulating material (Fig. 8 #602).
Regarding claim 4, Yu teaches the method of claim 2 (as discussed above), further comprising forming a fin cut mask ( CVD utilizes a mask ) over the anchoring material layer structure ( Fig. 2B #202 ), wherein patterning the anchoring material layer structure ( [0046] Any known manner of forming the dielectric layer #202 can be utilized, such as, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD) comprises etching ( flowable CVD involves etching steps ) the anchoring material layer structure ( Fig. 2B #202 ) using the fin cut mask as an etch mask ( flowable CVD utilizes a mask for etching), wherein the patterned anchoring material layer structure ( Fig. 2B #202) forms part of the anchoring structure ( Fig. 7B #202), wherein subsequent to patterning the anchoring material layer structure ( Fig. 2B #202 ), removing parts of each fin structure by etching ( [0047] The first sacrificial layers #106 and the thick sacrificial layer #110 can be selectively removed using a wet etch, a dry etch, or a combination of wet and/or dry etches ) the fin structures using the fin cut mask ( flowable CVD utilizes a mask for etching) as an etch mask ( flowable CVD utilizes a mask for patterning ), thereby forming a set of cut fin structures ( Fig. 4B fin structures are cut and channel edges #402 are exposed ) covered by the anchoring structure ( Fig. 4B #202) and having exposed end surfaces ( Fig. 4B #402 edges are exposed), wherein removing the sacrificial layers ( Fig. 2B #106) comprises etching ( [0047] the first sacrificial layers #106 and the thick sacrificial layer 3110 are removed to expose surfaces of the second sacrificial layer #108 ) the first semiconductor material ( Fig. 2B #106) from the exposed end surfaces ( Fig. 2A ) of each fin structure ( [0045] a fin cut ).
Regarding claim 5, Yu teaches the method of claim 2 ( as discussed above ), wherein the anchoring material layer structure ( Fig. 2B #202 ) comprises an insulating fill layer ( [0046] the dielectric layer #202 ) deposited to fill the trenches ( Fig. 7A a shallow trench isolation (STI) #704 ).
Regarding claim 6, Yu teaches the method of claim 5 (as discussed above), wherein patterning the anchoring material layer structure ( Fig. 2B #202 ) comprises forming at least one mask line extending across the set of fin structures ( flowable CVD utilizes a mask ) and etching ( flowable CVD utilizes a mask for etching ) the anchoring material layer structure ( Fig. 2B #202 ) using the at least one mask line as an etch mask ( flowable CVD utilizes a mask for etching ) such that fin structure side surface portions not masked by the at least one mask line are exposed ( Fig. 2A fin stack is exposed), wherein removing the sacrificial layers ( Fig. 2B #106 ) comprises etching the first semiconductor material ( [0047] The first sacrificial layers #106 and the thick sacrificial layer #110 can be selectively removed using a wet etch, a dry etch, or a combination of wet and/or dry etches ) from the exposed side surface portions of each fin structure ( Fig. 2A stack on the substrate), and wherein depositing the insulating material ( Fig. 8 #602) comprises depositing the insulating material such that the trenches ( Fig. 7A a shallow trench isolation (STI) #704 ) between the fin structures ( Fig. 7A area between #704 columns ) and the cavities ( Fig. 7A dielectric layer #602 ) are filled with the insulating material ( Fig. 7A #602 ), and wherein recessing the at least one anchoring structure ( Fig. 7B #202 ) and the insulating material (Fig. 7B #602) comprises simultaneously recessing the insulating fill layer ( Fig. 7B #602 ) and the insulating material to the level below the cavities ( Fig. 7A #602 ), wherein said level is such that a thickness portion of the insulating fill layer ( Fig. 7B #602) and the insulating material remains to form shallow trench isolation in a bottom part of the trenches ( Fig. 7A #704).
Regarding claim 7, Yu teaches the method of claim 5 (as discussed above), wherein forming the at least one anchoring structure ( Fig. 2B #202) comprises depositing an anchoring material layer structure ( Fig. 2B #202) of one or more layers on the set of fin structures ( Fig. 2B structure between the #202 columns) and in the trenches ( Fig. 7A #704), and patterning the anchoring material layer structure ( Fig. 2B #202) to form the at least one anchoring structure ( Fig. 7B #202); and wherein the method further includes forming a fin cut mask ( flowable CVD utilizes a mask) over the anchoring material layer structure ( Fig. 2B #202), wherein patterning the anchoring material layer structure comprises etching ( flowable CVD involves etching) the anchoring material layer structure ( Fig. 2B #202) using the fin cut mask as an etch mask ( flowable CVD utilizes a mask for etching), wherein the patterned anchoring material layer structure ( Fig. 2B #202) forms part of the anchoring structure ( Fig. 7B #202), wherein subsequent to patterning the anchoring material layer structure ( Fig. 2B #202), removing parts of each fin structure by etching (flowable CVD utilizes a mask for etching) the fin structures using the fin cut mask as an etch mask ( flowable CVD utilizes a mask for etching), thereby forming a set of cut fin structures ( Fig. 4B fin structures are cut and channel edges #402 are exposed ) covered by the anchoring structure and having exposed end surfaces ( Fig. 4B #202 ), wherein removing the sacrificial layers ( Fig. 2B #106 ) comprises etching the first semiconductor material ( [0047] The first sacrificial layers #106 and the thick sacrificial layer #110 can be selectively removed using a wet etch, a dry etch, or a combination of wet and/or dry etches ) from the exposed end surfaces ( Fig. 2A fin stack is exposed ) of each fin structure ( Fig. 2A stack on top of the substrate ) wherein recessing the anchoring structure ( Fig. 2B #202) and the insulating material ( Fig. 7B #602) comprises simultaneously recessing the insulating fill layer and the insulating material to the level below the cavities, wherein said level is such that a thickness portion ( [0053] The dielectric layer #602 can be formed to a thickness of about 2 nm to about 15 nm) of the insulating fill layer ( Fig. 7B #602) remains to form shallow trench isolation in a bottom part of the trenches ( Fig. 7A #704).
Regarding claim 8, Yu teaches the method of claim 6 (as discussed above), wherein the insulating fill layer ( Fig. 7B #602) is formed of a same material as the insulating material ( [ 0052] The dielectric layer #602 can be made of any suitable dielectric material, such as, for example, oxides, a low-k dielectric, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN ).
Regarding claim 9, Yu teaches the method of claim 2 (as discussed above), wherein the anchoring material layer structure ( Fig. 11 interlayer dielectric #1104) comprises an insulating liner layer ( Fig. 11 liner #1102 ) conformally deposited on the fin structures ( Fig. 11 #1102 covers the fin structure ) and in the trenches ( Fig. 11 #1102 fills the trenches between #1104 and the fin structure ).
Regarding claim 10, Yu teaches the method of claim 9 ( as discussed above), wherein the anchoring material layer structure ( Fig. 11 #1104 ) comprises an insulating fill layer ( Fig. 11 #602) deposited to fill the trenches ( [0083] portions of the ILD #1104 are removed to form source/drain contact trenches), and wherein the insulating fill layer (Fig. 11 #602) is deposited on the liner layer ( Fig. 11 #1104).
Regarding claim 11, Yu teaches the method of claim 9 ( as discussed above), wherein recessing the at least one anchoring structure ( Fig. 11 #1104) further comprises removing portions of the liner layer present above said level by etching ( [0083] The ILD #1104 can be patterned using a wet etch, a dry etch, or a combination of sequential wet and/or dry etches).
Regarding claim 12, Yu teaches the method of claim 1 ( as discussed above), wherein the insulating material (Fig. 2B #202) is a flowable oxide ( [0046] The dielectric layer #202 can be made of any suitable dielectric material, such as for example, oxides, a low-k dielectric, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN. Any known manner of forming the dielectric layer #202 can be utilized such as for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PCD).
Regarding claim 15, Yu teaches a method for forming a semiconductor device ( [0038] a final semiconductor device ), the method comprising: forming a precursor semiconductor device structure ( Fig. 13 semiconductor structure #100 ) in accordance with any one of the preceding claims ( as discussed above); and along one or more of the fin structures ( Fig. 13 central layered stack ), forming a gate structure ( Fig. 13 an active gate #1304 ) and source and drain regions ( Fig. 13 source and drain regions #1202 ).
Response to Arguments
Applicant's arguments filed 01/30/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies ( i.e., Structures which are described in, for example, the paragraphs [0036]-[0042], and [0070]-[0071] and shown in FIGS. 6a and 6b. FIGS. 6a and 6b illustrate an example of the (patterned) liner layer 120 defining an anchoring structure extending across the cut fin structures 110 along the Y-direction and being coextensive with the longitudinal dimension of the cut fin structures 110. The prior art does not teach or suggest these features or the configuration recited by the claims. ) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to the first argument, Yu discloses forming, on a substrate (Fig. 1 #104 ) an initial stack layer comprising a sacrificial layer (Fig. 1 #106) and further elaborates in paragraph [0034] that in the initial stages of fabrication these layers are grown and include the sacrificial layer. The channel layer is then added after removing the sacrificial layer ( which is why it is called a sacrificial layer). In response to the second argument, Yu discloses forming a set of fin structures by patterning trenches in the initial layer stack which is referenced in paragraph [0045] and shown in Fig. 2A. The fin cut from Fig. 1 to Fig. 2A illustrates the initial stack layer modification for the fin cut. In response to the third argument, Yu clearly shows anchoring structures starting in Fig. 2B as item #202 that extend across the set of fin structures and also anchor the channel layers #108 as shown in Fig. 3B.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817