DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
At the following locations, indicated by the notation [claim(s), line(s)], please make the following changes to provide better clarity, proper grammar, or proper antecedent basis:
[3, 5] change “a dielectric layer” to “the dielectric layer”.
[5, 5] change “the first, second and third sub-stack” to “the first, second and third sub-stacks”.
[5, 14] change “the third sacrificial layer” to “a third sacrificial layer”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as lacking antecedent basis for the limitations, "a second sacrificial layer on the first sacrificial layer” (Claim 1, Lines 6-7). It is unclear the term, “the first sacrificial layer” (Claim 1, Lines 6-7), is “first sacrificial layer" (Claim 1, Line 3) of first sub-stack (Claim 1, Line 3), “first sacrificial layer” (Claim 1, Line 15) of the second sub-stack (Claim 1, Line 5), or new “first sacrificial layer" of device layer stack (Claim 1, Line 2). Claims 2-15 depend from claim 1 and inherit its deficiencies. Examiner interprets “a second sacrificial layer on the first sacrificial layer” to mean a second sacrificial layer on the first sacrificial layer of the second sub-stack.
In addition, claims 5-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as lacking antecedent basis for the limitations, "a first sacrificial layer of the first sacrificial semiconductor material on the channel layer” (Claim 5, Lines 5-6). It is unclear the term, “the channel layer” (Claim 5, Lines 5-6), is “channel layer" (Claim 1, Line 4) of first sub-stack (Claim 1, Line 3) or “channel layer” (Claim 5, Line 4) of the third sub-stack (Claim 5, Line 3). Claims 6-12 depend from claim 5 and inherit its deficiencies. Examiner interprets “a first sacrificial layer of the first sacrificial semiconductor material on the channel layer” to mean a first sacrificial layer of the first sacrificial semiconductor material on the channel layer of the third sub-stack..
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 13, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier et al. (US 20230086633) (hereafter Frougier).
Regarding claim 1, Frougier discloses a method for forming a semiconductor device, the method comprising:
forming a device layer stack (stack vertically from 112-1 to 116-6 in Fig. 2B) on a substrate 102 (Fig. 2B, paragraph 0028), the device layer stack (stack vertically from 112-1 to 116-6 in Fig. 2B) comprising:
a first sub-stack (stack vertically from 116-1 to 114-2 in Fig. 2B) comprising a first sacrificial layer 116-1 (Fig. 2B, paragraph 0030) and on the first sacrificial layer 116-1 (Fig. 2B) a channel layer 114-2 (Fig. 2B, paragraph 0030) defining a topmost layer of the first sub-stack (stack vertically from 114-1 to 114-2 in Fig. 2B), and a second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B) on the first sub-stack (stack vertically from 116-1 to 114-2 in Fig. 2B) and comprising a first sacrificial layer 116-2 (Fig. 2B) defining a bottom layer of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B), and a second sacrificial layer 112-2 (Fig. 2B, paragraph 0030) on the first sacrificial layer 116-2 (Fig. 2B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B),
wherein said first sacrificial layers (116-1 and 116-2 in Fig. 2B) are formed of a first sacrificial semiconductor material (see paragraph 0035, wherein “SiGe alloy having a range of about 25% to 40% Ge”), the second sacrificial layer 112-2 (Fig. 2B) is formed of a second sacrificial semiconductor material (see paragraph 0035, wherein “SiGe alloy having a range of about 50% to about 90% Ge”), and the channel layer 114-2 (Fig. 2B) is formed of a semiconductor channel material (see paragraph 0035, wherein “Si or an SiGe alloy having a range of about 5% to about 15% Ge”), and wherein a thickness of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B) exceeds a thickness of the first sacrificial layer of the first sub-stack (stack vertically from 116-1 to 114-2 in Fig. 2B);
forming a sacrificial gate structure (120-2 and 130 in Fig. 2B, paragraph 0038) extending across (see paragraph 0039, wherein “blanket deposition of a sacrificial material such as polysilicon or amorphous silicon material to form the dummy gate electrode layer”) the device layer stack (stack vertically from 112-1 to 116-6 in Fig. 2B), the sacrificial gate structure (120-2 and 130 in Fig. 2B) comprising a sacrificial gate body 124-2 (Fig. 2B, paragraph 0038) and a first spacer 130 (Fig. 2B, paragraph 0041) on opposite sides of the sacrificial gate body 124-2 (Fig. 2B);
etching (see Fig. 3B and paragraph 0045) through the device layer stack (stack vertically from 112-1 to 116-6 in Fig. 2B) while using the sacrificial gate structure (120-2 and 130 in Fig. 3B) as an etch mask (see paragraph 0045, wherein “An etch process is utilized to recess the exposed portion of the nanosheet stack structure 110 down into the semiconductor substrate 102 according to a pattern defined by the etch mask 300, sidewall spacer 130 and sidewall liner 200 to form trenches 132”) such that portions of said layers of the device layer stack (stack vertically from 112-1 to 116-6 in Fig. 3B) are preserved underneath the sacrificial gate structure 120-2 (Fig. 3B);
subsequently, replacing (see Figs. 5B-7B) the second sacrificial layer 122-2 (Fig. 5B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 5B) with a dielectric layer (700 between 114-4 and 114-5 in Fig. 7B, paragraph 0055), comprising removing (see Fig. 6B) the second sacrificial layer 112-2 (Fig. 5B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 5B) to form a space (space between 114-4 and 114-5 in Fig. 6B) in the second sub-stack by selectively etching (see paragraph 0052, wherein “the etch chemistry and process may be selective to the materials of the semiconductor substrate 102, STI layer 104, nanosheet channel layers 114, sacrificial nanosheet layers 116, sidewall spacer 130 and gate capping layers 126”) the second sacrificial semiconductor material 112-2 (Fig. 5B), and thereafter filling the space (space between 114-4 and 114-5 in Fig. 6B) with a first dielectric material (700 between 114-4 and 114-5 in Fig. 7B; and see paragraph 0055, wherein “SiN, SiBCN, SiCON, or any other type of dielectric material (e.g., a low-k dielectric material having a k of less than 5) which is commonly used to form insulating nanosheet sidewall spacers of FET devices”);
forming recesses (opening vertically between 114 in Fig. 6B) in the device layer stack (stack vertically from 112-1 to 116-6 in Fig. 5B) by laterally etching back (see paragraph 0053, wherein “The exposed sidewall surfaces of sacrificial nanosheet layers 116 are laterally etched to form recesses in the sidewalls of the nanosheet stack structure 110”) end surfaces of the first sacrificial layers (116-1 and 116-2 in Fig. 5B) of the first (stack vertically from 116-1 to 114-2 in Fig. 5B) and second sub-stacks (stack vertically from 116-2 to 116-4 in Fig. 5B) from opposite sides of the sacrificial gate structure 122-2 (Fig. 5B);
forming inner spacers (portions of 700 contacting sidewalls of 116 in Fig. 7B) in the recesses (opening vertically between 114 in Fig. 6B);
subsequently, forming source and drain regions (802 and 804 in Fig. 8B, paragraph 0057) by epitaxially growing semiconductor material (see paragraph 0060) on end surfaces of the channel layer 114-2 (Fig. 8B) exposed at opposite sides of the sacrificial gate structure (120-2 and 130 in Fig. 8B);
subsequently, forming a gate trench (opening between 130 in Fig. 11B) by removing (see Fig. 11B) the sacrificial gate body 124-2 (Fig. 10B);
removing (see Fig. 11B) the first sacrificial layer (116-1 and 116-2 in Fig. 10B) of the first (stack vertically from 116-1 to 114-2 in Fig. 10B) and second sub-stacks (stack vertically from 116-2 to 116-4 in Fig. 10B) by selectively etching the first sacrificial semiconductor material (116-1 and 116-2 in Fig. 10B) from the gate trench (opening between 130 in Fig. 11B); and
forming a gate stack (1302, 1304, 1306, and 1308 in Fig. 13B) in the gate trench (opening between 130 in Fig. 13B) such that the gate stack (1302, 1304, 1306, and 1308 in Fig. 13B) surrounds the channel layer 114-2 (Fig. 13B).
Regarding claim 2, Frougier further discloses the method of claim 1, wherein said act of replacing (see Figs. 5B-7B) the second sacrificial layer 122-2 (Fig. 5B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 5B) with a dielectric layer (700 between 114-4 and 114-5 in Fig. 7B, paragraph 0055), is performed (see paragraph 0052, wherein “A dry or wet etch processes may be utilized to remove sacrificial nanosheet layers 112 without removing the nanosheet channel layers 114 and sacrificial nanosheet layers 116”) prior to said act (see paragraph 0053, wherein “The exposed sidewall surfaces of sacrificial nanosheet layers 116 are laterally etched to form recesses in the sidewalls of the nanosheet stack structure 110”) of forming the recesses (opening vertically between 114 in Fig. 6B).
Regarding claim 3, Frougier further discloses the method of claim 2, wherein the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 5B) comprises one or more units of a first sacrificial layer 116-2 (Fig. 5B) of the first sacrificial semiconductor material (see paragraph 0035, wherein “SiGe alloy having a range of about 25% to 40% Ge”) and a second sacrificial layer 112-2 (Fig. 5B) of the second sacrificial semiconductor material (see paragraph 0035, wherein “SiGe alloy having a range of about 50% to about 90% Ge”),
wherein the method comprises replacing (see Figs. 5B-7B) each second sacrificial layer 112-2 (Fig. 5B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 5B) with a dielectric layer (700 between 114-4 and 114-5 in Fig. 7B, paragraph 0055), wherein said act of forming recesses (opening vertically between 114 in Fig. 6B) comprises laterally etching back (see paragraph 0053, wherein “The exposed sidewall surfaces of sacrificial nanosheet layers 116 are laterally etched to form recesses in the sidewalls of the nanosheet stack structure 110”) end surfaces of each first sacrificial layer (116-1 and 116-2 in Fig. 5B) of the first (stack vertically from 116-1 to 114-2 in Fig. 5B) and second sub-stacks (stack vertically from 116-2 to 116-4 in Fig. 5B) from opposite sides of the sacrificial gate structure (120-2 and 130 in Fig. 5B), and
wherein the method comprises removing (see Figs. 5B-6B) each first sacrificial layer (116-1 and 116-2 in Fig. 5B) of the first (stack vertically from 116-1 to 114-2 in Fig. 5B) and second sub-stacks (stack vertically from 116-2 to 116-4 in Fig. 5B).
Regarding claim 4, Frougier further discloses the method of claim 1, wherein the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 5B) comprises one or more units of a first sacrificial layer 116-2 (Fig. 5B) of the first sacrificial semiconductor material (see paragraph 0035, wherein “SiGe alloy having a range of about 25% to 40% Ge”) and a second sacrificial layer 112-2 (Fig. 5B) of the second sacrificial semiconductor material (see paragraph 0035, wherein “SiGe alloy having a range of about 50% to about 90% Ge”),
wherein the method comprises replacing (see Figs. 5B-7B) each second sacrificial layer 122-2 (Fig. 5B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 5B) with a dielectric layer (700 between 114-4 and 114-5 in Fig. 7B, paragraph 0055),
wherein said act of forming recesses (opening vertically between 114 in Fig. 6B) comprises laterally etching back (see paragraph 0053, wherein “The exposed sidewall surfaces of sacrificial nanosheet layers 116 are laterally etched to form recesses in the sidewalls of the nanosheet stack structure 110”) end surfaces of each first sacrificial layer (116-1 and 116-2 in Fig. 5B) of the first (stack vertically from 116-1 to 114-2 in Fig. 5B) and second sub-stacks (stack vertically from 116-2 to 116-4 in Fig. 5B) from opposite sides of the sacrificial gate structure (120-2 and 130 in Fig. 5B), and
wherein the method comprises removing (see Figs. 5B-6B) each first sacrificial layer (116-1 and 116-2 in Fig. 5B) of the first (stack vertically from 116-1 to 114-2 in Fig. 5B) and second sub-stacks (stack vertically from 116-2 to 116-4 in Fig. 5B).
Regarding claim 5, Frougier further discloses the method of claim 4, wherein the second sub-stack further (stack vertically from 116-2 to 116-4 in Fig. 2B) comprises a third sacrificial layer 116-4 (Fig. 2B) of the first sacrificial material forming a topmost layer of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B), and wherein the device layer stack (stack vertically from 112-1 to 116-6 in Fig. 2B) further comprises a third sub-stack (stack vertically from 114-6 to 116-6 in Fig. 2B) on the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B) and comprising a channel layer 114-6 (Fig. 2B) of the channel material and forming a bottom layer 116-2 (Fig. 2B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B), and a first sacrificial layer 116-5 (Fig. 2B) of the first sacrificial semiconductor material on the channel layer 114-6 (Fig. 2B),
wherein said act of forming recesses (opening vertically between 114 in Fig. 6B) comprises laterally etching back (see Fig. 6B and paragraph 0053, wherein “The exposed sidewall surfaces of sacrificial nanosheet layers 116 are laterally etched to form recesses in the sidewalls of the nanosheet stack structure 110”) end surfaces of each first sacrificial layer (116-1 and 116-2 in Fig. 5B) of the first (stack vertically from 116-1 to 114-2 in Fig. 5B), second (stack vertically from 116-2 to 116-4 in Fig. 5B) and third sub-stack (stack vertically from 114-6 to 116-6 in Fig. 5B) and the third sacrificial layer 116-4 (Fig. 5B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 5B) vertically from opposite sides of the sacrificial gate structure (120-2 and 130 in Fig. 5B), wherein said act of forming source and drain regions (802 and 804 in Fig. 8B) further comprises epitaxially growing (see paragraph 0060) semiconductor material on end surfaces of the channel layer 114-6 (Fig. 8B) of the third sub-stack (stack vertically from 114-6 to 116-6 in Fig. 8B), exposed at opposite sides of the sacrificial gate structure (120-2 and 130 in Fig. 8B),
wherein the method comprises removing (se Fig. 6B) each first sacrificial layer (116-1, 116-2, and 116-5 in Fig. 5B) of the first (stack vertically from 116-1 to 114-2 in Fig. 5B), second (stack vertically from 116-2 to 116-4 in Fig. 5B) and third sub-stacks (stack vertically from 114-6 to 116-6 in Fig. 5B) and the third sacrificial layer 116-6 (Fig. 5B) of the third sub-stack (stack vertically from 114-6 to 116-6 in Fig. 5B), and
wherein said act of forming a gate stack (1302, 1304, 1306, and 1308 in Fig. 13B) comprises forming the gate stack (1302, 1304, 1306, and 1308 in Fig. 13B) in the gate trench (opening between 130 in Fig. 13B) such that the gate stack (1302, 1304, 1306, and 1308 in Fig. 13B) surrounds the channel layer 114-2 (Fig. 13B) of the first sub-stack (stack vertically from 116-1 to 114-2 in Fig. 13B), each dielectric layer 700-2 (Fig. 13B) of the second sub-stack (stack vertically from 114-6 to 116-6 in Fig. 13B), and the channel layer 114-6 (Fig. 13B) of the third sub-stack (stack vertically from 114-6 to 116-6 in Fig. 13B).
Regarding claim 6, Frougier further discloses the method of claim 5, wherein the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B) comprises exactly one unit of a first sacrificial layer 116-2 (Fig. 2B) of the first sacrificial semiconductor material and a second sacrificial layer 112-2 (Fig. 2B) of the second sacrificial semiconductor material, and the third sacrificial layer 116-4 (Fig. 2B) of the first sacrificial semiconductor material on said one unit 116-2 (Fig. 2B).
Regarding claim 13, Frougier further discloses the method of claim 1, wherein the first sub-stack (stack vertically from 116-1 to 114-2 in Fig. 2B) comprises one or more units of a first sacrificial layer 116-1 (Fig. 2B) of the first sacrificial semiconductor material (see paragraph 0035, wherein “SiGe alloy having a range of about 25% to 40% Ge”) and a channel layer 114-2 (Fig. 2B) of the channel material (see paragraph 0035, wherein “Si or an SiGe alloy having a range of about 5% to about 15% Ge”) on the first sacrificial layer 116-1 (Fig. 2B).
Regarding claim 14, Frougier further discloses the method of claim 1, wherein the channel material (see paragraph 0035, wherein “Si or an SiGe alloy having a range of about 5% to about 15% Ge”) is Si1-xGex,, the first sacrificial material (see paragraph 0035, wherein “SiGe alloy having a range of about 25% to 40% Ge”) is Si1-yGey and the second sacrificial material (see paragraph 0035, wherein “SiGe alloy having a range of about 50% to about 90% Ge”) is Si1-zGez, wherein 0 ≤ x < y < z.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier as applied to claim 6 above, and further in view of Yu et al. (US 2023/0178632) (hereafter Yu).
Regarding claim 7, Frougier discloses the method of claim 6, however Frougier does not disclose the second sacrificial layer of the second sub-stack has a greater thickness than the first and third sacrificial layers of the second sub-stack.
Yu discloses the second sacrificial layer 110 (Fig. 1, paragraph 0043, wherein “about 10 nm to about 50 nm”) of the second sub-stack has a greater thickness than the first (second 106 from the bottom of Fig. 1, paragraph 0043, wherein “about 4 nm to about 10 nm”) and third sacrificial layers (third 106 from the bottom of Fig. 1, paragraph 0043) of the second sub-stack (stack vertically from second 106 to third 106 from the bottom of Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Frougier to form the second sacrificial layer of the second sub-stack has a greater thickness than the first and third sacrificial layers of the second sub-stack, as taught by Yu, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 8, Frougier further discloses the method of claim 7, wherein the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B) comprises exactly two units (116-2 and 116-3 in Fig. 2B) of a first sacrificial layer of the first sacrificial semiconductor material and a second sacrificial layer 112-2 (Fig. 2B) of the second sacrificial semiconductor material, and the third sacrificial layer 116-4 (Fig. 2B) of the first sacrificial semiconductor material on an upper one of said units (116-2 and 116-3 in Fig. 2B).
Regarding claim 9, Frougier further discloses the method of claim 8, wherein each first (116-2 and 116-3 in Fig. 2B) and second sacrificial layers 112-2 (Fig. 2B) of the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B), and the third sacrificial layer 116-4 (Fig. 2B) have a similar thickness (see paragraph 0036, wherein “the thickness of the sacrificial nanosheet layers 112 and 116 is in a range of about 8 nm to about 15 nm”).
Allowable Subject Matter
1. Claims 10-12 and 15 are rejected under 35 USC § 112 in the above but would be allowable if 35 USC § 112 rejection is resolved and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 10 would be allowable because a closest prior art, Frougier et al. (US 20230086633), discloses a first sub-stack (stack vertically from 116-1 to 114-2 in Fig. 2B) comprising a first sacrificial layer 116-1 (Fig. 2B, paragraph 0030) and on the first sacrificial layer 116-1 (Fig. 2B) a channel layer 114-2 (Fig. 2B, paragraph 0030) defining a topmost layer of the first sub-stack (stack vertically from 114-1 to 114-2 in Fig. 2B); a third sub-stack (stack vertically from 114-6 to 116-6 in Fig. 2B) on the second sub-stack (stack vertically from 116-2 to 116-4 in Fig. 2B) and comprising a channel layer 114-6 (Fig. 2B) of the channel material; forming the gate stack (1302, 1304, 1306, and 1308 in Fig. 13B) further comprises: conformally depositing a gate dielectric layer 1300 (Fig. 13B, paragraph 0078, wherein “highly conformal deposition process”) and then a first gate work function metal 1302 (Fig. 13B, paragraph 0079) in the gate trench (opening between 130 in Fig. 13B), subsequently; and subsequently conformally depositing a second gate work function metal 1304 (Fig. 13B, paragraph 0080) in the gate trench (opening between 130 in Fig. 13B) but fails to disclose forming a block mask with a thickness such that the first gate work function metal surrounding the channel layer of the first sub-stack is covered and the first gate work function metal surrounding the channel layer of the third sub-stack is exposed, removing the first gate work function metal from the channel layer of the third sub-stack while using the block mask as an etch mask. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method for forming a semiconductor device, the method comprising: forming a block mask with a thickness such that the first gate work function metal surrounding the channel layer of the first sub-stack is covered and the first gate work function metal surrounding the channel layer of the third sub-stack is exposed, removing the first gate work function metal from the channel layer of the third sub-stack while using the block mask as an etch mask in combination with other elements of the base claims 9, 8, 7, 6, 5, 4, 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claims 11 and 12 depend on claim 10.
In addition, claim 15 would be allowable because a closest prior art, Frougier et al. (US 20230086633), discloses the device layer stack (stack vertically from 112-1 to 116-6 in Fig. 3B) is a first device layer stack (stack vertically from 112-1 to 114-4 in Fig. 3B), and the channel layer 114-2 (Fig. 3B) of the first sub-stack (stack vertically from 116-1 to 114-2 in Fig. 3B), and wherein the method further comprises: forming a second device layer stack (stack vertically from 114-5 to 116-6 in Fig. 3B) on the substrate 102 (Fig. 3B), the second device layer stack (stack vertically from 114-5 to 116-6 in Fig. 3B) having a same composition as the first device layer (stack vertically from 112-1 to 114-4 in Fig. 3B); and forming recesses (opening vertically between 114 in Fig. 6B), forming inner spacers (portions of 700 contacting sidewalls of 116 in Fig. 7B), forming source and drain regions (802 and 804 in Fig. 8B, paragraph 0057), forming a gate trench (opening between 130 in Fig. 11B), removing (see Fig. 11B) the first sacrificial layers (116-1 and 116-2 in Fig. 10B) of the first (stack vertically from 116-1 to 114-2 in Fig. 10B) and second sub-stacks (stack vertically from 116-2 to 116-4 in Fig. 10B), and forming a gate stack (1302, 1304, 1306, and 1308 in Fig. 13B) to each of the first device layer stack (stack vertically from 112-1 to 114-4 in Fig. 3B) and the second device layer stack (stack vertically from 114-5 to 116-6 in Fig. 3B) but fails to disclose the channel layer of the first sub-stack forms a top-most channel layer of the first device layer stack; and the first and second device layer stacks being separated by a vertically oriented insulating wall, wherein the layers of the first and second sub-stacks of the first device layer stack and the layers of the first and second sub-stacks of the second device layer stack abut opposite side surfaces of the insulating wall, wherein the method comprises forming the sacrificial gate structure to extend across the first and second device layer stacks and the insulating wall, and subsequently applying each one of said acts of etching through the device layer stack, replacing the second sacrificial layer of the second sub-stack. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method for forming a semiconductor device, the method comprising: the channel layer of the first sub-stack forms a top-most channel layer of the first device layer stack; and the first and second device layer stacks being separated by a vertically oriented insulating wall, wherein the layers of the first and second sub-stacks of the first device layer stack and the layers of the first and second sub-stacks of the second device layer stack abut opposite side surfaces of the insulating wall, wherein the method comprises forming the sacrificial gate structure to extend across the first and second device layer stacks and the insulating wall, and subsequently applying each one of said acts of etching through the device layer stack, replacing the second sacrificial layer of the second sub-stack in combination with other elements of the base claim 1.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813