DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A subspecies 1 in the reply filed on 11/26/2025 is acknowledged.
Claims 8-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/26/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0378219 A1 (Yokoyama).
Re claim 1, Yokoyama teaches an image sensor (imaging device 1A) comprising:
a first lower chip (second substrate 200); and
an upper chip (first substrate 100) on and bonded to the first lower chip, wherein the first lower chip and the upper chip collectively comprise a plurality of pixels (first substrate 100 comprises the pixel array unit wherein each pixel is controlled by the analog circuitry in second substrate 200 Fig. 3J), wherein a respective pixel of the plurality of pixels comprises:
a photoelectric conversion element (photodiodes PD 12), a floating diffusion region (floating diffusion region FD [0053]), a ground region (anode of PD coupled to ground line [0087] which is the ground reference connected to the bulk of substrate 100 outside of the highly doped regions), and a transfer gate (transfer transistor TR [0053]) in the upper chip; and
a plurality of lower transistors (full depletion mode transistors including fins 211 and gate 711 in substrate 200) in the first lower chip, and wherein a first lower transistor among the plurality of lower transistors comprises a plurality of first channel layers stacked vertically, and a first gate on the plurality of first channel layers (the transistors in the second substrate 200 can be GAAFETs as depicted in Fig. 5 which have multiple vertically stacked channels [0082] Figs. 3A-3J, 5).
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Re claim 11, Yokoyama teaches wherein the first lower transistor comprises a reset transistor, a selection transistor, or a driving transistor of the respective pixel (the transistors in second substrate 200 can be seen in Fig. 17 and can be RST, REF transistors [0054]), and the image sensor further comprising: a second lower chip (third substrate 300) below the first lower chip, wherein the second lower chip comprises a circuit configured to control a pixel array comprising the plurality of pixels (Fig. 2).
Re claim 12, Yokoyama teaches wherein the upper chip is free of the reset transistor, the selection transistor, and/or the driving transistor of the respective pixel (the transistors in second substrate 200 can be seen in Fig. 17 and can be RST, REF transistors [0054]), wherein the circuit of the second lower chip comprises transistors having at least one of a first three-dimensional (3D) transistor structure or a second three-dimensional (3D) transistor structure, wherein the first 3D transistor structure comprises a plurality of lower channel layers vertically stacked, and a first lower gate on the plurality of lower channel layers (the transistors in the second substrate 200 can be GAAFETs as depicted in Fig. 5 which have multiple vertically stacked channels [0082] Figs. 3A-3J, 5), and wherein the second 3D transistor structure has a lower channel structure comprising first lower semiconductor layers and second lower semiconductor layers that are alternately stacked, and a second lower gate on side surfaces and an upper surface of the lower channel structure.
Re claim 13, Yokoyama teaches an image sensor (imaging device 1A) comprising:
a first lower chip (second substrate 200);
an upper chip (first substrate 100) on and bonded to the first lower chip; and
a second lower chip (third substrate 300) bonded to the first lower chip, below the first lower chip, wherein the first lower chip and the upper chip collectively comprise a pixel array having a plurality of pixels, wherein the second lower chip comprises a control circuit configured to control the pixel array (first substrate 100 comprises the pixel array unit wherein each pixel is controlled by the analog circuitry in second substrate 200 and the third substrate 300 contains logic and memory for controlling the pixel array Fig. 3J),
wherein a respective pixel of the plurality of pixels comprises a photoelectric conversion element (photodiodes PD 12), (floating diffusion region FD [0053]), a ground region (anode of PD coupled to ground line [0087] which is the ground reference connected to the bulk of substrate 100 outside of the highly doped regions), a transfer gate (transfer transistor TR [0053]) a reset transistor (reset transistor RST [0087]), a selection transistor (selection transistor SEL [0087]), and a driving transistor (circuitry in 200 drives the pixels row by row [0054]), wherein the upper chip comprises the photoelectric conversion element, the floating diffusion region, the ground region, and the transfer gate, wherein the first lower chip comprises at least one transistor among the reset transistor, the selection transistor, or the driving transistor (the transistors in second substrate 200 can be seen in Fig. 17 and can be RST, REF transistors [0054]), and
wherein the at least one transistor of the first lower chip has a first three-dimensional transistor structure comprising a plurality of first channel layers stacked vertically, and a first gate on the plurality of first channel layers (the transistors in the second substrate 200 can be GAAFETs as depicted in Fig. 5 which have multiple vertically stacked channels [0082] Figs. 3A-3J, 5).
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Re claim 14, Yokoyama teaches wherein the at least one transistor is the driving transistor ((the transistors in the second substrate 200 can be GAAFETs as depicted in Fig. 5 which have multiple vertically stacked channels [0082] Figs. 3A-3J, 5, 17).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0378219 A1 (Yokoyama) further in view of US 2023/0411429 A1 (Nakazawa).
Re claim 17, Yokoyama teaches an image sensor (imaging device 1A) comprising:
a first lower chip (second substrate 200);
an upper chip (first substrate 100) on and bonded to the first lower chip; and
a second lower chip (third substrate 300) bonded to the first lower chip, below the first lower chip,
wherein the first lower chip and the upper chip collectively comprise a pixel array having a plurality of pixels, wherein the second lower chip comprises a control circuit configured to control the pixel array (first substrate 100 comprises the pixel array unit wherein each pixel is controlled by the analog circuitry in second substrate 200 and the third substrate 300 contains logic and memory for controlling the pixel array Fig. 3J),
wherein a respective pixel of the plurality of pixels comprises a photoelectric conversion element (photodiodes PD 12), (floating diffusion region FD [0053]), a ground region (anode of PD coupled to ground line [0087] which is the ground reference connected to the bulk of substrate 100 outside of the highly doped regions), a transfer gate (transfer transistor TR [0053]) a reset transistor (reset transistor RST [0087]), a selection transistor (selection transistor SEL [0087]), and a driving transistor (circuitry in 200 drives the pixels row by row [0054]), wherein the upper chip comprises the photoelectric conversion element, the floating diffusion region, the ground region, and the transfer gate, wherein the first lower chip comprises at least one transistor among the reset transistor, the selection transistor, or the driving transistor (the transistors in second substrate 200 can be seen in Fig. 17 and can be RST, REF transistors [0054]), and
wherein the upper chip further comprises:
an upper semiconductor substrate (semiconductor substrate 10) having a first surface and a second surface opposing each other;
color filters (color filters 51) on the second surface of the upper semiconductor substrate;
an upper insulating structure (interlayer insulating layer 42) below the first surface of the upper semiconductor substrate; and
upper bonding pads (pad electrode 41) in the upper insulating structure and having lower surfaces coplanar with a lower surface of the upper insulating structure,
wherein the photoelectric conversion element is in the upper semiconductor substrate (Fig. 3J),
wherein the first lower chip further comprises:
a first lower semiconductor substrate (semiconductor substrate 20);
a first lower insulating structure (insulation material of wiring layer 60) on the first lower semiconductor substrate;
first lower bonding pads (pad electrodes 61) in the first lower insulating structure and having upper surfaces coplanar with an upper surface of the first lower insulating structure; and
a lower protective insulating layer (interlayer insulating layer 73) below the first lower semiconductor substrate,
wherein the second lower chip further comprises:
a second lower semiconductor substrate (semiconductor substrate 30); and
a second lower insulating structure (insulating material of wiring layer 80) on the second lower semiconductor substrate,
wherein the first lower bonding pads and the upper bonding pads are in contact with each other (Fig. 3J), and
wherein the at least one transistor of the first lower chip has a first three-dimensional transistor structure comprising a plurality of first channel layers stacked vertically, and a first gate on the plurality of first channel layers (the transistors in the second substrate 200 can be GAAFETs as depicted in Fig. 5 which have multiple vertically stacked channels [0082] Figs. 3A-3J, 5).
Yokoyama does not illustrate the specific layout of the floating diffusion region and the ground region and only depicts a single photodiode. However, Yokoyama does teach that the floating diffusion region and ground region are in the upper chip (Fig. 17) and that the imager comprises an array of photodiodes (Fig. 2).
Nakazawa teaches an imager formed by bonded substrates wherein the upper layer having the photodiodes separates each pixel with a pixel isolation structure (pixel separation structure 17) and wherein the floating diffusion region (FD) and ground potential regions (118 [0251]) are under the photodiodes (Fig. 6).
It would have been obvious to one of ordinary skill in the art at the time of filing to form the photodiode layer of Yokoyama having pixel isolation between the photodiodes or the pixel array and wherein the floating diffusion and ground regions are under the photodiode closest to the connectors with the underlying transistors.
The motivation to do so is that pixel isolation provides the predictable result of preventing the generated photocurrent from interacting between pixels and the floating diffusion region and ground region collect the generated photocurrent and the electrical signal is passed on the transistors underneath and thus are under the photodiode and opposite from the light sensitive side of the substrate.
Allowable Subject Matter
Claims 2-7,15-16, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896