DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 11/12/2025, with respect to the rejections of the claims under 35 USC 102 and 112(a) and the objection to the drawings have been fully considered and are persuasive. Therefore, the rejections and objections have been withdrawn. However, upon further consideration, a new ground of rejection has been made below.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “MOL metallization layer is directly adjacent to a contact level that includes a S/D contact and a gate contact” of claim 3 which depends on the limitations in claim 1 which recites “a contact element configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second transistor without any metallization level transitions” and claim 2 which recites “the contact element is disposed entirely within a middle-of-line (MOL) metallization layer of the IC structure”;
the “forming the contact element comprises forming the contact element within the MOL metallization layer that is directly adjacent to a contact level that includes a source or drain contact and a gate contact” of claim 13 which is dependent upon claim 11 which recites “forming a contact element configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second” and claim 12 which recites “the contact element is disposed entirely within a middle-of-line (MOL) layer of the IC structure”;
“the contact element electrically couples to the first S/D through the S/D contact; the contact element electrically couples to the gate through the gate contact; and the contact element resides within a second metallization level that is adjacent to the first metallization level” of claim 10 is dependent upon the limitation “a contact element configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second” of claim 1; and
“forming a gate contact in electrical contact with the gate, where in the gate contact is within the first metallization level; wherein the contact element electrically couples to the S/D through the S/D contact; wherein the contact element electrically couples to the gate contact through the gate contact; and wherein the contact element resides within a second metallization level that is adjacent to the first metallization level one metallization level is adjacent the first metallization level” of claim 20 which is dependent upon the limitation “forming a contact element configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second”
the feature(s) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. [see 112(a) rejection below for more context]
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 10, 13 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Dependent Claim 3 recites the limitation “MOL metallization layer is directly adjacent to a contact level that includes a S/D contact and a gate contact” wherein claim 3 depends on the limitations in claim 1 which recites “a contact element configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second transistor without any metallization level transitions” and claim 2 which recites “the contact element is disposed entirely within a middle-of-line (MOL) metallization layer of the IC structure”.
Similarly Claim 13 recites “forming the contact element comprises forming the contact element within the MOL metallization layer that is directly adjacent to a contact level that includes a source or drain contact and a gate contact” where it is dependent upon claim 11 which recites “forming a contact element configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second without any metallization level transitions” and claim 12 which recites “the contact element is disposed entirely within a middle-of-line (MOL) layer of the IC structure”.
For both claims 3 and 13 no embodiment discloses and/or illustrates both the features of “a contact element…configured to directly connect the first S/D of the first transistor to the gate of the second transistor without any metallization level transitions” and “the MOL metallization layer is directly adjacent to a contact level that includes a S/D contact and a gate contact” wherein “the contact element is disposed entirely within a middle-of-line (MOL) metallization layer of the IC structure”. The closest embodiments presented in the application as identified by the examiner is the embodiment of fig. 4A-4B which illustrates “a contact element (412 fig. 4A-B)…configured to directly connect the first S/D of the first transistor to the gate of the second transistor” however no contact level appears to be adjacent to the MOL layer comprising “CA level” fig. 4B and the embodiment of fig. 5A-5B which illustrates “MOL metallization layer (C1 level comprising 412 fig. 5B) is directly adjacent to a contact level (C0 level fig. 5B) that includes a S/D contact (330/416 fig. 5B) and a gate contact (506/410 fig. 5B)” however the contact structure 412 appears to have an indirectly connection to the S/D and gate structures as it separated from the S/D and gates by the contact level (C0) and/or the Source/drain and/or gate contacts; and/or there is a metallization level transition from C0 level to C1 level. Note as presented there are two embodiments and/or species “MOL metallization layer is directly adjacent to a contact level that includes a S/D contact and a gate contact” of fig. 5A-5B or “a contact element…configured to directly connect the first S/D of the first transistor to the gate of the second transistor” and/or “without any metallization level transitions” of fig. 4A-4B, no election is required at this time. However, if the applicant believes these two species to be distinct and not obvious alternatives the examine recommends and election species.
Claim 10 similarly to the above recites “the contact element electrically couples to the first S/D through the S/D contact; the contact element electrically couples to the gate through the gate contact; and the contact element resides within a second metallization level that is adjacent to the first metallization level” wherein claim 10 is dependent upon the limitation “a contact element configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second”
And Claim 20 similarly to the above recites the limitations “forming a gate contact in electrical contact with the gate, where in the gate contact is within the first metallization level; wherein the contact element electrically couples to the S/D through the S/D contact; wherein the contact element electrically couples to the gate contact through the gate contact; and wherein the contact element resides within a second metallization level that is adjacent to the first metallization level one metallization level is adjacent the first metallization level” wherein claim 20 is dependent upon the limitation “forming a contact element configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second”.
Regarding Claims 10 and 20 the recitation of these limitations is similar to what is described for claims 3 and 13 above, no figure shows all of the claimed features nor is such an embodiment explicitly disclosed. Fig. 4A-4B shows an embodiment regrading only the direct connection without a metallization level transition and fig. 5A-5B shows an embodiment regrading only the adjacent first and second metallization levels (C0 and C1).
No prior art has been applied to claims 3, 10, 13, and 20 below.
Claim(s) 1-2, 4-9, 11-12, 14-15 and 18-19 are rejected under 35 U.S.C. 103 as being obvious in view of US 9224835 B2 Masuoka et al hereafter “Masuoka”
Claim 1 Masuoka teaches a multi-layer integrated circuit (IC) structure comprising:
a first transistor (comprising P1, P2, P3 Fig. 2M) having a first source or drain (S/D) (comprising 13aa and/or 12bb, 12aa fig. 2M and 2L);
a second transistor (comprising P4, P5, P6 Fig. 2M) having a second S/D (comprising 13bb, and/or 12dd and/or 12cc not labeled but illustrated in fig. 2M, labeled in fig. 2L) and a gate (comprising 14d and/or 14c fig. 2M); and
a contact element (comprising the elements of 22 and 21) configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second transistor [sufficiently illustrated fig. 2M the contact element horizontally connects the transistors], with a metallization level transition (21 to 22 fig. 2M)
Masuoka does not teach the contact element configured to directly connect the first S/D of the first transistor to the gate of the second transistor without any metallization level transitions.
It would have been obvious to one of ordinary skill in the art to eliminate the metallization level transition Masuoka teaches such that “the contact element configured to directly connect the first S/D of the first transistor to the gate of the second transistor without any metallization level transitions” as omission of an element and its function is obvious if the function of the element is not desired [See MPEP 2144.04 II]. In this case the function is separating the horizontal features of the contact element into a higher metallization layer than the level of the vertical transistor.
Claim 2 Modified Masuoka teaches as shown above the IC structure of claim 1, wherein the contact element is disposed entirely within a middle of line (MOL) metallization layer of the IC structure [Necessarily met in view of the modification as made above to achieve no metallization layer transition and maintain the direct connection, as the contact element would be in the vertical middle of the line and/or vertical middle of the cross section across the active region].
Claim 4 Modified Masuoka teaches as shown above the IC structure of claim 1, wherein:
the first transistor comprises a first n-type field effect transistor (NFET) (comprising P1 and/or P3 fig. 2M), a first p-type FET (PFET) (comprising P3 fig. 2M), and a first shared gate (comprising 14a and/or 14b fig. 2M); and
the first S/D region comprises:
a S/D region of the first NFET (comprising 12bb and/or 12aa fig. 2M); and
a S/D region of the first PFET (comprising 13aa fig. 2M).
Claim 5 Modified Masuoka teaches as shown above the IC structure of claim 4, wherein:
the second transistor comprises a second NFET (comprising P4 and/or P6 fig. 2M), a second PFET (comprising P5 fig. 2M), and a second shared gate (comprising 14c and/or 14d fig. 2M); and
the gate comprises the second shared gate [sufficiently disclosed and illustrated fig. 2M].
Claim 6 Modified Masuoka teaches as shown above the IC structure of claim 5, wherein the contact element connects (connecting with elements 21C, 21h, 22b fig. 2M of 21 and 22):
the S/D region of the first NFET (comprising 12bb fig. 2M);
the S/D region of the first PFET (comprising 13aa fig. 2M); and
the second shared gate (14d). [sufficiently illustrated fig. 2M]
Claim 7 Modified Masuoka the IC structure of claim 1 further comprising an inverter comprising the first transistor and the second transistor [sufficiently disclosed Column 9 lines 35-40 “This SRAM cell includes two inverter circuits. One of the inverter circuits is constituted by a P-channel SGT Pc1 serving as a load transistor, and an N-channel SGT Nc1 serving as a drive transistor. The other inverter circuit is constituted by a P-channel SGT Pc2 serving as a load transistor, and an N-channel SGT Nc2 serving as a drive transistor”].
Claim 8 Modified Masuoka teaches as shown above the IC structure of claim 7, wherein:
the first transistor comprises a first vertical transport field effect transistor (VTFET) [sufficiently illustrated fig. 2M, met under 2112.01 and/or broadest reasonable interpretation];
the second transistor comprises a second VTFET [sufficiently illustrated fig. 2M, met under 2112.01 and/or broadest reasonable interpretation]; and
the first VTFET is separated from the second VTFET by one transistor gate pitch [sufficiently illustrated fig. 2M, met under 2112.01 and/or broadest reasonable interpretation].
Claim 9 Modified Masuoka teaches as shown above the IC structure of claim 8 further comprising:
a S/D contact (21c fig. 2M) in electrical contact with the first S/D, wherein the S/D contact is within a first metallization level (22b fig. 2m); and
a gate contact (21h fig. 2M) in electrical contact with the gate, wherein the gate contact is within the first metallization level [illustrated fig. 2M].
Claim 11 Masuoka teaches a method of forming a multi-layer integrated circuit (IC) structure, the method comprising:
forming a first transistor (comprising P1, P2, P3 fig. 2M) having a first source or drain (S/D) (13aa and/or 12bb and/or 12aa fig. 2M);
forming a second transistor (comprising P4, P5, P6 fig. 2M) having a second S/D (comprising 13bb, and/or 12dd and/or 12cc not labeled but illustrated in fig. 2M, labeled in fig. 2L)and a gate (14d and/or 14c fig. 2M); and
forming a contact element (comprising elements 21 and 22) configured to operate as a single horizontally extending conductive bridge having substantially horizontal features configured to directly connect the first S/D of the first transistor to the gate of the second transistor [illustrated fig. 2M met under broadest reasonable interpretation as the transistors are horizontally connected through the contact element and/or elements 22 are substantially horizontal] without any metallization level transitions.
Claim 12 Modified Masuoka teaches as shown above the method of claim 11, wherein the contact element is within disposed entirely within a middle-of-line (MOL) layer of the IC structure [Necessarily met in view of the modification as made above Necessarily met in view of the modification to achieve no metallization layer transition and maintain the direct connection, the contact element would be in the vertical middle of the line and/or vertical middle of the cross section across the active region].
Claim 14 Modified Masuoka teaches as shown above the method of claim 11, wherein:
the first transistor comprises a first n-type field effect transistor (NFET) (P1 and/or P3 fig. 2M), a first p-type FET (PFET) (P2 fig. 2M), and a first shared gate (comprising 14a and/or 14b fig. 2M);
the first S/D region comprises:
a S/D region of the first NFET (12bb fig. 2M); and
a S/D region of the first PFET (13aa fig. 2M);
the second transistor comprises a second NFET (P4 and/or P6 fig. 2M), a second PFET (P5 fig. 2M), and a second shared gate (14d and/or 14c fig. 2M); and
the gate comprises the second shared gate [illustrated fig. 2M].
Claim 15 Modified Masuoka teaches as shown above the method of claim 14, wherein the contact element connects:
the S/D region of the first NFET;
the S/D region of the first PFET; and
the second shared gate.
[sufficiently illustrated fig. 2M]
Claim 18 Modified Masuoka teaches as shown above the method of claim 11, wherein forming the first transistor and forming the second transistor forms an inverter. [sufficiently disclosed Column 9 lines 35-40 “This SRAM cell includes two inverter circuits. One of the inverter circuits is constituted by a P-channel SGT Pc1 serving as a load transistor, and an N-channel SGT Nc1 serving as a drive transistor. The other inverter circuit is constituted by a P-channel SGT Pc2 serving as a load transistor, and an N-channel SGT Nc2 serving as a drive transistor”]
Claim 19 Modified Masuoka teaches as shown above the method of claim 18, wherein:
the first transistor comprises a first vertical transport field effect transistor (VTFET) [illustrated fig. 2M, under broadest reasonable interpretation];
the second transistor comprise a second VTFET [illustrated fig. 2M, under broadest reasonable interpretation]; and
the first VTFET is separated from the second VTFET by one transistor gate pitch [illustrated fig. 2M, under broadest reasonable interpretation].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Modified Masuoka as applied to the claims above, and further in view of US 20110130004 A1 Lee et al “Lee”.
Claim 16 Modified Masuoka teaches as shown above the method of claim 11,
Masuoka does not explicitly teach wherein forming the contact element comprises using damascene fabrication operations and subtractive fabrication operations.
Lee teaches a damascene fabrication operation to form contact elements that comprises subtractive fabrication operations [Paragraph 0067-0068, “self-aligned damascene process” wherein removing and recessing are subtractive fabrication under broadest reasonable interpretation].
It would have been obvious to one of ordinary skill in the art to take the contact element of Masuoka and form it using “damascene fabrication operations and subtractive fabrication operations” as Lee teaches to improve the uniformity of the contact structure (Paragraph 0068 Lee) and/or to substitute equivalents known for the same purpose (in this case for the purpose of forming a contact structure) [See MPEP 2144.06]
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Modified Masuoka as applied to the claims above, in further view of US 20130146982 A1 Rashed et al hereafter “Rashed”
Claim 17 Modified Masuoka the method of claim 11, wherein forming the device comprises
forming the substantially horizontal features of the contact element (comprising features 20 fig. 2M)
Modified Masuoka does not teach forming substantially vertical features of the contact structure.
Rashed teaches a forming a contact element (36 fig. 9) comprises;
forming a substantially horizontal features (36 extending left to right fig. 9) of the contact element;
forming substantially vertical features of the contact element (36 extending top to bottom fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the contact structure as Masuoka teaches such that it includes a “substantially vertical feature” as Rashed teaches to connect diagonally adjacent features and/or changes in shape are prima facie type obviousness [See MPEP 2144.04 IV B.].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893