CTNF 18/065,747 CTNF 83282 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-04 AIA A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/03/2026 has been entered. Election/Restrictions 08-04 AIA Newly submitted claim s 25-32 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: Applicant selected specie A: FIG. 4A in the response to the restriction dated on 05/18/2025 . Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim s 25-32 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03. To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-4 and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN107004633 (hereinafter `633) in view of another Mignot (Patent No.: US 11056426) . PNG media_image1.png 574 1028 media_image1.png Greyscale Re claim 1, `633 teaches a semiconductor device comprising: a second level of interconnect wiring ([SL], FIG. 2D [as shown above]) comprising a plurality of metal tracks (121-126) comprising a first metal track (122/[FMT]) and a second metal track (121/[SMT]) ; a third level of interconnect wiring [TS]; PNG media_image2.png 200 400 media_image2.png Greyscale a discontinuous dielectric cap over the second level of interconnect wiring comprising a first portion [FPosDC] located above the first metal track (122) and in direct contact with a top face of the first metal track (122/[FMT]) and a second portion [SPofDC] located above the second metal track and in direct contact with a top face of the first metal track (121/[SMT]) , wherein the first portion comprises a width equal to a width of the first metal track and wherein the second portion [SPofDC] comprises a width equal to a width of the second metal track (121) ; and a skip via connecting (181) the first level of interconnect wiring to the second level of interconnect wiring (121-126). `633 fails to teach a first level of interconnect wiring. Mignot teaches a first level of interconnect wiring ([FLI], FIG. 12 [as shown below]). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of controlling the interconnect via profile and chamfer height as taught by Mignot, BACKGROUND. Moreover, after the combining of `633 and Mignot would teach a skip via connecting the first level of interconnect wiring to the third level of interconnect wiring. Re claim 2, in the combination. Mignot, FIG. 12 [as shown above] teaches the semiconductor device of claim 1, further comprising a first via [FV] connecting the second level of interconnect wiring [SLI] to the third level of interconnect wiring [TLI]; and a second via [SV] connecting the first level of interconnect wiring [FLI] to the second level of interconnect wiring [SLI]. Re claim 3, in the combination, `633 teaches the semiconductor device of claim 1, wherein the plurality of metal tracks further comprises a third metal track (126). Re claim 4, in the combination, `633 teaches the semiconductor device of claim 1, wherein the skip via (124) is aligned between the first metal track (122) and the second metal track (121). Re claim 21, in the combination, `633 teaches the semiconductor device of claim 1, wherein the discontinuous dielectric cap comprises a plurality of gaps (horizontal gap) between the plurality of metal tracks (121-126). Re claim 22, in the combination, `633 teaches the semiconductor device of claim 1, further comprising an intermediate level dielectric [ID] in contact with side walls of the skip via (124) and a sidewall of the first portion and a sidewall of the second portion. Re claim 23, in the combination, `633 teaches the semiconductor device of claim 22, wherein the intermediate dielectric comprises a first material (105) and the discontinuous dielectric cap comprises a second material (103), and wherein the intermediate level dielectric ([ID], FIG. 2H [as shown above], note that [ID] is now including the dielectric layer 180 ) is in contact with three sides of the first portion. Re claim 24, in the combination, `633 teaches the semiconductor device of claim 1, wherein the skip via (124) is aligned within a gap of the plurality of gaps between the plurality of metal tracks (121-126) . 07-21-aia AIA Claim (s) 1-4 and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mignot in view of another `633 . PNG media_image3.png 671 927 media_image3.png Greyscale Re claim 1, Mignot, FIG. 12 [as shown above] teaches a semiconductor device comprising: a first level of interconnect wiring [FLI]; a second level of interconnect wiring [SLI] comprising a plurality of metal tracks comprising a first metal track and a second metal track; a third level of interconnect wiring [TLI]; a discontinuous dielectric cap [DDC] over the second level of interconnect wiring; and a skip via [SV] connecting the first level of interconnect wiring [FLI] to the third level of interconnect wiring [TLI]. Mignot fails to teach a discontinuous dielectric cap over the second level of interconnect wiring comprising a first portion located above the first metal track and in direct contact with a top face of the first metal track and a second portion located above the second metal track and in direct contact with a top face of the first metal track, wherein the first portion comprises a width equal to a width of the first metal track and wherein the second portion comprises a width equal to a width of the second metal track. Mignot teaches a discontinuous dielectric cap over the second level of interconnect wiring comprising a first portion [FPosDC] located above the first metal track (122) and in direct contact with a top face of the first metal track (122/[FMT]) and a second portion [SPofDC] located above the second metal track and in direct contact with a top face of the first metal track (121/[SMT]) , wherein the first portion [FPofDC] comprises a width equal to a width of the first metal track (122) and wherein the second portion [SPofDC] comprises a width equal to a width of the second metal track (121) . It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of connecting one interconnect line of one interconnect layer to a desired underlying layer or line, without error connection to different interconnect layers or lines as taught by `633, BACKGROUND. Re claim 2, in the combination, Mignot, FIG. 12 [as shown above] teaches the semiconductor device of claim 1, further comprising a first via [FV] connecting the second level of interconnect wiring [SLI] to the third level of interconnect wiring [TLI]; and a second via [SV] connecting the first level of interconnect wiring [FLI] to the second level of interconnect wiring [SLI]. Re claim 3, in the combination, Mignot, FIG. 12 [as shown above] teaches the semiconductor device of claim 1, wherein plurality of metal tracks further comprises a third metal track [TMT] . Re claim 4, in the combination, Mignot, FIG. 12 [as shown above] teaches the semiconductor device of claim 3, wherein the skip via [SV] is aligned between the first metal track [FMT] and the second metal track [SMT]. Re claim 21, in the combination, `633 teaches the semiconductor device of claim 1, wherein the discontinuous dielectric cap comprises a plurality of gaps (horizontal gap) between the plurality of metal tracks (121-126). Re claim 22, in the combination, `633 teaches the semiconductor device of claim 1, further comprising an intermediate level dielectric [ID] in contact with side walls of the skip via (124) and a sidewall of the first portion and a sidewall of the second portion. Re claim 23, in the combination, `633 teaches the semiconductor device of claim 22, wherein the intermediate dielectric comprises a first material (105) and the discontinuous dielectric cap comprises a second material (103), and wherein the intermediate level dielectric ([ID], FIG. 2H [as shown above], note that [ID] is now including the dielectric layer 180) is in contact with three sides of the first portion. Re claim 24, in the combination, `633 teaches the semiconductor device of claim 1, wherein the skip via (124) is aligned within a gap of the plurality of gaps between the plurality of metal tracks (121-126). Response to Arguments Applicant's arguments with respect to claims 1-4 on the remarks filed on 03/03/2026 have been considered but are not persuasive because `633 still reads on: PNG media_image2.png 200 400 media_image2.png Greyscale a discontinuous dielectric cap over the second level of interconnect wiring comprising a first portion [FPosDC] located above the first metal track (122) and in direct contact with a top face of the first metal track (122/[FMT]) and a second portion [SPofDC] located above the second metal track and in direct contact with a top face of the first metal track (121/[SMT]) , wherein the first portion comprises a width equal to a width of the first metal track and wherein the second portion [SPofDC] comprises a width equal to a width of the second metal track (121) . Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONY TRAN/Primary Examiner, Art Unit 2893 Application/Control Number: 18/065,747 Page 2 Art Unit: 2893 Application/Control Number: 18/065,747 Page 3 Art Unit: 2893 Application/Control Number: 18/065,747 Page 4 Art Unit: 2893 Application/Control Number: 18/065,747 Page 5 Art Unit: 2893 Application/Control Number: 18/065,747 Page 6 Art Unit: 2893 Application/Control Number: 18/065,747 Page 7 Art Unit: 2893 Application/Control Number: 18/065,747 Page 8 Art Unit: 2893 Application/Control Number: 18/065,747 Page 9 Art Unit: 2893 Application/Control Number: 18/065,747 Page 10 Art Unit: 2893
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