DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/11/2026 has been entered.
Response to Amendment
Applicant's amendments on 1/13/2026 have been reviewed and entered. Claims 1, 12, and 14-17 have been amended. Claims 1-20 remain for examination.
Applicant’s amendment to claim 12 has overcame the claim objection made on claim 12 in the Final Office action mailed on 11/13/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/18/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-11, 13, 15-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang-285 (US 2023/0307285 A1) in views of Mulfinger (US 2021/0398862 A1) and Hong (US 2022/0302172 A1).
Regarding claim 1, Huang-285 teaches a semiconductor structure (semiconductor device 100, Fig. 1A-H, [0019]) comprising:
a complementary field-effect transistor device (comprising GAA FETs 102A1 and 102A2, Fig. 1D, [0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”) with a first transistor (GAA FETs 102A1, Fig. 1D) under a second transistor (GAA FETs 102A2, Fig. 1D); and
a gate cut (isolation structure 106 filled with dielectric fill portions 106A, Figs. 1A and 1D, [0041]) directly adjacent (Figs. 1A and 1D) and abutting a gate (comprising gate structures 118A1 and 118A2, Fig. 1D, [0024]) of the complementary field-effect transistor device (comprising GAA FETs 102A1 and 102A2, Fig. 1D), wherein the gate cut (isolation structure 106, Fig. 1D) lacks a conductive fill material disposed in the gate cut (isolation structure 106, Fig. 1D, [0041]: filled with dielectric fill portions 106A).
Huang-285, however, does not teach that the gate cut is filled with a first dielectric material under a second dielectric material.
Mulfinger, on the other hand, teaches the usage of stress-inducing isolation dielectric materials (first and second stress-inducing isolation dielectrics 144 and 150, Fig. 5, [0033]) around active regions (first active region 130 (labeled as SOI 118) and second active region 132, Fig. 5, [0033]) in a multi field-effect transistor (FET) device (the device in Fig. 5 has two n-type FETs and two p-type FETs, Fig 5, [0033]) to improve the performance of each transistor in the device by inducing a proper stress to each active region (Abstract). Based on the fact that the tensile stress enhances electron mobility (or drive currents) in an n-channel FET (NFET) while compressive stress enhances hole mobility in a p-channel FET (PFET) ([0003]), Mulfinger discloses that performance improvements in NFET devices can be accomplished by using a tensile-stress-inducing dielectric material as an isolation material (such as in a trench isolation structure) next to the active region (channel), and similarly, performance improvements in PFET devices can be accomplished by using another type of dielectric material, which can induce compressive stress, as an isolation material next to the active region ([0004] and [0006]). Furthermore, a person of ordinary skill in the art would also know that such a tensile and compressive stress inducing approach has been utilized in CFETs, as evidenced by Hong (US 20220302172 A1). Hong teaches a CFET device (Figs. 3A-B), where upper nanosheet transistors UNT are PFETs (or NFETs), lower nanosheet transistors LNT are NFETs (or PFETs) ([0040], and diffusion break structures (DBS) 300 between adjacent CFETs is filled a first dielectric material (DBS 300L, Fig. 3B, [0061]) under a second dielectric material (DBS 300U, Fig. 3B, [0061]), so that “a drive current performance of the multi-stack semiconductor device 10 may be enhanced by effectively controlling stress applied to the lower nanosheet transistors LNT, that is, PFETs, at a lower stack and the upper nanosheet transistors UNT, that is, NFETs, at an upper stack using the lower DDB structure 100L and the upper DDB structure 100U” ([0043]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated by the teachings of Mulfinger and Hong to replace the dielectric filling material (dielectric fill portions 106A, Fig. 3B) in the gate cut (isolation structure 106, Fig. 3B) in the semiconductor structure of Huang-285, by filling the portion of the gate cut (isolation structure 106, Fig. 3B) with one type of dielectric material (first dielectric material) until the border between the first and second transistors to be able to induce a proper type of stress on the first transistor, and then filling the rest of the gate cut (isolation structure 106, Fig. 3B) with another type of dielectric material (second dielectric material) to be able to apply a proper type of stress on the second transistor. This modification would provide the benefit of improving the performance of both transistors as taught by Mulfinger ([0006]-[0007]) and Hong ([0043]).
Thus, the combination of Huang-285, Mulfinger, and Hong meets all the limitations of claim 1.
Regarding claim 2, while Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 1,
Huang-285 is silent about applying stress on the one or more channels of the first transistor.
Mulfinger, however, teaches that the stress-inducing dielectric material for a PFET device would be selected from materials that can induce a compressive stress on the active region, whereas the stress-inducing dielectric material for an NFET device would be selected from materials that can induce a tensile stress on the active region ([0003]).
Because the combination of Huang-285, Mulfinger and Hong according to claim 1 teaches that the stress inducing dielectric material (first dielectric material) is mainly next to the channels of the first transistor, a person of ordinary of ordinary skill in the art before the effective filing date of the claimed invention would be motivated by the teachings of Mulfinger to use a first dielectric material that applies a stress to one or more channels of the first transistor, the stress selected from the group consisting of: a compressive stress and a tensile stress, which would have the benefit of improving the performance of the first transistor by selecting the proper stress inducing dielectric material according to the type of the transistor (Mulfinger, Abstract).
Regarding claim 3, Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 2, wherein
Huang-285 further teaches that the first transistor (GAA FETs 102A1, Fig. 1D) is an n-type field-effect transistor (NFET) ([0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”, and therefore the first and second transistors can be an NFET and a PFET, respectively).
Huang-285, however, does not teach that the first dielectric material applies the tensile stress to the one or more channels of the first transistor.
Mulfinger, on the other hand, teaches that the stress inducing dielectric material for a PFET device would be selected among materials that induces a compressive stress on the active region, whereas the one for an NFET device would be selected among material that induces a tensile stress ([0003]).
Therefore, because the first transistor is an n-type field-effect transistor (NFET) in the semiconductor structure of Huang-285 in views of Mulfinger and Hong, a person of ordinary of ordinary skill in the art before the effective filing date of the claimed invention would be motivated by the teachings of Mulfinger to use a first dielectric material that applies the tensile stress to the one or more channels of the first transistor, which would have the benefit of improving the performance of the first transistor by selecting the proper stress inducing dielectric material according to the type of the transistor (Mulfinger, Abstract).
Regarding claim 4, Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 2, wherein
Huang-285 teaches that the first transistor (GAA FETs 102A1, Fig. 1D) is a p- type field-effect transistor (0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”, and therefore the first and second transistors can be a PFET and an NFET, respectively),
Huang-285, however, is silent on that a first dielectric material and stress applied to the one or more channels of the first transistor.
Mulfinger, however, teaches that the stress-inducing dielectric material would be selected from materials that can induce a compressive stress, if the target device is a PFET device ([0003]).
Therefore, a person of ordinary of ordinary skill in the art before the effective filing date of the claimed invention would be motivated by the teachings of Mulfinger to use a first dielectric material in the semiconductor device of Huang-285, Mulfinger, and Hong that applies the compressive stress to the one or more channels of the first transistor (a p- type field-effect transistor), which would have the benefit of improving the performance of the first transistor by selecting the proper stress inducing dielectric material according to the type of the transistor (Mulfinger, Abstract).
Regarding claim 5, Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 1, wherein
Huang-285 further teaches that the first transistor (GAA FETs 102A1, Fig. 1D) is an NFET, the second transistor (GAA FETs 102A2, Fig. 1D) is a PFET ([0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”, and therefore the first and second transistors can be an NFET and a PFET, respectively).
Huang-285, however, does not teach that the second dielectric material applies a compressive stress to one or more channels of the second transistor.
Mulfinger, on the other hand, teaches that the stress inducing dielectric material for a PFET device would be selected among materials that can induce a compressive stress on the active region, whereas the one for an NFET device would be selected among materials that can induce a tensile stress on the active region ([0003]).
Therefore, because the first transistor is an n-type field-effect transistor (NFET) and the second transistor is a p-type field effect transistor (PFET) in the semiconductor structure of Huang-285 in views of Mulfvinger and Hong, a person of ordinary of ordinary skill in the art before the effective filing date of the claimed invention would be motivated by the teachings of Mulfinger to use a second dielectric material that applies the compressive stress to the one or more channels of the second transistor (a p- type field-effect transistor) in the semiconductor device of Huang-285 in views of Mulfinger and Hong, which would provide the benefit of improving the performance of the second transistor by selecting the proper stress inducing dielectric material according to the type of the transistor (Mulfinger, Abstract).
Regarding claim 6, Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 1, wherein
Huang-285 further teaches that the first transistor (GAA FETs 102A1, Fig. 1D) is an PFET, the second transistor (GAA FETs 102A2, Fig. 1D) is an NFET 3B) is an NFET ([0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”, and therefore the first and second transistors can be a PFET and an NFET, respectively),
Huang-285, however, is silent on a second dielectric material and stress applied to one or more channels of the second transistor.
Mulfinger, however, teaches that the stress-inducing dielectric material for an NFET device would be selected among materials that can induce a tensile stress on the active region ([0003]).
Therefore, a person of ordinary of ordinary skill in the art before the effective filing date of the claimed invention would be motivated by the teachings of Mulfinger to use a second dielectric material that applies the tensile stress to one or more channels of the second transistor (an NFET), in the semiconductor device of Huang-285 in views of Mulfinger and Hong, which would have the benefit of improving the performance of the second transistor by selecting the proper stress inducing dielectric material according to the type of the transistor (Mulfinger, Abstract).
Regarding claim 7, Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 1, wherein
Huang-285 further teaches that the gate cut (isolation structure 106, Figs. 1A and 1D) extends from a top surface of the gate (top surface of gate structure 118A2, Figs. 1A and 1D) of the complementary field-effect transistor device (comprising GAA FETs 102A1 and 102A2, Figs. 1A and 1D) into a portion of a semiconductor substrate (substrate 104, Figs. 1A and 1D, [0064]) under the complementary field-effect transistor device (comprising GAA FETs 102A1 and 102A2, Figs. 1A and 1D).
Regarding claim 8, Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 1, wherein
Huang-285 further teaches that the gate cut (isolation structure 106, Figs. 1A and 1D) is abutting a sidewall of the gate (gate structures 118A1 and 118A2, Fig. 1D: isolation structure 106 is in direct contact with the right sidewalls of conductive layers 136A1 and 136A2) of the complementary field-effect transistor device (comprising GAA FETs 102A1 and 102A2, Fig. 1D).
Huang-285, however, is silent about the first dielectric material being under the second dielectric material and adjacent to the first transistor.
The combination of Huang-285, Mulfinger and Hong, however, teaches that the first dielectric material under the second dielectric material is adjacent to the first transistor (see claim 1 rejection above).
Thus, the combination of Huang-285, Mulfinger and Hong meets all the limitations of claim 8.
Regarding claim 9, Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 2, wherein
Huang-285 further teaches that the gate (gate structures 118A1 and 118A2, Fig. 1D) of the complementary field--effect transistor device (comprising GAA FETs 102A1 and 102A2, Fig. 1D) directly contacts each channel (nanostructured layers 116A1 and 116A2, Fig. 1D, [0024]: interfacial oxide (IL) layers 132 ([0033]) of the gate structures 118A1 and 118A2 contact each channel) of the one or more channels (nanostructured layers 116A1 and 116A2, Fig. 1D) of the first transistor (GAA FETs 102A1, Fig. 1D) and the second transistor (GAA FETs 102A1, Fig. 1D).
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Regarding claim 10, Huang-285 in views of Mulfinger and Hong teaches the semiconductor structure of claim 2, wherein
Huang-285 further teaches that a bottom portion of the gate (gate structures 118A1 and 118A2, Fig. 1D) of the complementary field-effect transistor device (comprising GAA FETs 102A1 and 102A2, Fig. 1D) is between the one or more channels (nanostructured layers 116A1, Fig. 1D, [0024]) of the first transistor (GAA FET 102A1, Fig. 1D) and the first dielectric material (see first dielectric material in Illustrative Fig. 1, which illustrates the semiconductor device of Huang-285 (Fig, 1D of Huang-285) modified according to Mulfinger and Hong in claim 1), and wherein a top portion of the gate (gate structures 118A1 and 118A2, Illustrative Fig. 1, [0060]) of the complementary field-effect transistor device (comprising GAA FETs 102A1 and 102A2, Illustrative Fig. 1) is between the one or more channels (nanostructured layers 116A2, Illustrative Fig. 1) of the second transistor (GAA FET 102A2, Illustrative Fig. 1) and the second dielectric material (second dielectric material, Illustrative Fig. 1).
Regarding claim 11, Huang-285 in views of Mulfinger anf Hong teaches the semiconductor structure of claim 1, wherein
Huang-285 further teaches that the first transistor (GAA FET 102A1, Figs. 1B and 1D) is electrically isolated from the second transistor (GAA FET 102A1, Figs. 1B and 1D) by at least one layer of a middle dielectric isolation material (channel isolation layers 114A, Figs. 1B and 1D, [0024]).
Regarding claim 13, Huang-285 in view of Mulfinger and Hong teaches the semiconductor structure of claim 1, wherein
Huang-285 further teaches that the first transistor (GAA FETs 102A1, Figs. 1B and 1D) and the second transistor (GAA FETs 102A2, Figs. 1B and 1D) are both a gate-all-around transistors ([0023]: both transistors are gate-all-around transistors), and wherein each channel layer (nanostructured layers 116A1 and 116A2, Figs. 1B and 1D) of the first transistor (GAA FETs 102A1, Figs. 1B and 1D) and the second transistor (GAA FETs 102A2, Figs. 1B and 1D) are a layer of a nanosheet stack ([0029]: “nano structured layers 116A1, 116A2, 116B1, and/or 116B2 can have be in the form of nanosheets”).
Mann, on the other hand, teaches a CFET device (CFETs 50 and 54, Fig. 1, [0036], wherein
each channel layer (nanosheet channel layers 10, Fig. 1, [0031]) of the first transistor (comprising the bottom two channel layers 10 and source/drain regions 36, Fig. 1) and the second transistor (comprising the bottom two channel layers 10 and source/drain regions 38, Fig. 1) are a layer of a nanosheet stack ([0026]).
Mann further discloses that forming the channels from nanosheet layers in CFET devices increases the packing density in devices comprising multiple CFETs (Mann, [0005]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form channels of the CFET devices in the semiconductor structure of Huang in views of Mulfinger and Hong from a layer of a nanosheet stack, as taught by Mann, which would provide the benefit of decreasing the size of the semiconductor structure by increasing the packing density of the CFET devices (Mann, [0005]).
Regarding claim 15, Huang-285 teaches a method of forming a complementary field-effect transistor (CFET) device (semiconductor device 100, Fig. 6, [0060] and [0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”), the method comprising:
epitaxially growing (Fig. 7, [0063]-[0064]: “the formation of first and second stacks of superlattice structures 746A and 746B can include epitaxially growing the materials of nanostructured layers 716 and 748 and depositing the material of nanostructured isolation layers 714A-714B on substrate 104”) a nanosheet stack (superlattice structures 746A1-746A2 and 746B1-746B2, Fig. 7, [0064]) on a semiconductor substrate (substrate 104, Fig. 7, [0021]: “substrate 104 can be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and a combination thereof”);
selectively etching (Figs. 8-9, [0067]: “by etching first and second stacks of superlattice structures 746A and 746B through openings 850”) the nanosheet stack (superlattice structures 746A and 746B, Figs. 8-9) and a first top portion of the semiconductor substrate (substrate 104, Figs. 9A-B: the top surface of the substrate in the openings 850 is etched);
forming shallow trench isolations (STI) (STI region 112A and 112B, Figs. 1A and 7, [0023]) in the semiconductor substrate (substrate 104, Figs. 1A and 7) adjacent to remaining portions of the nanosheet stack (superlattice structures 746A and 746B, Figs. 1A and 7: the STI regions are formed earlier in the method of Huang-285, but still meets the claim limitation);
forming (Figs. 9-16) at least two stacked gate-all-around field-effect transistors (GAA FET 102A1, GAA FET 102A2, GAA FET 102B1, and GAA FET 102B2, Fig. 16F, [0071] and [0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”) separated by a middle dielectric isolation material (channel isolation layers 114A and 114B, Figs. 16A and 16F, [0025]) on the semiconductor substrate (substrate 104, Fig. 16A), wherein more than one first transistors (GAA FET 102A1 (GAA FETs 102A1-1, GAA FETs 102A1-2, and GAA FETs 102A1-3) and GAA FET 102B1, Figs. 16A and 16F) is under the middle dielectric isolation material (channel isolation layers 114A and 114B, Figs. 16A and 16F) and more than one second transistors (GAA FET 102A2 and GAA FET 102B2, Figs. 16A and 16F) is above the middle dielectric isolation material (channel isolation layers 114A and 114B, Figs. 16A and 16F);
performing gate cuts (isolation trench 1806, Fig. 18C, [0044]) through a portion of each gate (gate structures 1518B-1, Fig. 17C) that is between the more than one first transistors (GAA FET 102A1 and GAA FET 102B1, Fig. 18C) and the more than one second transistors (GAA FET 102A2 and GAA FET 102B2, Fig. 18C), wherein the gate cuts (isolation trench 1806, Fig. 18C) go through the STI (STI region 112, Fig. 18C (STI region in the middle which is not labeled)) adjacent to the more than one first transistors (GAA FET 102A1 and GAA FET 102B1, Fig. 18C) and the first top portion of the semiconductor substrate (fin structures 110A-B, Fig. 18C, [0024]);
depositing a second dielectric material (filling isolation trench 1806 with nitride layer 1906, Fig. 19C, [0074]);
performing a planarization (nitride layer 1906, Fig. 20C, [0080]: the nitride layer 1806 is planarized to become dielectric fill portion 106A).
wherein, in the CFET device (semiconductor device 100, Fig. 20C) formed by the method, the gate cuts (isolation trench 1806, Fig. 20C) lack a conductive fill material disposed in the gate cut (isolation trench 1806, Fig. 20C).
Huang-285, however, does not teach
filling the gate cuts with a first dielectric; and
recessing the first dielectric material.
Mulfinger, on the other hand, teaches the usage of stress-inducing isolation dielectric materials (first and second stress-inducing isolation dielectrics 144 and 150, Fig. 5, [0033]) around active regions (first active region 130 (labeled as SOI 118) and second active region 132, Fig. 5, [0033]) in a multi field-effect transistor (FET) device (the device in Fig. 5 has two n-type FETs and two p-type FETs, Fig 5, [0033]) to improve the performance of each transistor in the device by inducing a proper stress to each active region (Abstract). Based on the fact that the tensile stress enhances electron mobility (or drive currents) in an n-channel FET (NFET) while compressive stress enhances hole mobility in a p-channel FET (PFET) ([0003]), Mulfinger discloses that performance improvements in NFET devices can be accomplished by replacing the isolation material (such as in a trench isolation structure) next to the active region (channel) with a tensile-stress-inducing dielectric material, and similarly, performance improvements in PFET devices can be accomplished by replacing the isolation material (such as in a trench isolation structure) next to the active region with a compressive-stress-inducing dielectric material ([0004] and [0006]). Furthermore, a person of ordinary skill in the art would also know that such a tensile and compressive stress inducing approach has been utilized in CFETs, as evidenced by Hong (US 20220302172 A1). Hong teaches a method for forming a CFET device (Figs. 3A-B), where upper nanosheet transistors UNT are NFETs (or PFETs), lower nanosheet transistors LNT are PFETs (or NFETs) ([0040], and diffusion break structures (DBS) 300 between adjacent CFETs is filled a first dielectric material (DBS 300L, Fig. 3B, [0061]) under a second dielectric material (DBS 300U, Fig. 3B, [0061]), so that “a drive current performance of the multi-stack semiconductor device 10 may be enhanced by effectively controlling stress applied to the lower nanosheet transistors LNT, that is, PFETs, at a lower stack and the upper nanosheet transistors UNT, that is, NFETs, at an upper stack using the lower DDB structure 100L and the upper DDB structure 100U” ([0043]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the more than one first and second transistors of Huang-285 are a PFET/NFET pair ([0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”), and the gate cuts (isolation trench 1806, Fig. 20C) in the device of Huang-285 are used as isolation structures ([0080]), and would be motivated by the teachings of Mulfinger and Hong to modify the method of Huang-285 to replace the filling material (dielectric fill portion 106A, Fig. 20C) in the gate cut (isolation trench 1806, Fig. 20C) such that the bottom portion of the gate cut (isolation trench 1806, Fig. 20C) is filled with one type of dielectric material (second dielectric material) until the border between the first and second transistors (GAA FETs 102A1/102B1 and GAA FETs 102A2/102B2, Fig. 20C) to be able to induce a proper type of stress on the first transistors, and then the rest of the gate cut ((isolation trench 1806, Fig. 20C), as taught by Hong, is filled with another type of dielectric material (first dielectric material) to be able to apply a proper type of stress on the second transistors. These modifications would provide the benefit of improving the performance of both transistors, as taught by Mulfinger ([0006]-[0007]) and Hong ([0043]).
Thus, the combination of Huang-285, Mulfinger and Hong teaches
filling the gate cuts with a first dielectric (at least until the border between the first transistor and second transistor).
The combination of Huang-285, Mulfinger and Hong, however, does not explicitly teach that the method comprises
recessing the first dielectric material.
However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that filling a narrow gate cut structure with a high aspect ratio structure (Fig. 18C, [0073]: height to width ratio of about 9 to 22) requires conformal deposition or using a flowable material to overfill the gate cut and then apply an etching process to obtain a desired filling depth (see Huang [0074]). Therefore, it would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply the gate cut filling method of Huang two times in a row for both dielectric layers, by recessing the first dielectric material to a desired depth before depositing the second dielectric material. Thus, the combination of Huang-285, Mulfinger and Hong meets all the limitations of claim 15.
Regarding claim 16, Huang-285 in views of Mulfinger and Hong teaches the method of claim 15, wherein
Huang-285 further teaches that the method further comprises:
forming top contacts (contact plugs 140 of transistors 102A2 and 102B2, Figs. 22A and 22D (note that these figures are flipped upside down), [0077]) and a plurality of top interconnection layers (not shown in figures, but see [0038]: “he front-side S/D contact structures can be electrically connected to power supplies and/or other active devices through front-side interconnect structure (not shown) formed on GAA FETs 102A2 and 102B2.”, and interconnect structures typically include a plurality of interconnect layers);
forming a back contact (any of the contact plugs 140 of transistors 102A1 and 102B1, Figs. 22A and 22D (note that these figures are flipped upside down), [0077]) for the CFET device (semiconductor device 100, Figs. 22A and 22D); and
forming a plurality of bottom interconnect layers (not shown in figures, but see [0038]: “the back-side S/D contact structures can be electrically connected to power supplies and/or other active devices through back-side interconnect structure (not shown) formed on the back-side S/D contact structures.”, and interconnect structures typically include a plurality of interconnect layers) connected to a bottom contact (any of the contact plugs 140 of transistors 102A1 and 102B1, Figs. 22A and 22D).
Regarding claim 18, Huang-285 in view of Mulfinger and Hong teaches the method of claim 15, wherein
Huang-285 further teaches that the more than one first transistor (GAA FET 102A1 and GAA FET 102B1, Figs. 18C-D) is a PFET ([0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”, and therefore GAA FETs 102A1-102B1 can be PFETs, and then GAA FETs 102A2-102B2 are NFETs).
Huang-285, however, does not teach that the first dielectric material creates a compression stress on a first transistor of the at least two stacked gate-all-around field-effect transistors.
Mulfinger, however, teaches that the stress inducing dielectric material would be selected from materials that can induce a compressive stress if used in a PFET device ([0003]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated by the teachings of Mulfinger to use a first dielectric material in the method of Huang-285 in views of Mulfinger and Hong such that the first dielectric material creates a compression stress on a first transistor of the at least two stacked gate-all-around field-effect transistors, which would provide the benefit of improving the performance of the first transistors by selecting the proper stress inducing dielectric material based on the type of the transistor (Mulfinger, Abstract).
Thus, Huang-285, Mulfinger, and Hong meets all the limitations of claim 18.
Regarding claim 19, Huang-285 in view of Mulfinger and Hong teaches the method of claim 15, wherein
Huang-285 further teaches that the second transistor (GAA FET 102A2 and GAA FET 102B2, Figs. 18C-D) is an NFET ([0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”, and therefore GAA FETs 102A1-102B1 can be PFETs, and then GAA FETs 102A2-102B2 are NFETs).
Huang-285, however, does not teache that the second dielectric material creates a tensile stress on a second transistor of the at least two stacked gate-all-around field-effect transistors.
Mulfinger, however, teaches that the stress inducing dielectric material would be selected from materials that can induce a tensile stress if used in an NFET device ([0003]).
Therefore, a person of ordinary of ordinary skill in the art before the effective filing date of the claimed invention would be motivated by the teachings of Mulfinger to use a second dielectric material in the method of Huang-285 in view of Mulfinger and Hong such that the second dielectric material creates a tensile stress on a second transistor of the at least two stacked gate-all-around field-effect transistors, which would provide the benefit of improving the performance of the first transistors by selecting the proper stress inducing dielectric material based on the type of the transistor (Mulfinger, Abstract).
Thus, Huang-285, Mulfinger, and Hong meets all the limitations of claim 19.
Regarding claim 20, Huang-285 in view of Mulfinger and Hong teaches the method of claim 15, wherein
Huang-285, Mulfinger and Hong, individually, do not teach that a PFET in the at least two stacked gate-all-around field- effect transistors is adjacent to a dielectric material that is creating a compressive stress on a plurality of channels of the PFET and an NFET in the at least two stacked gate-all-around field- effect transistors is adjacent to the second dielectric material that is creating a tensile stress on the plurality of channels of the NFET.
However, Huang-285 teaches that all the first transistors (GAA FET 102A1 and GAA FET 102B1, Figs. 18C-D) are PFETs ([0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”, and therefore GAA FETs 102A1-102B1 can be PFETs, and then GAA FETs 102A2-102B2 are NFETs), and all the second transistors (GAA FET 102A2 and GAA FET 102B2, Figs. 18C-D) are NFETs (see above). Mulfinger further teaches that that performance improvements in NFET devices can be accomplished by using a tensile-stress-inducing dielectric material as an isolation material (such as in a trench isolation structure) next to the active region (channel), and similarly, performance improvements in PFET devices can be accomplished by using another dielectric material, which can induce compressive stress, as an isolation material next to the active region ([0004] and [0006]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would combine the teachings of Huang-285 and Mulfinger, and select, in the method of Huang-285 in views of Mulfinger and Hong, the first dielectric material next to the first transistor (PFET) to be a compressive-stress inducing material and the second dielectric material next to the second transistor (NFET) to be a tensile-stress inducing material.
Accordingly, the combination of Huang-285, Mulfinger, and Hong teaches that a PFET in the at least two stacked gate-all-around field- effect transistors is adjacent to a dielectric material that is creating a compressive stress on a plurality of channels of the PFET and an NFET in the at least two stacked gate-all-around field- effect transistors is adjacent to the second dielectric material that is creating a tensile stress on the plurality of channels of the NFET.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang-285 (US 2021/0407999 A1) in views of Mulfinger (US 2021/0398862 A1) and Hong (US 2022/0302172 A1) as applied to claims 1-11, 13, 15-16, and 18-20 above, and further in view of another embodiment of Lin (US 2022/0216340 A1).
Regarding claim 12, Huang-285 in view of Mulfinger and Hong teaches the semiconductor structure of claim 1, wherein
Huang-285 further teaches that the semiconductor structure of claim 1 further comprises:
a second top contact (contact plug 140 ([0037]) on the top right in Fig. 1B (see second top contact in Illustrative Fig. 2 which is an annotated version of Fig. 1B)) connecting a second top surface (top surface of S/D regions 120A2-1, Illustrative Fig. 2, [0025]) of a second source/drain (S/D regions 120A2-1, shown as second S/D of the second transistor) of the second transistor (GAA FET 102A2 in the middle, Illustrative Fig. 2) to the plurality of frontside interconnect layers (not shown in figures, see [0038]: “In some embodiments, the front-side S/D contact structures can be electrically connected to power supplies and/or other active devices through front-side interconnect structure (not shown) formed on GAA FETs 102A2 and 102B2.”); and
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a backside contact (S/D contact structures 122A1-1 ([0040]) on the bottom left, labeled as backside contact in Illustrative Fig. 2) connecting a bottom surface of the second source/drain (bottom surface of S/D regions 120A1-1, shown as second S/D of the first transistor, Illustrative Fig. 2) of the first transistor (GAA FET 102A2 in the middle, Illustrative Fig. 2) to a plurality of backside interconnect layers (not shown in figures, see [0038]: “In some embodiments, the back-side S/D contact structures can be electrically connected to power supplies and/or other active devices through back-side interconnect structure (not shown) formed on the back-side S/D contact structures.”).
Huang-285, Mulfinger and Hong, however, do not teach
a first top contact connecting a first top surface of a first source/drain of the first transistor to a plurality of frontside interconnect layers.
Lin, on the other hand, teaches contact structures for a CFET device (workpiece 200, Fig. 20, [0003]-[0006]), wherein the contact structure comprises:
a first top contact (second frontside contact 278, Fig. 20, [0037]) connecting a first top surface (second bottom source/drain feature 228-2, Fig. 20, [0036]) of a source/drain (second bottom source/drain feature 228-2, Fig. 20, [0036]; second bottom source/drain feature 228-2 is analogous to the source feature 422PS of Chen in Fig. 33A) of the first transistor (the bottom transistors in Fig. 20, which corresponds to the first transistor of the current application and of Huang-285 in views of Mulfinger and Hong) to the frontside (top surface of the device).
Lin further discloses that for performing some logical operations local electrical connection between a source/drain feature of the first multi-gate device and a source/drain feature of the second multi-gate device in a CFET is needed [0011], and a local contact feature, such as the first top contact above, that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([0012]) is beneficial in reducing the device size and simplify manufacturing process and device structure ([0003]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention, who is aiming to form a device for performing logic operations requiring the source/drain regions of the top and bottom transistors to be connected, would be motivated to modify the semiconductor structure of Huang-285 in views of Mulfinger and Hong to form a first top contact as disclosed by Lin, which would further provide the benefit of simplifying the device structure and manufacturing process.
Thus, the combination of Huang-285, Mulfinger, Hong, and Lin meets all the limitations of claim 12.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang-999 (US 2021/0407999 A1) in views of Mulfinger (US 2021/0398862 A1), Hong (US 2022/0302172 A1) and Mauder (US 2012/0018798 A1).
Regarding claim 14, Huang-999 teaches a semiconductor structure (integrated circuit structure 200, Fig. 2, [0037]) comprising:
a plurality of cells (see cells as shown in Illustrative Fig. 3, which is an annotated version of Fig. 2 of Huang-999) of complementary field-effect transistor (CFET) devices (see first CFET and second CFET as indicated in Illustrative Fig. 3, [0028]: the bottom transistors are PFETs and upper transistors are NFETs), wherein the CFET devices (first CFET and second CFET, Illustrative Fig 2) each have a top transistor (transistor 2 of cell 1 and transistor 2 of cell 2, Illustrative Fig. 3) under a bottom transistor (transistor 1 of cell 1 and transistor 1 of cell 2, Illustrative Fig. 3);
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a first CFET device (first CFET, Illustrative Fig. 3) in a first cell (cell 1, Illustrative Fig. 3) of the plurality of cells (cell 1 and cell 2, Illustrative Fig. 3) and a second CFET device (second CFET, Illustrative Fig. 3) in a second cell (cell 2, Illustrative Fig. 3) of the plurality of cells (cell 1 and cell 2, Illustrative Fig. 3) adjacent to the first cell (cell 1, Illustrative Fig. 3);
a gate cut (backbone 201, Illustrative Fig. 3, [0037]: “… backbone 201, which may be a dielectric wall”) between the first CFET device (first CFET, Illustrative Fig. 3) and the second CFET device (second CFET, Illustrative Fig. 3); and
wherein the gate cut (backbone 201, Illustrative Fig. 3) lacks a conductive fill material disposed in the gate cut (backbone 201, Illustrative Fig. 3: backbone 201 is completely made of a dielectric material, [0037]).
Huang-999, however, does not teach that
a first dielectric material abuts a first portion of each channel in the top transistor of the first CFET device and abuts a second portion of each channel in the top transistor of the second CFET device, wherein the first dielectric material has a fixed charge with a first polarity; and
a second dielectric material abuts a third portion of each channel in the bottom transistor of the first CFET device and abuts a fourth portion of each channel in the bottom transistor of the second CFET device, wherein the second dielectric material has the fixed charge with a second polarity.
Mulfinger, on the other hand, teaches the usage of stress-inducing isolation dielectric materials (first and second stress-inducing isolation dielectrics 144 and 150, Fig. 5, [0033]) around active regions (first active region 130 (labeled as SOI 118) and second active region 132, Fig. 5, [0033]) in a multi field-effect transistor (FET) device (the device in Fig. 5 has two n-type FETs and two p-type FETs, Fig 5, [0033]) to improve the performance of each transistor in the device by inducing a proper stress to each active region (Abstract). Based on the fact that the tensile stress enhances electron mobility (or drive currents) in an n-channel FET (NFET) while compressive stress enhances hole mobility in a p-channel FET (PFET) ([0003]), Mulfinger discloses that performance improvements in NFET devices can be accomplished by replacing the isolation material (such as in a trench isolation structure) next to the active region (channel) with a tensile-stress-inducing dielectric material, and similarly, performance improvements in PFET devices can be accomplished by replacing the isolation material (such as in a trench isolation structure) next to the active region with a compressive-stress-inducing dielectric material ([0004] and [0006]). Furthermore, a person of ordinary skill in the art would also know that such a tensile and compressive stress inducing approach has been utilized in CFETs, as evidenced by Hong (US 20220302172 A1). Hong teaches a CFET device (Figs. 3A-B), where upper nanosheet transistors UNT are PFETs (or NFETs), lower nanosheet transistors LNT are NFETs (or PFETs) ([0040], and diffusion break structures (DBS) 300 between adjacent CFETs is filled a first dielectric material (DBS 300L, Fig. 3B, [0061]) under a second dielectric material (DBS 300U, Fig. 3B, [0061]), so that “a drive current performance of the multi-stack semiconductor device 10 may be enhanced by effectively controlling stress applied to the lower nanosheet transistors LNT, that is, PFETs, at a lower stack and the upper nanosheet transistors UNT, that is, NFETs, at an upper stack using the lower DDB structure 100L and the upper DDB structure 100U” ([0043]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would realize that gate cuts in the device of Huang-999 (backbone 201, Illustrative Fig. 3) are used as isolation structures ([0037]), and would be motivated by the teachings of Mulfinger to modify the gate cuts in the semiconductor structure of Huang-999 to replace the filling material in the gate cut (backbone 201, Illustrative Fig. 3) such that the bottom portion of the gate cut (backbone 201, Illustrative Fig. 3) is filled with one type of dielectric material (second dielectric material) until the border between the bottom and top transistors (Illustrative Fig. 3) to be able to induce a proper type of stress on the bottom transistor, and then the rest of the gate cut (backbone 201, Illustrative Fig. 3) is filled with another type of dielectric material (first dielectric material) to be able to apply a proper type of stress on the top transistor. These modifications would provide the benefit of improving the performance of both transistors, as taught by Mulfinger ([0006]-[0007]) and Hong (Figs. 3A-3B, [0043]).
Thus, the combination of Huang-999, Mulfinger, and Hong (see Illustrative Fig. 4 (a modified version of Huang-999’s Fig. 2 by incorporating first and second dielectric material) showing the semiconductor structure of Huang-999 modified by the teachings of Mulfinger and Hong) meets the limitations
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a first dielectric material (second dielectric material, Illustrative Fig. 4) abuts a first portion (right side surface, Illustrative Fig. 4) of each channel (nanowires or nanoribbons 203 of transistor 2 of cell 1, Illustrative Fig. 4) in the top transistor (transistor 2 of cell 1, Illustrative Fig. 4) of the first CFET device (first CFET, Illustrative Fig. 4) and abuts a second portion (left side surface, Illustrative Fig. 4) of each channel (nanowires or nanoribbons 203 of transistor 2 of cell 2, Illustrative Fig. 4) in the top transistor (transistor 2 of cell 2, Illustrative Fig. 4) of the second CFET device (second CFET, Illustrative Fig. 4), and
a second dielectric material (first dielectric material, Illustrative Fig. 4) abuts a third portion (right side surface, Illustrative Fig. 4) of each channel (nanowires or nanoribbons 203 of transistor 1 of cell 1, Illustrative Fig. 4) in the bottom transistor (transistor 1 of cell 1, Illustrative Fig. 4) of the first CFET device (first CFET, Illustrative Fig. 4) and abuts a fourth portion (left side surface, Illustrative Fig. 4) of each channel (nanowires or nanoribbons 203 of transistor 1 of cell 2, Illustrative Fig. 4) in the bottom transistor (transistor 2 of cell 2, Illustrative Fig. 4) of the second CFET device (second CFET, Illustrative Fig. 4).
However, Huang-999, Mulfinger and Hong do not teach that the first dielectric material has a fixed charge with a first polarity, and the second dielectric material has the fixed charge with a second polarity.
Mauder, on the other hand, teaches a method for protecting semiconductor devices, particularly field-effect transistors, against injection of hot charge carriers into a dielectric region located next to the active region when the device is exposed to a high load ([0001] and [0003]). Mauder discloses that using a dielectric material with a fixed charge matching the polarity (doping type) of the active region would reduce the carrier leakage in to the neighboring dielectric layer ([0008]).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the first and second dielectric layers of the semiconductor structure of Huang-999 in views of Mulfinger and Hong is in direct contact with the active layers (channels) of the top and bottom transistors, and therefore, would benefit from the teachings of Mauder. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to choose the dielectric materials such that the first dielectric material has a fixed charge with a first polarity, and the second dielectric material has the fixed charge with a second polarity, where polarities are determined by the doping types of the channels of the top and bottom transistors. These modifications would provide the benefit of reducing hot carrier injection into the dielectric layers (Mauder, [0001]) and minimize the risk of device degradation (Mauder, [0004]).
Thus, the combination of Huang-999, Mulfinger, Hong, and Mauder meets all the limitations of claim 14.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Huang-285 (US 2021/0407999 A1) in views of Mulfinger (US 2021/0398862 A1) and Hong (US 2022/0302172 A1) as applied to claims 1-11, 13, 15-16, and 18-20 above, and further in view of another embodiment of Xie (US 2021/0320035 A1).
Regarding claim 17, Huang-285 in views of Mulfinger and Hong teaches the method of claim 15, wherein
Huang-285 teaches forming the at least two stacked gate-all-around field-effect transistors (semiconductor device 100, Fig. 1A, [0023]: “Stacked FETs 102A and 102B can be referred to as "complementary FETs (CFETs) 102A and 102B" when GAA FETs 102A1-102B1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102A2-102B2.”) separated by the middle dielectric isolation material (dielectric fill portion 106A, Fig. 1D, [0080]) on the semiconductor substrate (substrate 104, Fig. 1B, [0021]).
Huang-285, Mulfinger, and Hong, however, do not provide full details of the method of forming the at least two stacked gate-all-around field-effect transistors, and also differ from the method of the current application.
Xie, on the other hand, teaches an alternative method (see Fig. 18 for block diagram, and Figs. 1-17 for individual steps) for forming the at least two stacked gate-all-around field-effect transistors (Fig. 17: three stacked gate-all-around CFETs are shown) which comprises
forming dummy gates (dummy gates 402, Figs. 4, [0037]) above each shallow trench isolation (shallow trench isolation (STI) structures 304, Fig. 4-X, [0034]: the STI structures are not labeled in Fig. 4 (see Fig. 3 for labels)) and on and around portions of the remaining portions of the nanosheet stack (channel layers 204, first sacrificial layers 206, and second sacrificial layers 208, Fig. 4-X, [0030]: channel layers 204, first sacrificial layers 206, and second sacrificial layers 208 are not labeled in Fig. 4 (see Figs. 2-3 for labels); the dummy gate is the region on the STI structures, and on and around the layers (see Fig. 4-Y));
removing two layers of a first sacrificial material (second sacrificial layers 208 (one around the middle of the layers and the other at the bottom of the layers), Figs. 4 and 5, [0038]: second sacrificial layers 208 are not labeled in Figs. 4 and 5 (see Fig. 3 for labels)) in the remaining portions of the nanosheet stack (channel layers 204, first sacrificial layers 206, and second sacrificial layers 208, Figs. 4 and 5)
conformally depositing a dielectric isolation material (Fig. 6, [0039]: “Spacer material is conformally deposited …”) where a first sacrificial dielectric material (second sacrificial layers 208 becomes middle spacer 602 and bottom spacer 604, Figs. 6) was and around the dummy gates (dummy gates 402, Figs. 6 (see Fig. 4 for the label), [0037]: the deposited material around the dummy gates is shown as dummy gate spacers 606 in Fig. 6),
removing horizontal portions of the dielectric isolation material ([0039]: “The spacer material can be masked and anisotropically etched, as appropriate, to preserve the dummy gate spacers 606 while removing the spacer material from the sidewalls of the fins 302.”) to form a bottom dielectric isolation (bottom spacer 604, Fig. 6, [0040]) on the semiconductor substrate (semiconductor substrate 202, Fig. 6 (see Fig. 2 for the label), [0035]), a middle dielectric isolation (middle spacer 602, Fig. 6, [0039]) in a middle area of the nanosheet stack (fins 302, Fig. 6, [0039]), and gate spacers (dummy gate spacers 606, Fig. 6, [0039]) around the dummy gates (dummy gates 402, Figs. 6);
selectively removing the portions of the remaining portions of the nanosheet stack (fins 302, Figs. 6 and 7, [0040]) between the dummy gates (dummy gates 402, Figs. 6 and 7, [0040]: “The fins 302 are etched away in the regions between the dummy gates, …”);
laterally etching an outer edge (location of inner spacers 702, Fig. 7, [0041]) of a second sacrificial material (first sacrificial layers 206, Fig. 7 (see Fig 2 for labels), [0041]: “… a selective etch can be used to recess the first sacrificial layers 206.”);
forming inner spacers (inner spacers 702, Fig. 7, [0041]) adjacent to the remaining portions of the second sacrificial material (first sacrificial layers 206, Fig. 7 (see Fig. 2 for the label));
epitaxially growing a bottom source/drain (lower source/drain regions 802, Fig. 8, [0042]: “Lower source/drain regions 802, for the lower device 210, are epitaxially grown…”) adjacent to a bottom portion of the remaining portions of the nanosheet stack (lower portions of the trenches between the three pillars, Fig. 8);
recessing the bottom source/drain (Fig. 8, [0042]: “After the epitaxial material is grown, any epitaxial material formed over top nanosheets is etched back, below the height of the middle spacer 602.”).
depositing a dielectric material (isolation layer 902, Fig. 9, [0044]) on the bottom source/drain (lower source/drain regions 802, Fig. 9 (see Fig. 8 for the label), [0044]);
epitaxially growing a top source/drain (upper source/drain regions 1002, Fig. 10, [0045]: “upper source/drain regions 1002 are epitaxially grown … “) adjacent to a second top portion (above the isolation layer 902, Fig. 10) of the remaining portions of the nanosheet stack (upper portions of the trenches between three layered structures, Fig. 10); and
performing the planarization ([0046]: chemical mechanical planarization performed after a final dielectric material is deposited on top).
Thus, Xie teaches all the limitations of forming the at least two stacked gate-all-around field effect transistors. Xie, further discloses that the method of Xie provides CFET devices with good power efficiency and structural stability ([0027]), and a more robust manufacturing method due to inclusion of sacrificial layers in manufacturing ([0027]-[0028]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who aims to improve the CFET devices (Xie, [0003]) formed by the method of Huang-285, Mulfinger, and Hong, while also improving the method of manufacturing them, would be motivated to modify the method of Huang-285 in views of Mulfinger and Hong according to the teachings of Xie to form the at least two stacked gate-all-around field-effect transistors as disclosed by Xie, which would provide the benefits of improved power efficiency, structural stability, and/or fabrication processes (Xie, [0003]).
Thus, the combination of Huang-325, Mulfinger, Mulfinger, and Hong meets all the limitations of claim 17.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 12, and 14-17 per response dated on 1/13/2026.
Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amendments to independent claims 1, 14, and 15 overcame their corresponding rejections made previously based on the prior art Chen (US 2023/0402528 A1) and Mulfinger (US 2021/0398862 A1) for claim 1, Chen, Mulfinger, and Mauder (US 2012/0018798 A1) for claim 14, and Chen, Xie (US 2021/0320035 A1), and Mulfinger for claim 15.
However, amended independent claims 1 and 15 are now rejected under new grounds based on a new prior-art, Huang-285 (US 2023/0307285 A1) and Hong (US 2022/0302172 A1), combined with Mulfinger in the current office action. Rejections are also made on claims that are dependent on either claim 1 or claim 15. Amended claim14 is also rejected under new grounds based on another new prior art, Huang-999 (US 2021/0407999 A1), combined with Mulfinger and Hong. Claims 16-20, which are dependent on claim 16, are also rejected.
For the purpose of compact prosecution, the Examiner notes that incorporating limitations about different layers and their spatial relations might make independent claims 1, 14, and 15 overcome their corresponding rejections based on the prior art of record.
The Examiner is available for an interview at Applicant' s convenience if the Applicant would like to discuss the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhou (US 2020/0126867 A1) teaches forming stress-inducing dielectric materials for PFET and NFET devices, which is relevant to claims 1-6, 8, 14-15, and 18-20.
Wu (US 10176995 B1) teaches forming stress-inducing dielectric materials for PFET and NFET devices, which is relevant to claims 1-6, 14-15, and 18-20.
Paul (US 10840146 B1) teaches stacked nanosheet transistors with a gate cut isolation, which is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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