DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant' s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Based on the previously cited prior art Chang and new reference Huang (US20220310603A1) the claims 1, 3 - 6, 8 - 9, 11 - 14, and 21 - 29 are rejected.
Response to Amendment
Applicant’s amendment to claim 4 has been considered and resolve the claim objections. The claim objections has been withdrawn.
Applicant’s amendments to claims 11, 12, and 14 has been fully considered and resolve the 35 U.S.C. 112(b) rejections. The 35 U.S.C. 112(b) rejection has been withdrawn.
Applicant’s cancellation of claims 2, 7, 10, 15 - 20 has been acknowledged. Applicant’s newly added claims 21 – 29 have been fully considered and examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8 - 9, 21, 26 – 28 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (US20220310603A1; hereinafter Huang).
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Huang: FIG. 60B
Regarding Claim 1 (Currently Amended), Huang discloses a semiconductor device (semiconductor device or an integrated circuit structure), FIG. 60B reproduced above, [0178], comprising:
a channel (channel region of fin 112) over a backside layer (backside metal lines 345), FIG. 60B, [0032], [0060], [0065];
Huang [0032] discloses the portions of the semiconductor fins 112 underlying the gate structures be referred to as the channel regions. [0060] discloses a third ILD layer 310 is formed to cover the semiconductor fins 112. [0065] discloses a backside MLI (multilayer interconnection) structure 340 including a plurality of backside metallization layers 342 which includes backside metal lines 345 are formed over the third ILD layer 310. Therefore, the channel region of semiconductor fin 112 is over a backside layer 345.
a semiconductor structure (lower semiconductor portion of fins 112) between the channel (channel region of fins 112) and the backside layer (345), FIG. 60B, [0032].
Huang [0032] discloses the portions of the semiconductor fins 112 underlying the gate structures be referred to as the channel regions. The lower portions of the semiconductor fin 112 beneath the channel region corresponds to the semiconductor structure between the channel and the backside layer.
a dielectric fill (interlayer dielectric ILD 310) on the backside layer (345), including a first dielectric material (310 includes materials such as tetraethylorthosilicate (TEOS)-formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials), FIG. 60B, [0060], [0065];
a gate conductor (170 including metal layer 174 and are in contact with the fill metal 176) on the channel (channel region 112) that makes electrical contact with the backside layer (345) through a hole (opening O4a filled with 335a) in the dielectric fill (310), FIG. 60B, [0061], [0064], [0065]; and
a dielectric liner (spacer structures 320) on sidewalls of the dielectric fill (inner sidewalls of opening O4a formed in 310) and on a sidewall of the semiconductor structure (sidewall of opening O4a which passes through lower semiconductor portion of fin 112), including a second dielectric material (spacer structures 320 include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiCxOyNz, high-k dielectric materials, or combinations thereof.) in contact with the gate conductor (320 contacts 170 via 335a) at the dielectric fill (310), wherein the dielectric liner (320) covers opposing sidewalls of the hole (O4a) in the dielectric fill (310), FIG. 60B, [0063], [0069].
Regarding Claim 8 (Original), Huang discloses the semiconductor device of claim 1, wherein the first dielectric material is silicon dioxide (310 is an oxide layer (e.g., silicon dioxide), [0180]) and the second dielectric material is silicon nitride (320 includes silicon nitride, [0063]).
Regarding Claim 9 (Currently Amended), Huang discloses a semiconductor device (semiconductor device or an integrated circuit structure), FIG. 60B, [0178] comprising:
a first channel (channel region of first 112) over a backside layer (345) in a first device region (a first device region including first semiconductor fin 112); FIG. 60B, [0028], [0032], [0060], [0065].
a second channel (channel region of second 112) over the backside layer (345) in a second device region (a second device region including second semiconductor fin 112), FIG. 60B, [0028], [0032], [0060], [0065].
Huang [0028] discloses one or more semiconductor fins 112 are formed on the substrate 110, which corresponds to the first and second semiconductor fins 112. Huang [0032] discloses the portions of the semiconductor fins 112 underlying the gate structures be referred to as the channel regions. [0060] discloses a third ILD layer 310 is formed to cover the semiconductor fins 112. [0065] discloses a backside MLI (multilayer interconnection) structure 340 including a plurality of backside metallization layers 342 which includes backside metal lines 345 are formed over the third ILD layer 310. Therefore, a first channel region of semiconductor fin 112 is over a backside layer 345 in the first device region and a second channel region of semiconductor fin 112 is over a backside layer 345 in the second device region.
a semiconductor structure (lower portions of first and second fins 112) between the first channel (channel region of first 112) and the backside layer (345) and between the second channel (channel region of second 112) and the backside layer (345), FIG. 60B, [0032];
Huang [0032] discloses the portions of the semiconductor fins 112 underlying the gate structures be referred to as the channel regions. The lower portions of the first and the second semiconductor fins 112 beneath the respective channel regions corresponds to the semiconductor structure between the first and second channels and the backside layer.
a dielectric fill (interlayer dielectric ILD 310) that includes a first dielectric layer, (310 includes materials such as tetraethylorthosilicate (TEOS)-formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials) on the backside layer (345) between the first device region and the second device region (first and second device region including first and second semiconductor fins 112 respectively), FIG. 60B, [0060], [0065].
a gate conductor (170 including metal layer 174 and are in contact with the fill metal 176) on the first channel and the second channel (channel regions of first 112 and second 112) that makes electrical contact with the backside layer (345) through a hole (opening O4a filled with 335a) in the dielectric fill (310), FIG. 60B, [0061], [0064], [0065]; and
a dielectric liner (spacer structures 320) on sidewalls of the dielectric fill (inner sidewalls of opening O4a formed in 310) and on a sidewall of the semiconductor structure (sidewall of opening O4a which passes through lower semiconductor portion of fin 112), including a second dielectric material (spacer structures 320 include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiCxOyNz, high-k dielectric materials, or combinations thereof), in contact with the gate conductor (320 contacts 170 via 335a) at the dielectric fill (310), wherein the dielectric liner (320) covers opposing sidewalls of the hole (O4a) in the dielectric fill (310), FIG. 60B, [0063], [0069].
Regarding Claim 21 (New), Huang discloses a semiconductor device (semiconductor device or an integrated circuit structure), FIG. 60B, [0178], comprising:
a channel (channel region of fin 112) over a backside layer (backside metal lines 345), FIG. 60B, [0032], [0060], [0065].
Huang [0032] discloses the portions of the semiconductor fins 112 underlying the gate structures be referred to as the channel regions. [0060] discloses a third ILD layer 310 is formed to cover the semiconductor fins 112. [0065] discloses a backside MLI (multilayer interconnection) structure 340 including a plurality of backside metallization layers 342 which includes backside metal lines 345 are formed over the third ILD layer 310. Therefore, the channel region of semiconductor fin 112 is over a backside layer 345.
a semiconductor structure lower semiconductor portion of fin 112) between the channel (channel region of fins 112) and the backside layer (345), FIG. 60B, [0032].
Huang [0032] discloses the portions of the semiconductor fins 112 underlying the gate structures be referred to as the channel regions. The lower portions of the semiconductor fin 112 beneath the channel region corresponds to the semiconductor structure between the channel and the backside layer.
a dielectric fill (interlayer dielectric ILD 310) on the backside layer (345), FIG. 60B, [0065];
a gate conductor (170 including metal layer 174 and are in contact with the fill metal 176) on the channel (channel region 112) that makes electrical contact with the backside layer (345) through a hole (opening O4a filled with 335a) in the dielectric fill (310), FIG. 60B, [0061], [0064], [0065]; and
a dielectric liner (spacer structures 320) on sidewalls of the dielectric fill (inner sidewalls of opening O4a formed in 310) and on a sidewall of the semiconductor structure (sidewall of opening O4a which passes through lower semiconductor portion of fin 112), in contact with the gate conductor (320 contacts 170 via 335a) at the dielectric fill (310), wherein the dielectric liner (320) covers opposing sidewalls of the hole (O4a) in the dielectric fill (310), FIG. 60B, [0063], [0069].
Regarding Claim 26 (New), Huang discloses the semiconductor device of claim 21, wherein the dielectric fill (310) includes a first dielectric material (310 includes materials such as tetraethylorthosilicate (TEOS)-formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials) and the dielectric liner (320) includes a second dielectric material (spacer structures 320 include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiCxOyNz, high-k dielectric materials, or combinations thereof), [0060], [0063].
Regarding Claim 27 (New), Huang discloses the semiconductor device of claim 26, wherein the first dielectric material is silicon dioxide (310 is an oxide layer (e.g., silicon dioxide), [0180]) and the second dielectric material is silicon nitride (320 includes silicon nitride, [0063]).
Regarding Claim 28 (New), Huang discloses the semiconductor device of claim 9, wherein the first device region (a first device region including first semiconductor fin 112) includes an n-type field effect transistor and the second device region (a second device region including second semiconductor fin 112) includes a p-type field effect transistor, [0028].
Huang [0028] discloses the semiconductor fins 112 form FinFETs and may be N-type or P-type.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, 11-14, 22-25, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chang et al. (US20210375761A1; hereinafter Chang).
Regarding Claim 3, (Original) Huang discloses the semiconductor device of claim 1, further comprising:
a source/drain structure (150) in electrical contact with the channel (channel region of 112), FIG. 60B, [0037];
Huang does not disclose “a bottom source/drain contact that makes electrical contact between the source/drain structure and a power line in the backside layer.”
In a similar art, Chang discloses a nanostructure field-effect transistor (nano-FET), [0005].
Chang discloses: further comprising: a source/drain structure (92A) in electrical contact with the channel (55), FIG. 12C, [0056];
Chang FIG. 29A, [0084] discloses backside vias 130 may be electrically connected to the epitaxial source/drain regions 92 through the second silicide regions 129. Chang [0094] discloses the power regions 140P of the backside interconnect structure 140 may include routing from the transistor structures 109 and the backside vias 130 to the power rails 135P.
The combination of Huang and Chang discloses: a bottom source/drain contact (Chang: backside vias 130) that makes electrical contact between the source/drain structure (Chang: 92A) and a power line (Chang: power rails 135P) in the backside layer (Huang: 345, FIG. 60B, [0065]).
Chang discloses that a device as taught routing the power supply lines through the backside interconnect structure may reduce the total routing used in the front-side interconnect structure, which improves routing performance by decreasing routing density [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device such that one or more of the metal lines may be configured as a power line in order to improve routing performance by decreasing routing density as disclosed by Chang [0011].
Regarding Claim 4 (Currently Amended), The combination of Huang and Chang discloses the semiconductor device of claim 3.
Huang does not disclose “wherein the dielectric fill and the dielectric liner are part of a shallow trench isolation (STI) structure that runs parallel to an orientation of the channel and the source/drain structure.”
Chang discloses: wherein the dielectric fill and the dielectric liner are part of a shallow trench isolation (STI) structure (68) that runs parallel to an orientation of the channel and the source/drain structure (epitaxial source/drain regions 92), FIG. 4, [0026], [0056].
Chang [0056] discloses portions of the nanostructures 55 acts as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions 92. Chang FIG. 4, [0026] discloses a liner may be formed along a surface of the substrate 50, fins 66, and nanostructures 55 and then a fill material may be formed over the liner; and Shallow trench isolation (STI) regions 68 are formed by depositing an insulation material over the substrate 50, fins 66, and nanostructure 55 and between adjacent fins 66. Thus, the STI structure 68 runs parallel to an orientation of the channel 55 and the source/drain structure 92.
Chang discloses that a device as taught including the shallow trench isolation structure provides isolation between adjacent fins [0013]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device to provide isolation between adjacent fins as disclosed by Chang [0013].
Regarding Claim 5 (Original), Huang discloses the semiconductor device of claim 1.
Huang does not disclose “wherein the gate conductor makes electrical contact with a signal line in the backside layer.”
Chang FIG. 31D, [0108] discloses the backside gate vias 164 couples the gate electrodes 102 to the signal lines 135S in the backside interconnect structure 140.
The combination of Huang and Chang discloses: wherein the gate conductor (Chang: gate electrodes 102) makes electrical contact with a signal line (Chang: 135S) in the backside layer (Huang: 345, FIG. 60B, [0065]).
Chang discloses that a device as taught routing the signal lines through the backside interconnect structure may reduce the total routing used in the front-side interconnect structure, which improves routing performance by decreasing routing density [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device such that one or more of the metal lines may be configured as a signal line in order to improve routing performance by decreasing routing density as disclosed by Chang [0011].
Regarding Claim 6 (Currently Amended), Huang discloses the semiconductor device of claim 1.
Huang does not disclose “a bottom dielectric isolation layer between the semiconductor structure and the channel.”
Chang discloses: further comprising a bottom dielectric isolation layer (100) between the semiconductor structure (66) and the channel (55), FIG. 18A, [0058].
Chang discloses that a device as taught includes improves electrical isolation between the semiconductor structure and the channel [0058]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device in order to improve electrical isolation of the device as disclosed by Chang [0058].
Regarding Claim 11 (Currently Amended), Huang discloses the semiconductor device of claim 9, further comprising:
a source/drain structure (150) in electrical contact with at least one of the first or second channel (channel region of first 112 or second 112), FIG. 60B, [0028], [0037].
Huang does not disclose “a bottom source/drain contact that makes electrical contact between the source/drain structure and a power line in the backside layer.”
Chang discloses: further comprising: a source/drain structure (92A) in electrical contact with the first channel 55 or the second channel 55 channel, FIG. 12C, [0056];
Chang FIG. 29A, [0084] discloses backside vias 130 may be electrically connected to the epitaxial source/drain regions 92 through the second silicide regions 129. Chang [0094] discloses the power regions 140P of the backside interconnect structure 140 may include routing from the transistor structures 109 and the backside vias 130 to the power rails 135P.
The combination of Huang and Chang discloses: a bottom source/drain contact (Chang: backside vias 130) that makes electrical contact between the source/drain structure (Chang: 92A) and a power line (Chang: power rails 135P) in the backside layer (Huang: 345, FIG. 60B, [0065]).
Chang discloses that a device as taught routing the power supply lines through the backside interconnect structure may reduce the total routing used in the front-side interconnect structure, which improves routing performance by decreasing routing density [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device such that one or more of the metal lines may be configured as a power line in order to improve routing performance by decreasing routing density as disclosed by Chang [0011].
Regarding Claim 12 (Currently Amended), The combination of Huang and Chang discloses the semiconductor device of claim 11.
Huang does not disclose “wherein the dielectric fill and the dielectric liner are part of a shallow trench isolation (STI) structure that runs parallel to an orientation of at least one of the first channel or the second channel and the source/drain structure.”
Chang discloses: wherein the dielectric fill and the dielectric liner are part of a shallow trench isolation (STI) structure (68) that runs parallel to an orientation of at least one of the first channel or the second channel and the source/drain structure (epitaxial source/drain regions 92), FIG. 4, [0026], [0056].
Chang [0056] discloses portions of the nanostructures 55 acts as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions 92. Chang FIG. 4, [0026] discloses a liner may be formed along a surface of the substrate 50, fins 66, and nanostructures 55 and then a fill material may be formed over the liner; and Shallow trench isolation (STI) regions 68 are formed by depositing an insulation material over the substrate 50, fins 66, and nanostructure 55 and between adjacent fins 66. Thus, the STI structure 68 runs parallel to an orientation of at least one of the first channel 55 or the second the channel 55 and the source/drain structure 92.
Chang discloses that a device as taught including the shallow trench isolation structure provides isolation between adjacent fins [0013]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device to provide isolation between adjacent fins as disclosed by Chang [0013].
Regarding Claim 13 (Original), Huang discloses the semiconductor device of claim 9.
Huang does not disclose “wherein the gate conductor makes electrical contact with a signal line in the backside layer.”
Chang FIG. 31D, [0108] discloses the backside gate vias 164 couples the gate electrodes 102 to the signal lines 135S in the backside interconnect structure 140.
The combination of Huang and Chang discloses: wherein the gate conductor (Chang: gate electrodes 102) makes electrical contact with a signal line (Chang: 135S) in the backside layer (Huang: 345, FIG. 60B, [0065]).
Chang discloses that a device as taught routing the signal lines through the backside interconnect structure may reduce the total routing used in the front-side interconnect structure, which improves routing performance by decreasing routing density [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device such that one or more of the metal lines may be configured as a signal line in order to improve routing performance by decreasing routing density as disclosed by Chang [0011].
Regarding Claim 14 (Currently Amended), Huang discloses the semiconductor device of claim 9.
Huang does not disclose “a bottom dielectric isolation layer between the semiconductor structure and at least one of the first channel or the second channel.”
Chang discloses: further comprising a bottom dielectric isolation layer (100) between the semiconductor structure (66) and at least one of the channel first channel or the second channel (first channel 55 or the second channel 55), FIG. 18A, [0058].
Chang discloses that a device as taught includes improves electrical isolation between the semiconductor structure and the channel [0058]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device in order to improve electrical isolation of the device as disclosed by Chang [0058].
Regarding Claim 22 (New), Huang discloses the semiconductor device of claim 21, further comprising:
a source/drain structure (150) in electrical contact with the channel (channel region of 112), FIG. 60B, [0037];
Huang does not disclose “a bottom source/drain contact that makes electrical contact between the source/drain structure and a power line in the backside layer.”
Chang discloses: further comprising: a source/drain structure (92A) in electrical contact with the channel (55), FIG. 12C, [0056];
Chang FIG. 29A, [0084] discloses backside vias 130 may be electrically connected to the epitaxial source/drain regions 92 through the second silicide regions 129. Chang [0094] discloses the power regions 140P of the backside interconnect structure 140 may include routing from the transistor structures 109 and the backside vias 130 to the power rails 135P.
The combination of Huang and Chang discloses: a bottom source/drain contact (Chang: backside vias 130) that makes electrical contact between the source/drain structure (Chang: 92A) and a power line (Chang: power rails 135P) in the backside layer (Huang: 345, FIG. 60B, [0065]).
Chang discloses that a device as taught routing the power supply lines through the backside interconnect structure may reduce the total routing used in the front-side interconnect structure, which improves routing performance by decreasing routing density [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device such that one or more of the metal lines may be configured as a power line in order to improve routing performance by decreasing routing density as disclosed by Chang [0011].
Regarding Claim 23 (New), The combination of Huang and Chang discloses the semiconductor device of claim 22.
Huang does not disclose “wherein the dielectric fill and the dielectric liner are part of a shallow trench isolation (STI) structure that runs parallel to an orientation of the channel and the source/drain structure.”
Chang discloses: wherein the dielectric fill and the dielectric liner are part of a shallow trench isolation (STI) structure (68) that runs parallel to an orientation of the channel and the source/drain structure (epitaxial source/drain regions 92), FIG. 4, [0026], [0056].
Chang [0056] discloses portions of the nanostructures 55 acts as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions 92. Chang FIG. 4, [0026] discloses a liner may be formed along a surface of the substrate 50, fins 66, and nanostructures 55 and then a fill material may be formed over the liner; and Shallow trench isolation (STI) regions 68 are formed by depositing an insulation material over the substrate 50, fins 66, and nanostructure 55 and between adjacent fins 66. Thus, the STI structure 68 runs parallel to an orientation of the channel 55 and the source/drain structure 92.
Chang discloses that a device as taught including the shallow trench isolation structure provides isolation between adjacent fins [0013]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device to provide isolation between adjacent fins as disclosed by Chang [0013].
Regarding Claim 24 (New), Huang discloses the semiconductor device of claim 21.
Huang does not disclose “wherein the gate conductor makes electrical contact with a signal line in the backside layer.”
Chang FIG. 31D, [0108] discloses the backside gate vias 164 couples the gate electrodes 102 to the signal lines 135S in the backside interconnect structure 140.
The combination of Huang and Chang discloses: wherein the gate conductor (Chang: gate electrodes 102) makes electrical contact with a signal line (Chang: 135S) in the backside layer (Huang: 345, FIG. 60B, [0065]).
Chang discloses that a device as taught routing the signal lines through the backside interconnect structure may reduce the total routing used in the front-side interconnect structure, which improves routing performance by decreasing routing density [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device such that one or more of the metal lines may be configured as a signal line in order to improve routing performance by decreasing routing density as disclosed by Chang [0011].
Regarding Claim 25 (New), Huang discloses the semiconductor device of claim 21.
Huang does not disclose “a bottom dielectric isolation layer between the semiconductor structure and at least one of the first channel or the second channel.”
Chang discloses: further comprising a bottom dielectric isolation layer (100) between the semiconductor structure (66) and the channel (55), FIG. 18A, [0058].
Chang discloses that a device as taught includes improves electrical isolation between the semiconductor structure and the channel [0058]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device in order to improve electrical isolation of the device as disclosed by Chang [0058].
Regarding Claim 29 (New), The combination of Huang and Chang discloses the semiconductor device of claim 13.
Huang does not disclose “wherein the backside layer further includes a power line laterally spaced from the signal line.”
Chang FIG. 29A, [0096] discloses the backside interconnect structure 140 may be separated into a plurality of signal regions 140S and power regions 140P and minimizes the lateral widths of the power regions 140P to provide more lateral space available for density and complexity in the routing through the signal regions 140S.
Thus, the power rails 135P and the signal lines 135S are laterally spaced from one another.
The combination of Huang and Chang discloses: wherein the backside layer (Huang: 345, FIG. 60B, [0065]) further includes a power line (Chang: 135P) laterally spaced from the signal line (Chang: 135S).
Chang discloses that a device as taught reduce the effects of parasitic capacitance [0096]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to improve device performance as disclosed by Chang [0096].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
