DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, and Claims 1-15 in
the reply filed on 02/02/2026 is acknowledged. Claims 16-20 are withdrawn from
further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected
invention, there being no allowable generic or linking claim. Election was made without
traverse in the reply filed on 02/02/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/14/2022 and 02/18/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4 recites “wherein the dielectric fill and the dielectric liner are part a shallow trench isolation (STI) structure”; this should be written as “wherein the dielectric fill and the dielectric liner are part of a shallow trench isolation (STI) structure”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 12, 14, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the channel" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the channel" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation "the channel" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 is rejected due to its dependency on claim 14.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US20210375761A1; hereinafter Chang), in view of Su et al. (US20220271138A1; hereinafter Su).
Regarding Claim 1, Chang discloses a semiconductor device (nano-FETs), comprising:
a channel (nanostructures 55) over a backside layer (substrate 50), FIG. 4 reproduced below, [0013];
a dielectric fill (Shallow trench regions 68) on the backside layer (substrate 50), including a first dielectric material (insulation material), FIG. 4, [0013], [0026].
Chang [0026] discloses the STI region 68 may be formed by depositing an insulation material such as an oxide, such as silicon oxide, a nitride, the like, or a combination thereof over the substrate 50.
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Chang: FIG. 4
Chang does not disclose “a gate conductor on the channel that makes electrical contact with the backside layer through the dielectric fill; and a dielectric liner on sidewalls of the dielectric fill, including a second dielectric material, in contact with the gate conductor at the dielectric fill.”
In a similar art, Su discloses a method of forming a semiconductor device with backside contact [0005].
Su discloses: a gate conductor (gate electrode layer 246 of the gate structure 240) on the channel (channel members 208) that makes electrical contact with the backside layer (first backside conductive feature 302) through the dielectric fill (backside dielectric layer 280), FIG. 15 reproduced below, [0030], [0031], [0033].
Su [0030] discloses the backside dielectric layer 280 is etched to form an opening 292. Su [0031] discloses a backside gate contact 294 is formed in the opening 292 and is coupled to and in direct contact with the gate electrode layer 246 of the gate structure 240. Su [0033] discloses the first backside conductive features 302 are electrically coupled to the first backside gate contact 294, thus the gate conductor 246 makes electrical contact with the backside conductive feature 302 through the dielectric fill 280.
a dielectric liner (278) on sidewalls of the dielectric fill (280), including a second dielectric material (278 may include silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride), in contact with the gate conductor (246) at the dielectric fill (280), FIG. 9, FIG. 15, [0027], [0031].
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Su: FIG. 15
Su discloses that a device as taught may reduce off-state leakage current into the substrate and improves device performance [0027]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to reduce off-state leakage current into the substrate and improve device performance as disclosed by Su [0027].
Regarding Claim 2, The combination of Chang and Su discloses the semiconductor device of claim 1.
Chang does not disclose “wherein the dielectric liner covers opposing sidewalls of a hole in the dielectric fill.”
Su discloses: wherein the dielectric liner (278) covers opposing sidewalls of a hole (gate access opening 276) in the dielectric fill (280), FIG. 15, [0027].
Su [0027] discloses the liner 278 is deposited along sidewalls and bottom surfaces of the gate access openings 276 and then the dielectric 280 is deposited over the liner 278 and into the gate access opening 276, thus the liner 278 covers the opposing sidewalls of the hole 276 in the dielectric fill 280.
Su discloses that a device as taught may reduce off-state leakage current into the substrate and improves device performance [0027]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to reduce off-state leakage current into the substrate and improve device performance as disclosed by Su [0027].
Regarding Claim 3, The combination of Chang and Su discloses the semiconductor device of claim 1.
Chang discloses: further comprising: a source/drain structure (92A) in electrical contact with the channel (55), FIG. 4, [0056]; and
a bottom source/drain contact (130) that makes electrical contact between the source/drain structure (92A) and a power line (135P) in the backside layer (backside interconnect structure 140 formed on the backside of the transistor structures formed in substrate 50), FIG. 29A, [0085], [0095].
Chang does not explicitly disclose “a power line in the backside layer.”
Su discloses: further comprising: a source/drain structure (source/drain feature 230) in electrical contact with the channel (208), FIG. 2, [0016]; and
a bottom source/drain contact (backside source/drain contact 274) that makes electrical contact between the source/drain structure (230) and a power line in the backside layer (backside conductive feature 302), FIG. 7, FIG. 15, [0026], [0033].
Su [0033] discloses the first backside conductive features 302 are electrically coupled to the first backside gate contact 294-1 and the first backside source/drain contact 274-1, thereby interconnecting them. It would be obvious to one of ordinary skill in the art to implement a power line to the backside conductive feature 302 to electrically connect to the source/drain structure 230.
Su discloses that a device as taught with backside conductive features would enable backside power routing of the device. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to enable backside power routing of the device as disclosed by Su.
Regarding Claim 4, The combination of Chang and Su discloses the semiconductor device of claim 3.
Chang discloses: wherein the dielectric fill and the dielectric liner are part a shallow trench isolation (STI) structure (68) that runs parallel to an orientation of the channel and the source/drain structure (portions of the nanostructures 55 acts as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions 92, [0056]), FIG. 4, [0026].
Chang [0026] discloses a liner may be formed along a surface of the substrate 50, fins 66, and nanostructures 55 and then a fill material may be formed over the liner; and Shallow trench isolation (STI) regions 68 are formed by depositing an insulation material over the substrate 50, fins 66, and nanostructure 55 and between adjacent fins 66, thus the STI structure 68 runs parallel to an orientation of the channel 55 and the source/drain structure 92.
Regarding Claim 5, The combination of Chang and Su discloses the semiconductor device of claim 1.
Chang discloses: wherein the gate conductor (102) makes electrical contact with a signal line (135S) in the backside layer (backside interconnect structure 140 formed on the backside of the transistor structures formed in substrate 50), FIG. 31D, [108].
Chang [0108] discloses the backside gate vias 164 couples the gate electrodes 102 to the signal lines 135S in the backside interconnect structure 140.
Chang does not explicitly disclose “a signal line in the backside layer.”
Su discloses: wherein the gate conductor (246) makes electrical contact with a signal line in the backside layer (backside conductive features 302), FIG. 7, FIG. 15, [0031], [0033].
Su [0033] discloses the first backside conductive features 302 are electrically coupled to the first backside gate contact 294-1 and the first backside source/drain contact 274-1, thereby interconnecting them. It would be obvious to one of ordinary skill in the art to implement a signal line to the backside conductive feature 302 to electrically connect to the gate conductor 246.
Su discloses that a device as taught with backside conductive features would enable backside signal routing of the device. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to enable backside signal routing of the device as disclosed by Su.
Regarding Claim 6, The combination of Chang and Su discloses the semiconductor device of claim 1.
Chang discloses: further comprising: a semiconductor structure (66) between the channel (55) and the backside layer (50), FIG. 4, [0023]; and
a bottom dielectric isolation layer (100) between the semiconductor structure (66) and the channel (55), FIG. 18A, [0058].
Regarding Claim 7, The combination of Chang and Su discloses the semiconductor device of claim 6.
Chang discloses: wherein the dielectric liner (liner of STI 68) is formed on a sidewall of the semiconductor structure (fins 66), FIG. 4, [0026].
Chang [0026] discloses a liner may be formed along a surface of the substrate 50, fins 66, and nanostructures 55 and then a fill material may be formed over the liner; thus, the liner is formed on a sidewall of the semiconductor structure (fins 66).
Regarding Claim 8, The combination of Chang and Su discloses the semiconductor device of claim 1.
Chang discloses: wherein the first dielectric material is silicon dioxide (STI region 68 is formed of insulation material which may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof), [0026].
Chang does not explicitly disclose “and the second dielectric material is silicon nitride.”
Su discloses: wherein the first dielectric material is silicon dioxide (dielectric plug 280 includes silicon oxide) and the second dielectric material is silicon nitride (liner 274 includes silicon nitride), [0036].
Su discloses that a device as taught may reduce off-state leakage current into the substrate and improves device performance [0027]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to reduce off-state leakage current into the substrate and improve device performance as disclosed by Su [0027].
Regarding Claim 9, Chang discloses a semiconductor device (nano-FETs), comprising:
a first channel (nanostructures 55) over a backside layer (substrate 50) in a first device region (p-type region 50P), FIG. 4, [0013], [0019];
a second channel (nanostructures 55) over the backside layer (substrate 50) in a second device region (n-type region 50N), FIG. 4, [0013], [0019];
a dielectric fill that includes a first dielectric layer (STI region 68), on the backside layer (50) between the first device region (50P) and the second device region (50N), FIG. 4, [0026].
Chang [0026] discloses the STI regions 68 may be formed by depositing an insulation material over the substrate 50, the fins 66, and nanostructures 55, and between adjacent fins 66, thus the dielectric fill 68 is formed on the backside layer 50 between device regions 50P and 50N.
Chang does not disclose “a gate conductor on the first channel and the second channel that makes electrical contact with the backside layer through the dielectric fill; and a dielectric liner on sidewalls of the dielectric fill, including a second dielectric material, in contact with the gate conductor at the dielectric fill.”
In a similar art, Su discloses a method of forming a semiconductor device [0027].
Su discloses: a gate conductor (gate electrode layer 246 of the gate structure 240) on the first channel and the second channel (first and second vertically stacked channel members 208, [0015]) that makes electrical contact with the backside layer (first conductive feature 302) through the dielectric fill (backside dielectric layer 280), FIG. 15, [0030], [0031], [0033].
Su [0030] discloses the backside dielectric layer 280 is etched to form an opening 292. Su [0031] discloses a backside gate contact 294 is formed in the opening 292 and is coupled to and in direct contact with the gate electrode layer 246 of the gate structure 240. Su [0033] discloses the first backside conductive feature 302 are electrically coupled to the first backside gate contact 294-1, thus the gate conductor 246 makes electrical contact with the backside conductive feature 302 through the dielectric fill 280.
a dielectric liner (liner 278) on sidewalls of the dielectric fill (280), including a second dielectric material (278 may include silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride), in contact with the gate conductor (246) at the dielectric fill (280), FIG. 9, FIG. 15, [0027], [0031].
Su discloses that a device as taught may reduce off-state leakage current into the substrate and improves device performance [0027]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to reduce off-state leakage current into the substrate and improve device performance as disclosed by Su [0027].
Regarding Claim 10, The combination of Chang and Su discloses the semiconductor device of claim 9.
Chang does not disclose “wherein the dielectric liner covers opposing sidewalls of a hole in the dielectric fill.”
Su discloses: wherein the dielectric liner (278) covers opposing sidewalls of a hole (gate access opening 276) in the dielectric fill (280), FIG. 15, [0027].
Su [0027] discloses the liner 278 is deposited along sidewalls and bottom surfaces of the gate access openings 276 and then the dielectric 280 is deposited over the liner 278 and into the gate access opening 276, thus the liner 278 covers the opposing sidewalls of the hole 276 in the dielectric fill 280.
Su discloses that a device as taught may reduce off-state leakage current into the substrate and improves device performance [0027]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to reduce off-state leakage current into the substrate and improve device performance as disclosed by Su [0027].
Regarding Claim 11, The combination of Chang and Su discloses the semiconductor device of claim 9.
Chang discloses: further comprising: a source/drain structure (92A) in electrical contact with the channel (55), FIG. 4, [0056]; and
a bottom source/drain contact (130) that makes electrical contact between the source/drain structure (92A) and a power line (135P) in the backside layer (backside interconnect structure 140 formed on the backside of the transistor structures formed in substrate 50), FIG. 29A, [0085], [0095].
Chang does not explicitly disclose “a power line in the backside layer.”
Su discloses: further comprising: a source/drain structure (source/drain feature 230) in electrical contact with the channel (208), FIG. 2, [0016]; and
a bottom source/drain contact (backside source/drain contact 274) that makes electrical contact between the source/drain structure (230) and a power line in the backside layer (backside conductive feature 302), FIG. 7, FIG. 15, [0026], [0033].
Su [0033] discloses the first backside conductive features 302 are electrically coupled to the first backside gate contact 294-1 and the first backside source/drain contact 274-1, thereby interconnecting them. It would be obvious to one of ordinary skill in the art to implement a power line to the backside conductive feature 302 to electrically connect to the source/drain structure 230.
Su discloses that a device as taught with backside conductive features would enable backside power routing of the device. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to enable backside power routing of the device as disclosed by Su.
Regarding Claim 12, The combination of Chang and Su discloses the semiconductor device of claim 11.
Chang discloses: wherein the dielectric fill and the dielectric liner are part a shallow trench isolation (STI) structure (68) that runs parallel to an orientation of the channel and the source/drain structure (portions of the nanostructures 55 acts as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions 92, [0056]), FIG. 4, [0026].
Chang [0026] discloses a liner may be formed along a surface of the substrate 50, fins 66, and nanostructures 55 and then a fill material may be formed over the liner; and Shallow trench isolation (STI) regions 68 are formed by depositing an insulation material over the substrate 50, fins 66, and nanostructure 55 and between adjacent fins 66, thus the STI structure 68 runs parallel to an orientation of the channel 55 and the source/drain structure 92.
Regarding Claim 13, The combination of Chang and Su discloses the semiconductor device of claim 9.
Chang discloses: wherein the gate conductor (102) makes electrical contact with a signal line (135S) in the backside layer (backside interconnect structure 140 formed on the backside of the transistor structures formed in substrate 50), FIG. 31D, [108].
Chang [0108] discloses the backside gate vias 164 couples the gate electrodes 102 to the signal lines 135S in the backside interconnect structure 140.
Chang does not explicitly disclose “a signal line in the backside layer.”
Su discloses: wherein the gate conductor (246) makes electrical contact with a signal line in the backside layer (backside conductive features 302), FIG. 7, FIG. 15, [0031], [0033].
Su [0033] discloses the first backside conductive features 302 are electrically coupled to the first backside gate contact 294-1 and the first backside source/drain contact 274-1, thereby interconnecting them. It would be obvious to one of ordinary skill in the art to implement a signal line to the backside conductive feature 302 to electrically connect to the gate conductor 246.
Su discloses that a device as taught with backside conductive features would enable backside signal routing of the device. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s device in order to enable backside signal routing of the device as disclosed by Su.
Regarding Claim 14, The combination of Chang and Su discloses the semiconductor device of claim 9.
Chang discloses: further comprising: a semiconductor structure (66) between the channel (54) and the backside layer (50), FIG. 4, [0023]; and
a bottom dielectric isolation layer (100) between the semiconductor structure (66) and the channel (54), FIG. 18A, [0058].
Regarding Claim 15, The combination of Chang and Su discloses the semiconductor device of claim 14.
Chang discloses: wherein the dielectric liner (liner of STI 68) is formed on a sidewall of the semiconductor structure (fins 66), FIG. 4, [0026].
Chang [0026] discloses a liner may be formed along a surface of the substrate 50, fins 66, and nanostructures 55 and then a fill material may be formed over the liner; thus, the liner is formed on a sidewall of the semiconductor structure (fins 66).
Conclusion
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899