DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/19/2026 has been entered.
Claims 1-7 are pending. Claim 1 has been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-7 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayakawa et al. US 2013/0043501 A1 (Kobayakawa’501) in view of Miyazaki et al. US 2021/0043818 A1 (Miyazaki).
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In re claim 1, Kobayakawa’501 discloses (e.g. FIGs. 3-4) a semiconductor apparatus A2 comprising:
a substrate including a base (portion of support 4 below leads 1,2), a first conductor pattern 1, and a second conductor pattern 2, wherein
the base includes a first main (top) surface, and
the first conductor pattern 1 and the second conductor pattern 2 are arranged on the first main (top) surface;
a semiconductor chip 3;
a connection material (non-conductive resin, not shown, ¶ 47);
a bonding wire 61,62;
a first partition 42b; and
a second partition 42a, wherein
the semiconductor chip 3 is arranged on the substrate through the connection material (¶ 47),
the bonding wire 62 includes a first end (ends connected to electrodes 31) and a second end (end connected to 13),
the bonding wire is connected to the semiconductor chip 3 at the first end (at 31) and connected to the substrate at the second end (at 13),
the first partition 42b is arranged on the substrate, at a position between the semiconductor chip 3 and the second end (at 13) in plan view, and
the second partition 42a (corresponding to the portion annotated in drawing above) is disposed on a portion of the first main (top) surface between the first conductor pattern 1 and the second conductor pattern 2, such that the second partition 42a does not cover a surface of the first conductor pattern (e.g. a surface of lead 1 exposed by 42a) or a surface of the second conductor pattern (e.g. a surface of lead 2 exposed by 42a).
The recitation to “a surface of the first/second conductor pattern” does not require distinguish over surface of the leads 1,2 exposed by the second partition 42a. As such, the second partition 42a does not cover the surface (exposed surface) of the first/second conductor pattern.
Furthermore, Miyazaki discloses (e.g. FIG. 9) a semiconductor apparatus comprising a semiconductor chip 51 arranged on the first conductor pattern 10 with a connection material 551 and connected to second conductor pattern 40 by a bonding wire 61 at wire bonding portion 45, a partition 78 disposed between conductor patterns 10,40 and does not cover an entire upper surface 101 of the first conductor pattern 10 or an entire upper surface 401 of the second conductor pattern 40 (¶ 100). Miyazaki discloses the partition protrudes from the upper surfaces 101,401 of the conductor pattern 10,40 so as to prevent the connection material 551 from following into second conductor pattern 40 to cause connection failure of the bonding wire 61 at the wire bonding portion 45 (¶ 132,140).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Kobayakawa’501’s second partition 42a to protrude from upper surfaces of the conductor patterns 1,2 without covering any part of the upper surfaces as taught by Miyazaki.
In re claim 2, Kobayakawa’501 discloses (e.g. FIG. 3-4) further comprising:
a reflector (upper portion of support 4 having reflective surface 41) arranged on the substrate, wherein
the semiconductor chip 3 is a light emitting element (¶ 43), and
the first partition 42b contains a same material as the reflector (upper portion of the support having the reflective surface 41 and partition portion 42 are all parts of the support member 4).
In re claim 3, Kobayakawa’501 discloses (e.g. FIGs. 3-4) wherein
the base (portion of support 4 below leads 1,2) further includes a second main (bottom) surface, and
the first conductor pattern 1 and the second conductor pattern 2 are spaced apart and lined up along a longitudinal direction of the substrate in the plan view (see FIG. 3).
In re claim 4, Kobayakawa’501 discloses (e.g. FIGs. 3-4) wherein
the semiconductor chip 3 is arranged on the first conductor pattern 1 (at the portion 12) through the connection material (¶ 47), and
the bonding wire 62 is connected to the first conductor pattern 1 at the second end (at 13).
In re claim 6, Kobayakawa’501 discloses (e.g. FIG. 4) wherein an upper end of the first partition 42b is closer to the substrate than an upper surface of the semiconductor chip 3 (¶ 36).
In re claim 7, Kobayakawa’501 discloses (e.g. FIGs. 3-4) wherein the connection material is a die bonding paste containing a resin material (non-conductive resin, not shown, ¶ 47).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayakawa’501 in view of Miyazaki as applied to claim 3 above, and further in view of Kobayakawa et al. US 2016/0284678 A1 (Kobayakawa’678).
In re claim 5, Kobayakawa’501 discloses the claimed invention including (e.g. FIG. 4) conductor patterns 12,13,14,15,22 on the first main (top) surface of the substrate and further includes a third conductor pattern 11 and a fourth conductor pattern 21 that are arranged on the second main (bottom) surface.
Kobayakawa’501 teaches the conductor patterns 11,21 on the bottom surface connect to an external circuit (¶ 30,32).
Kobayakawa’501 does not explicitly disclose a resist arranged on the second main surface, and the resist is arranged between the third conductor pattern and the fourth conductor pattern in the longitudinal direction.
However, Kobayakawa’678 teaches (e.g. FIG. 5) an LED package comprising conductor patterns 211 on the top surface 11 of a substrate 1 and conductor patterns 212 on the bottom surface 12 of the substrate 1. Kobayakawa’678 further teaches a resist 14 (¶ 55) arranged on the bottom surface 12, and the resist 14 is arranged between the bottom conductor patterns 212 in the longitudinal direction. The resist 14 is provided to prevent short-circuit when the LED package is solder bonded to external module (¶ 55).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a resist between Kobayakawa’501’s conductor patterns 11,21 on the bottom surface of the support so as to prevent short circuit when the LED package A2 is solder bonded to the external circuit as taught by Kobayakawa’678.
Response to Arguments
Applicant's arguments filed 1/19/2026 have been fully considered but they are not persuasive.
Regarding Kobayakawa’501, Applicant argues the protective portion 42 having inclined portions 42a covering the ends of the upper surface of the leads 1 and 2, leaving exposed only the upper surfaces of the wire bonding portions 13,22 and chip mounting portion 12, and thus fails to teach the “second partition does not cover a surface of the first conductor pattern and a surface of the second conductor pattern” (Remark, pages 6-7).
This is not persuasive. The recitation to “a surface of the first/second conductor pattern” does not require distinguish over surface of the leads 1,2 exposed by the second partition 42a. As such, the second partition 42a does not cover the surface, i.e. exposed surface, of the first/second conductor pattern 1,2. Alternatively, the first and second conductor patterns may correspond only to portions 12/13 and 22 of the leads 1,2 which are exposed by protective portion 42.
Furthermore, Miyazaki discloses (e.g. FIG. 9) a semiconductor apparatus comprising a semiconductor chip 51 arranged on the first conductor pattern 10 with a connection material 551 and connected to second conductor pattern 40 by a bonding wire 61 at wire bonding portion 45, a partition 78 disposed between conductor patterns 10,40 and does not cover an entire upper surface 101 of the first conductor pattern 10 or an entire upper surface 401 of the second conductor pattern 40 (¶ 100). Miyazaki discloses the partition protrudes from the upper surfaces 101,401 of the conductor pattern 10,40 so as to prevent the connection material 551 from following into second conductor pattern 40 to cause connection failure of the bonding wire 61 at the wire bonding portion 45 (¶ 132,140).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Kobayakawa’501’s second partition 42a to protrude from upper surfaces of the conductor patterns 1,2 without covering any part of the upper surfaces as taught by Miyazaki.
Conclusion
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights