DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Continued Examination Under 37 CFR 1.114 3
III. Claim Rejections - 35 USC § 103 3
A. Claims 1-3, 7, 10, 15, 26, 27, and 46-48 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0178568 (“Cheng”) in view of US 2016/0334362 (“Liu”). 3
B. Claims 39 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Liu, as applied to claim 1 above, and further in view of US 2015/0093816 (“Lagae”). 10
IV. Allowable Subject Matter 11
V. Response to Arguments 16
Conclusion 16
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 12/02/2025 has been entered.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-3, 7, 10, 15, 26, 27, and 46-48 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0178568 (“Cheng”) in view of US 2016/0334362 (“Liu”).
Claim 1 reads,
1. (Currently Amended) An integrated circuit, comprising:
[1a] a semiconductor die including
[1b] a semiconductor substrate,
[1c] a dielectric layer on the semiconductor substrate, and
[1d] a metallization structure encapsulated in the dielectric layer,
[2a] in which the semiconductor substrate includes sensor circuitry,
[2b] the sensor circuitry includes a transistor having a first current terminal, a second current terminal, and a channel region between the first and second current terminals, and
[2c] the dielectric layer has a sensing side facing away from the semiconductor substrate;
[3] an insulation layer on the sensing side;
[4] a sensor terminal on the sensing side and over the channel region;
[5a] a restriction structure including an opening and a rigid silicon-based fluidic structure,
[5b] in which the fluidic structure is on the sensing side and encapsulates a fluid cavity on the sensing side,
[5c] the sensor terminal is in the fluid cavity, and
[5d] the restriction structure is configured to allow a fluid to enter the fluid cavity and reach the sensor terminal through the opening; and
[6] a voltage terminal on the sensing side of the dielectric layer and configurable to contact the fluid directly to apply a voltage signal to the fluid.
With regard to claim 1, Cheng discloses, generally in Figs. 2A-3B,
1. (Currently Amended) An integrated circuit, comprising:
[1a] a semiconductor die 102 including
[1b] a semiconductor substrate 102 [¶ 15],
[1c] a dielectric layer 204 [¶ 21] on the semiconductor substrate 102, and
[1d] a metallization structure C0/M1/V1/M2/V2/M3 [¶ 21] encapsulated in the dielectric layer 204,
[2a] in which the semiconductor substrate 102 includes sensor circuitry 202, 203,
[2b] the sensor circuitry includes a transistor 203 having a first current terminal 202a, a second current terminal 202b, and a channel region 202c between the first and second current terminals [¶ 20], and
[2c] the dielectric layer 202 has a sensing side [side where M3 is positioned] facing away from the semiconductor substrate 102;
[3] an insulation layer [“second ILD 206” (¶ 22) and/or “sensing enhancement layer 212 comprising a high-k dielectric material” (¶ 23)] on the sensing side;
[4] a sensor terminal M3/V3/M4 on the sensing side and over the channel region 202c [¶ 21]; and
[5a] a restriction structure 218/220 including an opening [where “sample 234” enters “micro-fluidic channel 218a” (¶ 30; Fig. 2B)] and a rigid silicon-based fluidic structure 218/220 [¶ 25: “For example, in some embodiments, the first capping structure 218 may comprise PDMS (polydimethylsiloxane), while the second capping structure 220 may comprise quartz. In other embodiments, the first and/or second capping structures, 218 and 220, may comprise quartz and/or silicon.”],
[5b] in which the fluidic structure 218/220 is on the sensing side and encapsulates a fluid cavity 218a on the sensing side,
[5c] the sensor terminal M3/V3/M4 is in the fluid cavity 218a, and
[5d] the restriction structure 218/220 is configured to allow a fluid 234 [“sample (e.g. liquid)” (¶ 16); ¶¶ 28, 30] to enter the fluid cavity 218a and reach the sensor terminal M3/V3/M4 through the opening; and
[6] a voltage terminal 208a, 208b on the sensing side of the dielectric layer 204 and configurable to apply a voltage signal to the fluid 234 [¶¶ 27, 64].
With regard to feature [5d] of claim 1, diffusion, by definition, is the movement of a component in a region of higher concentration to a region of lower concentration. As such, the movement of the sample 234 from its source, i.e. high concentration, to a region where there is no sample 234, i.e. in the fluid fluidic channel 218a and the sensing well 214 having zero concentration of sample 234, is by definition, diffusion of the fluid. As such, it is held, absent evidence to the contrary that the restriction structure 218/220 is capable of “allow[ing] a fluid to enter the fluid cavity 218a and reach the sensor terminal M3/V3/M4 through the opening by microfluidic diffusion” as required by feature [5a]. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to feature [6] of claim 1, Cheng states,
[0027] In some embodiments, the upper metal wire layer M4 may comprise one or more EWOD (electrowetting on dielectrics) electrodes, 208a and 208b. In some embodiments, a hydrophobic layer 216 is disposed over the sensing enhancement layer 212 at a position overlying the EWOD electrodes, 208a and 208b. In some embodiments, the hydrophobic layer 216 may comprise a self assembled monolayer (SAM) or a teflon material. The EWOD electrodes, 208a and 208b, are configured to selectively generate electric fields that are configured to modify wetting properties of the hydrophobic layer 216 to control the flow of liquid within the micro-fluidic channel 218a. For example, the EWOD electrodes, 208a and 208b, may be configured to manipulate liquid drops in a manner that fills the sensing well 214. In other embodiments, the integrated chip 200 may comprise alternative droplet manipulation elements, such as light-generation elements that enable droplet manipulation by optical tweezers or electrodes that generate non-uniform electric fields to enable droplet manipulation by dielecrophoresis.
(Cheng: ¶ 27; emphasis added)
The voltage signal applied to the fluid 234 by the EWOD electrodes 208a, 208b, is indirect and therefore not in direct contact with the fluid. However, Cheng states that “alternative droplet manipulation elements, such as … electrodes that generate non-uniform electric fields to enable droplet manipulation …” (id.).
Liu, like Cheng, teaches a biosensor including electrodes 137A, 137B for manipulating the analyte fluid (Liu: title, abstract, ¶¶ 36-42). Liu states, “Manipulation electrodes 137 are operative to manipulate analytes in adjacent fluid or set the adjacent fluid to a reference potential.” (Liu: ¶ 36). Liu further teaches that the “manipulation electrodes 137” can be covered by a dielectric passivation layer 135, i.e. manipulation electrodes 137A in Fig. 1A (Liu: ¶¶ 36-39), or can be in direct contact with the analyte fluid, i.e. manipulation electrodes 137B in Fig. 1B (Liu: ¶¶ 39-40). In each instance, Liu indicates that the manipulation electrodes 137 are configured and used to apply a voltage signal to the analyte fluid (Liu: ¶¶ 36-39, 41, 42).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include electrodes—in direct contact with the analyte fluid—in Cheng, as taught in Liu, because Cheng explicitly states that manipulation electrodes can be used (Cheng: ¶ 27, supra) and because Liu proves that it is a matter of design choice that said manipulation electrodes covered by a passivation layer 135 (i.e. 137A in Fig. 1A) or not covered by a passivation layer and consequently directly exposed to the analyte fluid (i.e. 137B in Fig. 1B).
This is all of the features of claim 1.
With regard to claim 2,
2. (Previously Presented) The integrated circuit of claim 1, wherein:
[1] the sensor terminal is a first sensor terminal;
[2] the transistor is a first transistor;
[3] the channel region is a first channel region;
[4a] the semiconductor die further includes
[4b] a second transistor having a second channel region and a second sensor terminal on the sensing side over the second channel region; and
[5a] the second sensor terminal is either
[5b] external to the restriction structure, or
[5c] in the fluid cavity and between the opening and the first sensor terminal.
Cheng further discloses, generally in Figs. 3A-3B and paragraphs [0031]-[0033], an array of sensing wells 214a, 214b, etc., and therefore the first and second sensor terminals and their respective transistors, as shown in Fig. 2A.
With regard to claims 3 and 7, Cheng further discloses,
3. (Previously Presented) The integrated circuit of claim 2, wherein
[1] the fluid cavity 218a is a first fluid cavity, and
[2] the restriction structure 218/220 includes a second fluid cavity coupled between the opening and the first fluid cavity.
7. (Original) The integrated circuit of claim 3, wherein the second fluid cavity is on the sensing side, the fluidic structure 218/220 includes a connection structure on the sensing side, and the connection structure is coupled between the first and second fluid cavities [see annotated Fig. 3, above].
Fig. 3B of Cheng, reproduced below, shows the features of claims 3 and 7.
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(Annotated Fig. 3B of Cheng)
With regard to claim 10, Cheng further discloses,
10. (Original) The integrated circuit of claim 2, wherein the fluid cavity 218a includes a valve 222a [¶¶ 26, 32; Fig. 3A].
With regard to claim 15, Cheng further discloses,
15. (Original) The integrated circuit of claim 1, wherein the opening is a first opening [where sample 308a enters micro-fluidic channel 218a in Fig. 3B] through the fluidic structure, and the fluidic structure includes a second opening [where sample 308b enters micro-fluidic channel 218b in Fig. 3B].
With regard to claims 26 and 27, Cheng further discloses,
26. (Previously Presented) The integrated circuit of claim 1, wherein:
[1] the fluid cavity 218a includes a nanofluidic channel 218a [as shown in Figs. 3A-3B;
[2] the semiconductor die 102 further includes a second transistor having a second channel region and a second sensor terminal on the sensing side over the second channel region [as shown in Figs. 3A-3B and as explained under claim 3]; and
[3] the second sensor terminal is in the nanofluidic channel 218a.
27. (Previously Presented) The integrated circuit of claim 1, wherein:
[1] the fluid cavity 218a includes a nanofluidic channel 218a [as shown in Figs. 3A-3B;
[2] the semiconductor die 102 further includes a third transistor having a third channel region and a third sensor terminal on the sensing side over the third channel region [as shown in Figs. 3A-3B and as explained under claim 3]; and
[3] the third sensor terminal is in the nanofluidic channel 218a.
With regard to claims 46-48, Cheng further discloses,
46. (Original) The integrated circuit of claim 1, wherein the fluidic structure 218/220 includes at least one of Silicon Oxide, Silicon Nitride, SU-8, Polyimide, Parylene, Aluminum Oxide, Tantalum Pentoxide, Hafnium Oxide, Zirconium Dioxide, Yttrium Oxide, Zinc Oxide, Tin Oxide, Manganese Dioxide, or Gallium Oxide [supra].
47. (Previously Presented) The integrated circuit of claim 1, wherein the insulation layer 206 [¶ 21] and/or 212 [¶ 23] includes at least one of silicon oxide, silicon nitride, aluminum oxide, tantalum pentoxide, hafnium oxide, zirconium dioxide, yttrium oxide, zinc oxide, tin oxide, manganese dioxide, or gallium oxide.
48. (Original) The integrated circuit of claim 1, wherein the transistor 202 includes an open gate ion-sensitive field effect transistor (ISFET) or an extended gate C0/M1/V1/M2/V2/M3 ISFET [as shown in Fig. 2A].
B. Claims 39 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Liu, as applied to claim 1 above, and further in view of US 2015/0093816 (“Lagae”).
Claims 39 and 40 read,
39. (Original) The integrated circuit of claim 1, further comprising a particle filter in the fluid cavity between the opening and the sensor terminal.
40. (Original) The integrated circuit of claim 39, wherein the particle filter includes a restricted portion of the fluid cavity.
The prior art of Cheng in view of Liu, as explained above, teaches each of the features of claim 1.
Cheng does not disclose a particulate filter in the fluid cavity 218a.
Lagae, like Cheng, teaches a fluid analysis device for biological materials (Lagae: ¶¶ 2, 78) including a CMOS substrate 103 including sensors electrode 114 and a microfluidic substrate 101 including fluid channels that may be fabricated from silicon (Lagae: Figs. 18, 22; ¶¶ 72, 76 99, 108). Lagae further teaches that the fluid channels of the microfluidic substrate 101 include a particulate filter:
[0077] FIG. 27 illustrates a top view of a part of an open micro-fluidic component 102 comprising micro-pillars 270 to allow filtering and separation, valving, and mixing of a fluid sample during capillary flow. FIG. 28 illustrates a 3D view of the open micro-fluidic component 102 of FIG. 27 comprising micro-pillars 270. The micro-pillars 270 in FIG. 27 and FIG. 28 are positioned as to form a gradient. This gradient may be advantageous to filter out larger particles in a first part of the micro-fluidic component 102 and to filter out smaller particles in a second part of the micro-fluidic component 102.
(Lagae: ¶ 77; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the micro-pillars 270 that serve as a particulate filter in the fluid channels in Cheng in order to filter particles. As such Lagae may be seen as an improvement to Cheng in this aspect. (See MPEP 2143.)
This is all of the features of claims 39 and 40.
IV. Allowable Subject Matter
Claims 28-38 and 41-45 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 4-6, 8, and 9 read,
4. (Currently Amended) The integrated circuit of claim 3,
[1a] wherein the second fluid cavity is in the semiconductor substrate, and
[1b] the opening is a first opening through the insulation layer and the dielectric layer and external to the fluidic structure; and
[2] the integrated circuit further comprises a second opening through the semiconductor substrate and coupled between the first and second fluid cavities.
5. (Original) The integrated circuit of claim 4, wherein the insulation layer is a first insulation layer, the semiconductor substrate includes a second insulation layer including silicon dioxide, and the second fluid cavity is in the second insulation layer.
6. (Original) The integrated circuit of claim 3, further comprising a wafer on a back side of the semiconductor die opposite to the sensing side, wherein the wafer encloses the second fluid cavity.
8. (Original) The integrated circuit of claim 3, further comprising a buffer fluid in the first and second fluid cavities.
9. (Original) The integrate circuit of claim 3, further comprising a water-soluble solid in at least one of the first or second fluid cavities.
The prior art does not reasonably teach or suggest—in the context of each of claims 4-6, 8, and 9—the specific combination of limitations.
Claims 11-14, 16, and 17 read,
11. (Original) The integrated circuit of claim 10, wherein the valve is constructed as a bubble chamber, the bubble chamber having recessed internal surfaces configured to trap a bubble.
12. (Original) The integrated circuit of claim 10, wherein the valve is directly below the opening and the second sensor terminal, or between the first and second sensor terminals.
13. (Original) The integrated circuit of claim 11, wherein the valve includes a set of control terminals configured to block or unblock transportation of the fluid from the opening to at least one of the first or second sensor terminals.
14. (Currently Amended) The integrated circuit of claim 10, comprising:
[1] a first control terminal partially covered by the insulation layer and in the fluid cavity;
[2] a second control terminal partially covered by the insulation layer and being external to the fluid cavity;
[3] a first voltage source coupled to the first control terminal; and
[4] a second voltage source coupled to the second control terminal,
[5] wherein the first control terminal or the second control terminal is the voltage terminal; and
[6] wherein the first and second voltage sources are configured to set a DC potential difference between the first and second control terminals to generate a gas bubble in the fluid cavity by the first control terminal.
16. (Original) The integrated circuit of claim 15, wherein the fluid cavity includes a set of bubble chambers each having recessed internal surfaces configured to trap a bubble; wherein the integrated circuit further includes a heater circuit in the dielectric layer below each respective bubble chamber; and wherein the heater circuits and the set of bubble chambers provide a pump to transport the fluid in the fluid cavity by convection.
17. (Original) The integrated circuit of claim 16, further comprising a Tesla valve at one end of the set of bubble chambers, and the Tesla valve is part of the pump.
The prior art does not reasonably teach or suggest—in the context of each of claims 11-14, 16, and 17—the specific combination of limitations.
Claim 18 reads,
18. The integrated circuit of claim 15, further comprising
[1] a first voltage terminal and a second voltage terminal on the sensing side,
[2] a first voltage source coupled to the first voltage terminal via the metallization structure, and
[3] a second voltage source coupled to the second voltage terminal via the metallization structure; and
[4] wherein each of the first and second voltage terminals include a respective metal surface at least partially covered by the insulation layer.
As such, the prior art does not reasonably teach or suggest—in the context of claim 18—the limitations recited therein. Claims 19-21, 23, and 24 would be allowable at least for including the same allowable feature by depending from claim 18.
Claim 22 reads,
22. The integrated circuit of claim 15, further comprising:
[1] multiple sets of control terminals in the fluid cavity; and
[2] a set of AC voltage sources, each AC voltage source coupled to a respective control terminal within each set of the multiple sets of control terminals,
[3] wherein the set of AC voltage sources are configured to provide AC voltage signals having different phases.
The prior art does not reasonably teach or suggest—in the context of claim 22—the specific combination of elements.
Claim 25 reads,
25. (Currently Amended) The integrated circuit of claim 2, wherein the second sensor terminal
[1] is less than 250 micrometers (μm) from the opening if in the fluid cavity and
[2] is less than 0.5 mm from the opening if external to the fluid cavity, and
[3] the first sensor terminal is more than 1 mm from the opening.
The prior art does not reasonably teach or suggest—in the context of claim 25—the specific combination of elements.
Claim 28 reads,
28. The integrated circuit of claim 1, wherein:
[1] the fluid cavity is a first fluid cavity,
[2] the sensor terminal is a first sensor terminal,
[3] the transistor is a first transistor,
[4] the channel region is a first channel region; and
[5] the fluidic structure encapsulates a second fluid cavity and a connection structure coupled between the first and second fluid cavities on the sensing side;
[6] the second fluid cavity includes a buffer solution having a known pH;
[7] the semiconductor die further includes a second transistor having a second channel region; and
[8] the integrated circuit further comprises a second sensor terminal over the second channel region in the second fluid cavity.
As explained above, under claims 1-3, Cheng discloses each of features [1]-[5], [7], and [8] of claim 28. Cheng does not teach feature [6] of claim 28. As such, the prior art does not reasonably teach or suggest—in the context of claim 28—the limitation “the second fluid cavity includes a buffer solution having a known pH”.
Claims 29-38 would be allowable at least for including the same allowable limitation by depending from claim 28.
Claims 41-45 read
41. The integrated circuit of claim 39, wherein the particle filter includes a field effect terminal.
42. The integrate circuit of claim 39, wherein the particle filter includes a restricted portion of the fluid cavity and a field effect terminal in the restricted portion.
43. The integrate circuit of claim 39, wherein the particle filter is configured as part of a nanofluidic diode.
44. The integrate circuit of claim 15,
[1] wherein the sensor terminal is a first sensor terminal, the transistor is a first transistor, the channel region is a first channel region;
[2] wherein the semiconductor die further includes multiple transistors having respective channel regions;
[3a] wherein the integrated circuit further comprises
[3b] multiple sensor terminals over the respective channel regions in the fluid cavity,
[3c] the multiple sensor terminals arranged along a first axis orthogonal to a second axis between the first and second openings; and
[4] wherein a height of the fluid cavity decreases along the first axis.
45. The integrated circuit of claim 1, wherein:
[1] the fluid cavity has a ring footprint;
[2] the fluidic structure includes first inlets and first outlets for a first fluid, second inlets and second outlets for a second fluid, and third inlets and third outlets for a third fluid;
[3a] the integrated circuit includes
[3b] a first group of sensor terminals positioned along a first portion of the ring footprint between the first and third inlets,
[3c] a second group of sensor terminals positioned along a second portion of the ring footprint between the first and second outlets,
[3d] a third group of sensor terminals positioned along a third portion of the ring footprint between the second inlet and third outlet, and
[3e] a fourth group of sensor terminals positioned along a fourth portion of the ring footprint between the third inlet and the third outlet; and
[3f] a valve in the fourth portion of the ring footprint to control a flow of the third fluid between the third inlet and the third outlet.
The prior art does not reasonably teach or suggest—in the context of each of claims 41-45—the specific combination of elements.
V. Response to Arguments
Applicant’s arguments filed 12/02/2025 with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814