DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/31/2026 has been entered.
Response to Arguments
Applicant’s arguments filed 07/31/2026 have been fully considered but are moot in view of the new grounds of rejection in light of Applicant’s claim amendments as detailed below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2004/0130026 A1 to Imai et al., “Imai”.
Regarding claim 21, Imai discloses a transistor (FIG. 1K), comprising:
a semiconductor layer (silicon substrate 1, ¶ [0030]) having a first conductivity type (p-type) and a first band gap (Si ~ 1.12 eV);
a source region (12 on right, ¶ [0034]) and a drain region (12 on left) spaced apart over the semiconductor layer, source and drain regions having an opposite second conductivity type (n-type);
a gate electrode (6/7, ¶ [0032]) between the source region (12 on right) and the drain region (12 on left);
a source contact (15/16, ¶ [0037]) conductively connected to the source region (12 on right);
a drain contact (22/23/24, ¶ [0040]) over the drain region (12 on left);
a semiconductor material (silicon carbide (SiC) layer 21, ¶ [0040]-[0056]) between the drain contact and the drain region, the semiconductor material having a greater second band gap (SiC ~ 3.3 eV); and
a metal-containing conductor (19/20, ¶ [0039]) sandwiched between the semiconductor material (21) and the drain region (12 on left).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8,10 are rejected under 35 U.S.C. § 103 as being unpatentable over US 2010/0140713 A1 to IMOTO et al., “Imoto”, in view of US 2010/0073122 A1 to Le Neel et al., “Le Neel”.
Regarding claim 1, Imoto discloses a semiconductor device (FIG. 15A), comprising:
a switch element (“TRm”) having a surface and first (5) and second (7 and 8) regions and including a first semiconductor material (2) having a band-gap (silicon, ¶ [0093],[0137]), the first region of the switch element being coupled to a source contact (12, ¶ [0118],[0129],[0150]);
a voltage-support structure including a second semiconductor material (resistor 9F,¶ [0221]-[0225]);
a floating electrode (plug 11A, ¶ [0221]) sandwiched between the first semiconductor material (2) and the voltage-support structure (9F); and
a drain contact (13, ¶ [0221]) over the voltage-support structure.
Imoto fails to clearly state wherein the second semiconductor material (of thin film resistor layer 9F) has a band-gap that is greater than silicon (Si ~ 1.12 eV).
Le Neel teaches (e.g. FIG. 15) wherein a transistor (285, ¶ [0061]) connected to a thin-film resistor which includes a heater (106, ¶ [0031]-[0034]) and a resistor layer (108, ¶ [0038]-[0040]) separated by a thermal separator (214), wherein the thermal separator includes second semiconductor material (silicon carbide (SiC), ¶ [0048]) which inherently has a greater bandgap (SiC ~ 3.3 eV) than silicon (Si ~ 1.12 eV).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Imoto with the resistor including a thin film thermal separator as taught by Le Neel at least one of two configurations: either a single thin-film resistor layer together formed on a thin-film thermal separator in order to protect the resistor during temperature changes without cracking and with high breakdown voltage (Le Neel ¶ [0048]), or with a heater separated from the resistor by a thin-film thermal separator as taught by Le Neel in order to form a thin-film transistor which can be heat-trimmed and the resistance be set to a selected value over a wide range of possible resistances (Le Neel Abstract, ¶ [0004]-[0015]).
Regarding claim 2, although Imoto in view of Le Neel yields the semiconductor device of claim 1, Imoto fails to clearly state wherein the floating electrode (11A) includes at least one of metal or silicide.
Le Neel teaches wherein an electrode (e.g. FIG. 11 plugs 222s) are metal (¶ [0051]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Imoto with the floating electrodes (plugs 11A) made of metal as taught by Le Neel in order to form low-resistance electrical contacts and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 3, Imoto in view of Le Neel yields the semiconductor device of claim 1, and Imoto further teaches wherein: the floating electrode (plugs 11A) is in ohmic contact with the second region (8) of the switch element; and the floating electrode (Imoto 11A) is in ohmic contact with the voltage-support structure (Imoto resistor 9F, when applying teachings of Le Neel).
Regarding claim 4, Imoto in view of Le Neel yields the semiconductor device of claim 1, and Imoto further teaches wherein the switch element is a field-effect transistor (planar MOSFET as pictured, ¶ [0237])
Regarding claim 5, Imoto in view of Le Neel yields the semiconductor device of claim 4, and Imoto further teaches wherein: the switch element includes a field-effect transistor; and the field-effect transistor is an n-type field-effect transistor (Imoto ¶ [0097],[0238]).
Regarding claim 6, Imoto in view of Le Neel yields the semiconductor device of claim 5, and Imoto further teaches wherein the switch element is a laterally-diffused metal oxide semiconductor field-effect transistor (Imoto ¶ [0237]).
Regarding claim 7, Imoto in view of Le Neel yields the semiconductor device of claim 5, and Imoto further teaches wherein the switch element includes a gate (4, ¶ [0095]).
Regarding claim 8, Imoto in view of Le Neel yields the semiconductor device of claim 1, and Le Neel further teaches wherein the second semiconductor material includes silicon carbide (SiC ¶ [0048]).
Regarding claim 10, Imoto in view of Le Neel yields the semiconductor device of claim 1, and Imoto further teaches wherein the first semiconductor material includes silicon (¶ [0093]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0140713 A1 to IMOTO et al., “Imoto”, in view of US 2010/0073122 A1 to Le Neel et al., “Le Neel”, as applied to claim 1 above, and further in view of US 2020/0058788 A1 to Rahman et al., “Rahman”.
Although Imoto in view of Le Neel yields the semiconductor device of claim 1, Imoto fails to clearly teach (claim 11) a field-control element extending towards the drain contact, and (claim 12) wherein the field-control element is a field plate electrically coupled to the source contact.
Rahman teaches (FIG. 3) forming a field-control element (gate shield 48, ¶ [0025]) extending towards a drain (“D”), wherein the field-control element (48) is a field plate electrically coupled to the source contact (“S” 54).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Imoto in view of Le Neel with a gate shield as taught by Rahman in order to improve the shape of the electric field in the drain region (e.g. LDD region of an LDMOS) thus increasing the voltage blocking capability in the off-state and/or lower the gate-to-drain capacitance. In addition, the gate shield (field-control element) allows for a higher doping of the LDD by completely or partially removing localized high electric field due to voltage signals applied to the drain contact of the device. As a result, the on-state resistance of the power device can decrease while preserving the device's high breakdown. (Rahman ¶ [0004]).
Allowable Subject Matter
Claims 13-20 are allowed.
Claim 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior art e.g. Imoto in view of Le Neel yields the semiconductor device of claim 1 as discussed above, and prior art e.g. US 5,589,695 to Malhi teaches a semiconductor device (e.g. FIG. 2, column 4 lines 5-21), comprising:
a switch element (14’) having a surface (upper) and first (22 at “S”) and second (24 at “C”) regions and including a first semiconductor material (silicon substrate 12, column 4 line 12) having a band-gap, the first region of the switch element being coupled to a source contact (“S”);
a voltage-support structure (18) including a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material (high figure-of-merit e.g. GaAs or SiC, column 3 lines 60-63);
a floating electrode (“C” 34) (laterally and/or electrically) between the first semiconductor material (portion of 12 in region 14’ on left) and the voltage-support structure (18 on right); and
a drain contact (“D” 42) over the voltage-support structure, as discussed previously.
However, prior art fails to reasonably teach or suggest wherein the second semiconductor material includes a nano-tube material as claimed in claim 9 together with all of the limitations of claim 1.
Additionally, prior art e.g. US 2019/0058053 A1 to Dewey et al. discloses a semiconductor device (e.g. FIG. 1A), comprising:
a switch element (100, ¶ [0019]) having a surface (upper) and first (102 on left) and second (102 on right) regions and including a first semiconductor material having a band-gap (low band gap ¶ [0017]), the first region of the switch element including a source (102 on left) being coupled (as per definition of “coupled” in Applicant’s specification page 26 paragraph [0085] which allows for intervening elements) to a source contact (118 on left, ¶ [0019],[0020]);
a voltage-support structure (114 on right side, ¶ [0020]) including a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material (¶ [0021]-[0025]);
a contiguous floating electrode (116 on right side, ¶ [0020], contiguous within region to the right side of gate stack 106) over a portion of both the voltage-support structure (114 on right side) and the second region of the switch element; and
a drain contact (118 on right side of 108, ¶ [0019]) over the voltage-support structure (114 on right side), as discussed previously.
However, prior art fails to reasonably teach or suggest wherein the floating electrode is contiguous with both the voltage-support structure and the second region of the switch element, together with all of the limitations of claim 13 as claimed. Claims 14-20 are allowable insofar as they depend upon and include all of the limitations of allowable claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 6,731,531 B1 to Forbes et al. teaches (FIG. 3) a transistor (gate 325) with a source/drain diffusion (326b) and an electrode (334) and then a layer (338) formed of a second semiconductor material having a higher bandgap (338 is carburized i.e. silicon carbide, column 5 lines 59-65, SiC inherently has a higher bandgap than silicon).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891
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