DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/20/2026 has been entered.
Status of the Application
The Amendment filed on 2/5/2026, responding to the Office action mailed on 12/22/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-2, 4-5, 7-9, and 11-23 are pending in this application.
Claim Objections
Claim 1 is objected to because of the following informalities:
Line 10 on page 2 (printed text on page) repeats words that do not add meaning to the claim, “…between the at least one source region source region and the at least one …”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-5, 7-9, and 21-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "substrate" in lines 3 and 5 on page 2 (printed text on page). There is insufficient antecedent basis for this limitation in the claim.
Claims 2, 4-5, 7-9, and 21-23 are rejected as being dependent on claim 1.
For compact prosecution, the examiner interprets “substrate” to mean “semiconductor device”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-9, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 20210343645 A1) in view of Van (US 20220077062 A1) and Yang (US 20220310489 A1).
Re Claim 1 Peng teaches a semiconductor device (100a, FIG. 1C) [0020], comprising:
a backside power rail (210) [0047] located at a backside (bottom) of the semiconductor device (100a);
at least one source region (150a) [0027] that is not located at the backside of the semiconductor device (FIG. 1D),
at least one drain region (150b) [0027] that is not located at the backside of the semiconductor device (FIG. 1D),
a via (115) [0048] located between the first (104 on left in FIG. 1C) [0020] and the second (104 on right, FIG. 1C) NS, wherein the via (115) connects one of the at least one source region source region (150a, 185a is source contact [0036]) or the at least one drain region to the backside power rail (210), and wherein the via (115) is located between the at least one source region source region (150a) and the at least one drain region (150b, FIG. 1D);
two or more gates (130) [0024], each gate being connected to at least one of the first NS (130 on left is connected to 104 on left) or the second NS (130 on right is connected to 104 on right, FIG. 1C); and
a via spacer (110) located between the via (115) and each gate (130) which is adjacent to the via (110), and wherein the via spacer (110) is adjacent to the via (115, FIG. 1C).
Modified FIG. 1C below shows components being used as the nano sheets and gates
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The limitation “…wherein the via spacer prevents shorting between the via and each adjacent gate.” is merely functional/intended use limitation that do structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114.
Peng does not teach the at least one source region is located in a first nano sheet (NS) of the semiconductor device; and
wherein the at least one drain region is located in a second NS of the semiconductor device.
Van teaches the at least one source region (124a) [0032] is located in a first nano sheet (126) (NS) of the semiconductor device (FIG. 2); and
wherein the at least one drain region (124b) [0032] is located in a second (126) NS of the semiconductor device (FIG. 1A and 2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Van into the structure of Peng since Van teaches a gate all around device with a via integrated that connects the power rail and a source or drain region integrated to the device.
The ordinary artisan would have been motivated to modify Van in combination with Peng in the above manner for the motivation of combing the space for the source/drain regions with the nanosheets to help optimize the space in the device. [0018] states, “One challenge with the above semiconductor device is scaling down device features in order to increase device density without degrading device performance.”
Peng in view of Van does not teach the via spacer completely surrounds all surfaces of the via except where the via is connected to the backside power rail and the one of the at least one source region or the at least one drain region.
Yang teaches the via spacer (347, [0075] “liner”) completely surrounds all surfaces of the via (346) [0068] except where the via is connected to the backside power rail (322a) [0068] and at least one drain region (344, [0072], 344 and 343 are electrically connected by channel layers 352 [0072] , so 343 and 344 are both connected to 346, FIG. 3D-1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yang into the structure of Peng in view of Van since Yang teaches a gate all around device.
The ordinary artisan would have been motivated to modify Yang in combination with Peng in view of Van in the above manner for the motivation of integrating a VPBR to the gate all around device to optimize integration density in the device. [0001] states, “The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components, hence more functions, to be integrated into a given area, forming integrated circuit dies.”
Re Claim 2 Peng in view of Van and Yang teaches the semiconductor device of claim 1, further comprising a silicon nitride filled gate cut area (Peng, 160, [0031] states, “In some embodiments, the dummy fins 160 serve as portions of insulating gate-cut structures as shown in FIG. 1C, and are made of a nitride-based material, such as silicon nitride…”) located between the first and second NS's (104, see modified image above), wherein the via (115) is located outside of the silicon nitride filled gate cut area (FIG. 1C).
Re Claim 4 Peng in view of Van and Yang teaches the semiconductor device of claim 1, further comprising:
a backside power delivery network (Peng 210, [0047] “metal line”) on the backside of the semiconductor device, wherein the backside power delivery network (210) comprises the backside power rail (210, FIG. 1D).
Re Claim 7 Peng in view of Van and Yang teaches the semiconductor device of claim 1, wherein at least one source region (Peng, 185a) and the at least one drain region (185b) are connected to respective contacts (190a and 190b) on a frontside of the semiconductor device (FIG. 1A and 1D).
Re Claim 8 Peng in view of Van and Yang teaches the semiconductor device of claim 1, further comprising:
a backside power delivery network (Peng, 210) that comprises the backside power rail (210, FIG. 1C).
Re Claim 9 Peng in view of Van and Yang teaches the semiconductor device of claim 1, wherein the via spacer (Peng, 110) comprises (112) [0022] a dielectric material (FIG. 1C).
Re Claim 21 Peng in view of Van and Yang teaches the semiconductor device of claim 1, wherein the via (Yang, 346) comprises a metal material ([0076] states, “…any suitable metal such as Cu, Al, Co, Ru, Mo, Ir, W, or related alloys, is then formed in the opening on the silicide layer 345, forming the backside power rail 346…”).
Re Claim 22 Peng in view of Van and Yang teaches the semiconductor device of claim 21, wherein the metal material comprises at least one of cobalt, ruthenium, or copper (Yang, [0076] states, “…any suitable metal such as Cu, Al, Co, Ru, Mo, Ir, W, or related alloys, is then formed in the opening on the silicide layer 345, forming the backside power rail 346…”).
Re Claim 23 Peng in view of Van and Yang teaches the semiconductor device of claim 21, wherein the metal material comprises at least one molybdenum, tungsten, or rhodium (Yang, [0076] states, “…any suitable metal such as Cu, Al, Co, Ru, Mo, Ir, W, or related alloys, is then formed in the opening on the silicide layer 345, forming the backside power rail 346…”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 20210343645 A1) in view of Van (US 20220077062 A1) and Yang (US 20220310489 A1) as applied to claim 1 above, and further in view of Su (US 20210399109 A1, cited in IDS).
Re Claim 5 Peng in view of Van and Yang teaches the semiconductor device of claim 1, but does not teach the via spacer comprises one or more layers of silicon oxycarbide (SiOC).
Su teaches the via spacer (140, [0028] “liner layer”) comprises one or more layers of silicon oxycarbide (SiOC) ([0028] “…140 may include…SiOC…”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Su into the structure of Peng in view of Van and Yang since Su teaches device with a VPBR integrated.
The ordinary artisan would have been motivated to modify Su in combination with Peng in view of Van and Yang in the above manner for the motivation of using SiOC to form spacer layers to build an optimal semiconductor device and keep costs to a minimum without sacrificing performance. [0002] states, “As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs…”
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 5/18/26
Prosecution Insights