CTNF 18/067,127 CTNF 89973 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election with traverse of claims 1-14 drawn to Group I (a semiconductor device) in the reply filed on 05/04/2026 is acknowledged. The traversal is on the grounds that there is no serious burden. This is not found persuasive because of clearly different classifications for the method and device claims, and the fact that the device can be formed by a different method, rather than the method of claims 17-20, specifically, without forming a sacrificial plug. The method claims 15-16 that are not patentably distinct from device claims are examined on the merits. Applicant argues that there is no search burden. However, for purposes of the initial requirement, a serious search burden on the examiner may be prima facie shown by appropriate explanation of separate classification, or separate status in the art, or a different field of search as defined in MPEP 808.02: Where, as disclosed in the application, the several inventions claimed are related, and such related inventions are not patentably distinct as claimed, restriction under 35 U.S.C. 121 is never proper (MPEP § 806.05). If applicant voluntarily files claims to such related inventions in different applications, double patenting may be held. Where the inventions as claimed are shown to be independent or distinct under the criteria of MPEP § 806.05(c) - § 806.06, the examiner, in order to establish reasons for insisting upon restriction, must explain why there would be a serious search and/or examination burden on the examiner if restriction is not required. In order to demonstrate a serious search burden, the examiner must show by appropriate explanation one of the following: (A) Separate classification thereof: This shows that each invention has attained recognition in the art as a separate subject for inventive effort, and also a separate field of search. Patents need not be cited to show separate classification. (B) A separate status in the art when they are classifiable together: Even though they are classified together, each invention can be shown to have formed a separate subject for inventive effort when the examiner can show a recognition of separate inventive effort by inventors. Separate status in the art may be shown by citing patents which are evidence of such separate status, and also of a separate field of search. (C) A different field of search: Where it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s) (e.g., searching different classes/subclasses or electronic resources, or employing different search queries), a different field of search is shown, even though the two are classified together. The indicated different field of search must in fact be pertinent to the type of subject matter covered by the claims. Patents need not be cited to show different fields of search. The Election/Restriction requirement has shown a burden. The requirement is still deemed proper and is therefore made FINAL. Claims 15-16 are linking claims of Invention II which are not patentably distinct from Invention. Therefore, claims 15-16 were not restricted and are examined on the merits in this Office Action with claims 1-14. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 and 15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Xie et. al., U.S. Pat. Pub. 2022/0223698, hereafter Xie . Regarding claim 1, Xie discloses (Fig 19A, B) a semiconductor device, comprising: a front-end-of-line (FEOL) layer (everything above the spacer [53]) including a FEOL device (the nanosheet transistor of Fig. 19 A, B); a backside power line [31]-[32] on a back side of the FEOL layer; and a conductive structure [11], [12] that contacts the FEOL device [71] (source/drain of the nanosheet transistor) at a front side of the FEOL layer and that extends through the FEOL layer (see annotated Fig. 19B below) to contact the backside power line [31]-[32], including a frontside part that includes a metal liner [11] and a first fill material [12] and a backside part that includes a second fill material [12] having an outer surface that aligns with an outer surface of the metal liner [11]. Regarding claim 15, Xie discloses (Fig 1-19A, B, see annotatede Fig. 19B below) a method for forming a semiconductor device, comprising: forming a front-end-of-line (FEOL) layer (everything above the spacer [53]) that includes a FEOL device (the nanosheet transistor of Fig. 19 A, B); forming a frontside conductive contact [11],[12] on the FEOL device, including a metal liner [11] between the frontside conductive contact [32] and the FEOL device; and forming a backside conductive contact [11],[12] in electrical contact with the frontside conductive contact [11],[12], an outer surface of the backside conductive contact [11],[12] aligning with an outer surface of the metal liner [11]. PNG media_image1.png 1066 1193 media_image1.png Greyscale Regarding claim 15, Xie discloses (Fig 1-19A, B) a method for forming a semiconductor device, comprising: forming a front-end-of-line (FEOL) layer (everything above the spacer [53]) that includes a FEOL device (the nanosheet transistor of Fig. 19 A, B); forming a frontside conductive contact [11],[12] on the FEOL device, including a metal liner [11] between the frontside conductive contact [32] and the FEOL device; and forming a backside conductive contact [11],[12] in electrical contact with the frontside conductive contact [11],[12], an outer surface of the backside conductive contact [32] aligning with an outer surface of the metal liner [11] (see annotated Figs 19B) . 07-15-03-aia AIA Claim s 1-3, 9, and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Majhi et. al., U.S. Pat. Pub. 2023/0197613, hereafter Majhi . Regarding claim 1, Majhi discloses (Figs 1A-1F) A semiconductor device [100] (IC [100] includes nanowire transistors [101a], [101b]), comprising: a front-end-of-line (FEOL) layer [125] including a FEOL device [100] (IC, par. [0030]); a backside power line [112] (par. [0027]) on a back side of the FEOL layer [125]; and a conductive structure [114], [116], [113], [117], [119] that contacts the FEOL device at a front side of the FEOL layer and that extends through the FEOL layer to contact the backside power line ([117],[112]), including a frontside part [114], [116], [119] that includes a metal liner [119] and a first fill material [114], [116] and a backside part [113], [117] that includes a second fill material [113] having an outer surface (top surface) that aligns with an outer surface of the metal liner [119]. Regarding claim 2, Majhi further discloses (Figs 1A-1F, par. [0042], [0050]) wherein the frontside part of the conductive structure includes a first metal and the metal liner includes a metal nitride. Regarding claim 3, Majhi further discloses (Figs 1A-1F, par. [0050]) wherein the metal liner [119] further includes a metal silicide (TaSiN, TiSiN, WSiN) in direct contact with a source/drain structure [106b] of the FEOL device. Regarding claim 9, Majhi further discloses (par.[0054]) further comprising a back-end-of-line (BEOL) layer on the front side of the FEOL layer. Regarding claim 15, Majhi discloses (Figs 1A-1F) a method for forming a semiconductor device [100], comprising: forming a front-end-of-line (FEOL) layer [125] that includes a FEOL device [100] (IC, par. [0030]); forming a frontside conductive contact [114],[116],[119] on the FEOL device, including a metal liner [119] between the frontside conductive contact [116] and the FEOL device [106b]; and forming a backside conductive contact [11],[12] in electrical contact with the frontside conductive contact [113],[117], an outer surface of the backside conductive contact [114],[119] aligning with an outer surface of the metal liner [119] (see Fig. 1C) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Majhi et. al., U.S. Pat. Pub. 2023/0197613, hereafter Majhi . Regarding claim 4, Majhi discloses everything as applied above. Majhi further discloses (Figs 1A-1F, par. [0042], [0050]) different metals for the backside structure [113],[117] and the front side structure [114], [119], so Majhi discloses that materials can be different. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to apply different materials because optimizing materials of integrated circuits for thermal and electrical requirements is routine in the art. Regarding claim 5, Majhi discloses everything as applied above. Majhi further discloses various materials (par. [0042], [0050]) suitable for the structure. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to apply different materials for the backside part, backside power line, and frontside part, because optimizing materials of integrated circuits for thermal and electrical requirements is routine in the art . 07-21-aia AIA Claim s 6-7, 10-11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Majhi et. al., U.S. Pat. Pub. 2023/0197613, hereafter Majhi, in view of Sung, U.S. Pat. Pub. 2020/0027777, hereafter Sung . Regarding claim 6, Majhi discloses everything as applied above. Majhi fails to explicitly disclose further comprising a dielectric liner on sidewalls of the backside part of the conductive structure, formed from a first dielectric material. However, Sung discloses (Fig. 1, par. [0027]) further comprising a dielectric liner [140] on sidewalls of the backside part of the conductive structure [140], [145], [146], formed from a first dielectric material (e.g., Silicon Nitride, par. [0027]). It would have been obvious to one of ordinary skill in the art to modify Majhi with the teachings of a dielectric liner of Sung because such a liner provides better isolation. Regarding claim 7, Majhi in view of Sung discloses everything as applied above. Sung further discloses (Fig. 1) further comprising an interlayer dielectric [134] (par. [0025], silicon dioxide is frequently used as an interlayer dielectric material) around the dielectric liner, formed from a second dielectric material different from the first dielectric material (the materials in pars. [0025] and [0027] are different dielectrics). Regarding claim 10, Majhi discloses (Figs 1A-1F) a semiconductor device [100] (IC [100] includes nanowire transistors [101a], [101b]), comprising: a front-end-of-line (FEOL) layer [125] including a FEOL device [100] (IC, par. [0030]); a backside power line [112] (par. [0027]) on a back side of the FEOL layer [125]; and a conductive structure [114], [116], [113], [117], [119] that contacts the FEOL device at a front side of the FEOL layer and that extends through the FEOL layer to contact the backside power line ([117],[112]), including a frontside part [114], [116], [119] that includes a metal liner [119] and a first fill material [114], [116] and a backside part [113], [117] that includes a second fill material [113] having an outer surface (top surface) that aligns with an outer surface of the metal liner [119]. Majhi fails to explicitly disclose a dielectric liner on sidewalls of the backside part of the conductive structure, including a first dielectric material; and an interlayer dielectric around the dielectric liner, including a second dielectric material different from the first dielectric material. However, Sung discloses (Fig. 1, par. [0027]) further comprising a dielectric liner [140] on sidewalls of the backside part of the conductive structure [140], [145], [146], formed from a first dielectric material (e.g., Silicon Nitride, par. [0027]). an interlayer dielectric [134] (par. [0025], silicon dioxide is frequently used as an interlayer dielectric material) around the dielectric liner, formed from a second dielectric material different from the first dielectric material (the materials in pars. [0025] and [0027] are different dielectrics). It would have been obvious to one of ordinary skill in the art to modify Majhi with the teachings of a dielectric liner of Sung because such a liner provides better isolation. Regarding claim 11, Majhi in view of Sung discloses everything as applied above. Majhi further discloses (Figs 1A-1F, par. [0042], [0050]) wherein the frontside part of the conductive structure includes a first metal and the metal liner includes a metal nitride. Regarding claim 12, Majhi in view of Sung discloses everything as applied above. Majhi further discloses (Figs 1A-1F, par. [0050]) wherein the metal liner [119] further includes a metal silicide (TaSiN, TiSiN, WSiN) in direct contact with a source/drain structure [106b] of the FEOL device. Regarding claim 13, Majhi in view of Sung discloses everything as applied above. Majhi further discloses various materials (par. [0042], [0050]) suitable for the structure. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to apply different materials for the backside part, backside power line, and frontside part, because optimizing materials of integrated circuits for thermal and electrical requirements is routine in the art. Regarding claim 16, Majhi in view of Sung discloses everything as applied above. Sung further discloses (Fig. 2D) further comprising forming a dielectric-lined [140] via [145] through the FEOL layer. (par. [0027], [0025]) It would have been obvious to one of ordinary skill in the art to modify Smith with the teachings of a dielectric liner of Sung because such a liner provides better isolation . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to explicitly disclose or make obvious wherein the backside part of the conductive structure extends farther from the back side of the FEOL layer than the dielectric liner . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure – background prior art in power rails for semiconductor devices . Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VICTOR V BARZYKIN/ Examiner, Art Unit 2893 /Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893 Application/Control Number: 18/067,127 Page 2 Art Unit: 2893 Application/Control Number: 18/067,127 Page 3 Art Unit: 2893 Application/Control Number: 18/067,127 Page 4 Art Unit: 2893 Application/Control Number: 18/067,127 Page 5 Art Unit: 2893 Application/Control Number: 18/067,127 Page 6 Art Unit: 2893 Application/Control Number: 18/067,127 Page 7 Art Unit: 2893 Application/Control Number: 18/067,127 Page 8 Art Unit: 2893 Application/Control Number: 18/067,127 Page 9 Art Unit: 2893 Application/Control Number: 18/067,127 Page 10 Art Unit: 2893 Application/Control Number: 18/067,127 Page 11 Art Unit: 2893
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