DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2022/0077134) by Chen et al (“Chen”) in view of (US-2022/0382949) by Lee et al (“Lee”).
Regarding claim 1, Chen discloses in FIGs. 1 & 2C and related text, e.g., a multi-layer integrated circuit (IC) having a three-dimensional structure (see cited figures; all “integrated circuits” are three-dimensional) formed along an x-axis, a y-axis and a z-axis, the multi-layer IC comprising:
a back-end-of-line (BEOL) region (typically, this is interpreted as wiring above transistors; FIG. 1, “Frontside Signal Lines” and “Frontside Metal Layers” reads on all the metal lines above transistors) at a first side of a wafer (FIG. 1; “Frontside”);
a backside region at a second side of the wafer (“Backside”) that is opposite the first side of the wafer;
a set of signal lines in the BEOL region (“Backside Metal Layers”);
power rails (“Backside Supply Rails”) in the backside region, the power rails comprising a first set of power rails and a second set of power rails (so, a total of 4 power rails; 2 in one set and 2 in another; this is inherent and notoriously well-known in any sufficiently big standard cell layout; just 4 rows of cells will give the necessary number of power rails);
a first cell and a second cell (same reasoning as power rails; inherent and notoriously well-known for the same reasons as above), each positioned between the BEOL region and the backside region (that is where cells are, by definition; cells contain transistors; transistors are located between BEOL region and the backside region; also see FIG. 3, 310 and related text);
wherein the first cell comprises:
first cell logic gates configured to perform a first cell logic function (inherent and notoriously well-known; that is what cells normally contain (logic gates, which perform a given logic function); and
first cell tracks comprising a first portion of the set of signal lines and a first portion of power rails (see FIG. 2C and FIG. 3, 310 and related text; also, inherent and notoriously well-known; that is the point of cells [Wingdings font/0xE0] to have tracks of signal lines and to have shared power rails);
wherein the second cell comprises:
second cell logic gates configured to perform a second cell logic function (same logic as first cell);
second cell tacks comprising a second portion of the set of signal lines and a second portion of the power rails (same logic as first cell);
wherein the set of signal lines comprises a substantially constant signal-line pitch between each signal line in the set of signal lines (see FIG. 2C, “FS/M1” signal lines; the pitch between some of the groups is shown to be “substantially constant”).
Chen does not disclose “wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power-rail pitch between each power rail in the second set of power rails“.
To elaborate briefly on the above, Chen does not appear to say anything at all about “power-rail pitch”. Whether it is “substantially constant” or “substantially varying” is simply unknown.
Lee discloses in FIG. 1 and related text, e.g., “wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power-rail pitch between each power rail in the second set of power rails” (see FIG. 1; it shows two cells: C01 with height H1, and C02 with height H2; they each have set of power rails (VDD/VSS); the pitch between the two is different; thus meeting limitations).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Chen with “wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power-rail pitch between each power rail in the second set of power rails” as taught by Lee, in order to allow for multi-height cell integrated circuit design (Title, Abstract, etc.; it is the whole point of the reference).
Regarding claim 2, the combined device of Chen and Lee disclose in cited figures and related text, e.g., further comprising a backside power distribution network (BSPDN) electrically coupled to the power rails (such as BSB in FIG. 1 and par. 14; the “Backside Supply Rails” are connected to other layers, such as “power connection bumps” (BSB); that, and the necessary interconnections between “118” and “BSB” are all part of “backside power distribution network”).
Regarding claim 3, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein the first cell comprises a first cell height extending along a z-axis (Y axis in Lee, FIG. 1, C01) and defined by the first cell tracks (see FIG. 1, C01, and see M1 tracks).
Regarding claim 4, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein the second cell comprises a second cell height extending along the Z-axis and defined by the second cell tracks (see FIG. 1, C02, and see M1 tracks).
Regarding claim 5, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein the second cell is positioned adjacent to the first cell (see FIG. 4B of Lee and related text; all sorts of arrangements of cells of various heights “adjacent” to each other are shown and discussed).
Regarding claim 6, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein the second cell height is greater than the first cell height (see FIG. 1).
Regarding claim 7, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein:
the set of signal lines extends over the first cell and the second cell (that is the whole point; cells are to be interconnected; hence, that is what they do [Wingdings font/0xE0] signal lines extend between cells; inherent and notoriously well-known); he first set of power rails extends under the first cell (in combined device; the multi-height design of FIG. 4B of Lee, with “under rails” of Chen, would have a first set of power rails);
the second set of power rails extends under the second cell (same logic as first cell);
the set of signal lines is less thick, more densely packed, and less widely spaced than the power rails (less thick signal lines are shown in FIG. 1 of Lee; more densely packed signal lines are shown in FIG. 2B of Chen, less widely spaced is also shown in FIG. 2B of Chen); and
locating the set of signal lines at the first side of the wafer and the set of power rails at the second side of the wafer that is opposite the first side of the wafer separates the set of signal lines from the power rails (that is the basic architecture of Chen, so far) such that the set of signal lines is patterned and formed in substantially straight lines without irregular shapes (see FIG. 2B, of Chen), and the set of power rails, being thicker and spaced further apart than the set of signal lines, are formed in patterns that enable a coupling between the first set of power rails and the second set of power rails (see FIG. 7 of Lee for coupling between power rails; together, the two references teach all limitations).
Regarding claim 8, the combined device of Chen and Lee disclose in cited figures and related text, e.g., a multi-layer integrated circuit (IC) having a three-dimensional structure (see cited figures; all “integrated circuits” are three-dimensional) formed along an x-axis, a y-axis and a z-axis, the multi-layer IC comprising:
a first region at a first side of a wafer (see claim 1; “BEOL”);
a second region at a second side of the wafer that is opposite the first side of the wafer (see claim 1; “backside region”);
a third region of the wafer between the first region and the second region (see claim 1; “first cell”, etc.);
a set of signal lines in the first region (see claim 1);
power rails in the second region (see claim 1), power rails comprising a first set of power rails and a second set of power rails (see claim 1);
a first cell positioned in the third region (see claim 1);
a second cell adjacent to the first cell and positioned in the third region (see claims 1 & 5); and
a backside power distribution network (BSPDN) electrically coupled to the set of power rails (see claim 2);
wherein the first cell comprises:
first cell logic gates configured to perform a first cell logic function (see claim 1); and
first cell tracks comprising a first portion of the set of signal lines and a first portion of the power rails (see claim 1);
wherein the second cell comprises:
second cell logic gates configured to perform a second cell logic function (see claim 1); and
second cell tracks comprising a second portion of the set of signal lines and a second portion of the power rails (see claim 1);
wherein the set of signal lines comprises a signal-line pitch between each signal line in the set of signal lines (see claim 1);
wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power rail pitch between each power rail in the second set of power rails (see claim 1); and
wherein the first power-rail pitch and the second power rail pitch substantially vary from one another (see FIG. 7 of Lee), and the signal-line pitch does not substantially vary (see FIG. 2B of Chen).
Regarding claim 9, the combined device of Chen and Lee disclose in cited figures and related text, e.g., see claims 3-6.
Regarding claim 10, the combined device of Chen and Lee disclose in cited figures and related text, e.g., see claim 7.
Regarding claim 11, the combined device of Chen and Lee disclose in cited figures and related text, e.g., see claim 7.
Regarding claim 12, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein the first region comprises a metal layer (see claim 1; cited layers include metal layers).
Regarding claim 13, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein the first side of the wafer comprises a front side of the wafer (see claim 1).
Regarding claim 14, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein the second side of the wafer comprises a backside of the wafer (see claim 1).
Regarding claim 15, the combined device of Chen and Lee disclose in cited figures and related text, e.g., a multi-layer integrated circuit (IC) structure (see claims 1 & 8) comprising:
a back-end-of-line (BEOL) region at a first side of a wafer (see claim 1);
a backside region at a second side of the wafer that is opposite the first side of the wafer (see claim 1);
a front-end-of-line (FEOL) region (transistors) of the wafer between the BEOL region and the backside region (that is where transistors are; they are between BEOL wiring, and backside wiring);
a set of signal lines in the BEOL region (see claim 1);
power rails in the backside region, the power rails comprising a first of power rails and a second set of power rails (see claim 1);
a first cell positioned in the FEOL region and having a first cell height (see claims 3 & 5);
a second cell adjacent to the first cell, positioned in the FEOL region, and having a second cell height that is greater than the first cell height (see claims 4 & 6); and
a backside power distribution network (BSPDN) electrically coupled to the set of power rails (see claim 2);
wherein the first cell comprises:
first cell logic gates configured to perform a first cell logic function (see claim 1); and
first cell tracks comprising a first portion of the set of signal lines and a first portion of the power rails (see claim 1);
wherein the second cell comprises:
second cell logic gates configured to perform a second cell logic function (see claim 1); and
second cell tracks comprising a second portion of the set of signal lines and a second portion of the power rails (see claim 1);
wherein the set of signal lines comprises a signal-line pitch between each signal line in the set of signal lines (see claim 8);
wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power rail pitch between each power rail in the second set of power rails (see claim 1); and
wherein the first power-rail pitch and the second power rail pitch substantially vary from one another (see FIG. 7 of Lee), and the signal-line pitch does not substantially vary (see FIG. 2B of Chen).
Regarding claim 16, the combined device of Chen and Lee disclose in cited figures and related text, e.g., see claims 3 & 4.
Regarding claim 17, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein the first cell logic gates are electrically coupled to the set of signal lines and the first set of power rails (inherent and notoriously well-known; the whole point of cells (and its internal cell gates) is to be connected to a set of signals; same for its power rails); and
the second cell logic gates are electrically coupled to the set of signal lines and the second set of power rails (notoriously well-known; second set of power rails was already discussed [Wingdings font/0xE0] it is a cell of different height and different power rails; as far as cells being coupled to the same or different set of signal lines, it all depends on whether they are connected together in a circuit diagram; if yes, then same set of signal lines, by definition).
Regarding claim 18, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein a width dimension of each signal line in the set of signal lines is less than width dimensions of power rails in the first set of power rails and power rails the second set of power rails (discussed in claim 7).
Regarding claim 19, the combined device of Chen and Lee disclose in cited figures and related text, e.g., wherein each of the first power-rail pitch and the second power-rail pitch is greater than the signal-line pitch that does not substantially vary (see claim 7).
Response to Arguments
Applicant’s arguments with respect to above claims have been considered but are moot because the arguments do not apply to the current rejection.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
03/17/26
/Mounir S Amer/Primary Examiner, Art Unit 2818