Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 05/05/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US Patent Pub 20220344233 A1).
Regarding Claim 1, Chang teaches a semiconductor device, comprising:
a front-end-of-line (FEOL) layer (Fig. 3, Layer marked by arrows and labeled FEOL (See annotated figure below));
a back-end-of-line (BEOL) layer that includes a thermal transfer structure in contact with the FEOL layer (Fig. 3, Layer marked by arrows and labeled BEOL (See annotated figure below). BEOL layer includes thermal transfer structure (plurality of horizontal and vertical thermal structures 222 and 220));
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and a carrier wafer bonded to the BEOL layer that includes a thermal dissipation structure in thermal contact with the thermal transfer structure (Fig. 3, carrier wafer 214 bonded to the BEOL via 212. The thermal dissipation structure is the top portion of 208a marked by the yellow line (Figures 4P-Q and paragraph 0070 teaches the deposition of the second portion of 208a), 212, the portion of 220 located in 212, and 214. The thermal dissipation structure is in thermal contact with the thermal transfer structure).
Regarding Claim 2, Cheng teaches the semiconductor device of claim 1, wherein the thermal transfer structure includes vertical vias relative to a plane of the FEOL layer and penetrates the BEOL layer to make thermal contact with the FEOL layer (Fig. 3, the thermal transfer structure includes vertical vias, including 224, which is vertical and penetrates the BEOL to make thermal contact with the FEOL layer).
Regarding Claim 3, Cheng teaches the semiconductor device of claim 2, wherein the FEOL layer includes a first thermal via that makes thermal contact with the thermal transfer structure (Fig. 3, FEOL Layer includes first thermal via 222 (portion of 222 on right side of FEOL) which makes thermal contact with the thermal transfer structure through 220).
Regarding Claim 4, Cheng teaches the semiconductor device of claim 3, further comprising a backside layer, on a side of the FEOL layer opposite to the BEOL layer, wherein the backside layer includes another thermal transfer structure that completely penetrates the backside layer and that is in thermal contact with the first thermal via (Fig. 3, backside layer 324 which includes another thermal transfer structure 224 which completely penetrates 324 and is in thermal contact with first thermal via (portion of 222 on right side of FEOL)).
Regarding claim 5, Cheng teaches the semiconductor device of claim 3, wherein the BEOL layer further includes a crack stop structure formed from a thermally conductive material that makes thermal contact with a second thermal via of the FEOL layer (Fig. 3. Applicant’s own specification (paragraph 0030-0031) teaches the crack stop features may include vertical vias and horizontal connecting structures passing through a dielectric material of the BEOL, and are formed of a conductive material such has copper. Therefore, any of the plurality of thermal transfer structure features 222 and 220 located in the dielectric layer 208a (Cheng, paragraph 0030 teaches 220 and 222 can be formed of copper. Paragraph 0027 teaches 208a is a dielectric layer) of the BEOL layer can be crack stop features which thermally connect to a second thermal via of the FEOL layer (222 located on the left side of the FEOL)).
Regarding Claim 6, Cheng teaches the semiconductor device of claim 1, further comprising a bonding layer between the BEOL layer and the carrier wafer that includes a thermal via between the thermal transfer structure and the thermal dissipation structure to make thermal contact with the thermal transfer structure and the thermal dissipation structure (Fig. 3, bonding layer 212 between BEOL layer and the carrier wafer 214. Thermal vias 222 (See annotated figure above) located in the thermal dissipation structure allow the thermal transfer structure to make thermal contact with the thermal dissipation structure).
Regarding Claim 7, Cheng teaches the semiconductor device of claim 1, wherein the thermal transfer structure includes a pad of thermally conductive material on a surface of the BEOL layer (Fig. 3, thermal transfer structure includes pad of thermally conductive material (220 located on surface of BEOL layer contacting the thermal dissipation structure (see annotated figure above))) .
Regarding Claim 8, Cheng teaches the semiconductor device of claim 1, wherein thermal dissipation structure includes a wire that connects to multiple thermal transfer structures (Fig. 3, thermal dissipation structure includes wiring (portion of 220 located in 212) that connects to multiple thermal transfer structures 222).
Regarding Claim 9, Cheng teaches the semiconductor device of claim 1, wherein the BEOL layer further includes a horizontal thermally conductive wire that thermally connects multiple thermal transfer structures together (Fig. 3, BEOL layer includes a wire (portion of 220 located on left side of surface of FEOL) that connects multiple thermal transfer structures 222 together).
Regarding Claim 10, Cheng teaches a semiconductor device, comprising:
a front-end-of-line (FEOL) layer that includes a thermal via (Fig. 3, Layer marked by arrows and labeled FEOL (See annotated figure below). FEOL layer includes a thermal via 222 on right side of FEOL);
a back-end-of-line (BEOL) layer that includes a first thermal transfer structure in thermal contact with the thermal via (Fig. 3, Layer marked by arrows and labeled BEOL (See annotated figure below). BEOL layer includes a first thermal transfer structure 220 (220 on the right side of the BEOL layer on surface of FEOL layer) in contact with thermal via 222 on right side of FEOL layer);
a backside layer, on a side of the FEOL opposite to the BEOL layer, that includes a second thermal transfer structure in thermal contact with the thermal via (Fig 3, backside layer 324 which includes a second thermal transfer structure 224 in thermal contact with thermal via 222 (on right side of FEOL));
and a carrier wafer bonded to the BEOL layer that includes a thermal dissipation structure thermal in contact with the first thermal transfer structure (Fig. 3, carrier wafer 214 bonded to BEOL layer via 212. 212 includes a thermal dissipation structure (the thermal dissipation structure is the top portion of 208a marked by the yellow line (Figures 4P-Q and paragraph 0070 teaches the deposition of the second portion of 208a), 212, the portion of 220 located in 212, and 214). The thermal dissipation structure is in thermal contact with the first thermal transfer structure though 222 (222 on right side of BEOL layer in thermal contact with 220 on right side of BEOL layer located on surface of FEOL layer).
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Regarding Claim 11, Cheng teaches the semiconductor device of claim 10, wherein the BEOL layer further includes a crack stop structure formed from a thermally conductive material that makes thermal contact with a second thermal via of the FEOL layer (Fig. 3. Applicant’s own specification (paragraph 0030-0031) teaches the crack stop features may include vertical vias and horizontal connecting structures passing through a dielectric material of the BEOL, and are formed of a conductive material such has copper. Therefore, any of the plurality of thermal transfer structure features 222 and 220 located in dielectric layer 208a of the BEOL can be crack stop features, which thermally connect to a second thermal via of the FEOL layer (222 located on the left side of the FEOL)).
Regarding Claim 12, Cheng teaches the semiconductor device of claim 10, further comprising a bonding layer between the BEOL layer and the carrier wafer that includes another thermal via between the first thermal transfer structure and the thermal dissipation structure to make thermal contact with the thermal transfer structure and the thermal dissipation structure (Fig. 3, bonding layer 212 between BEOL layer and the carrier wafer 214. Thermal vias 222 (See annotated figure above) located in the thermal dissipation structure allow the first thermal transfer structure to make thermal contact with the thermal dissipation structure).
Regarding Claim 13, Cheng teaches the semiconductor device of claim 10, wherein the thermal dissipation structure includes a wire that connects to multiple thermal transfer structures (Fig. 3, thermal dissipation structure (portion of 220 located in 212) is wiring that connects to multiple thermal transfer structures 222).
Regarding Claim 14, Cheng teaches the semiconductor device of claim 10, wherein the BEOL layer further includes a horizontal thermally conductive wire that thermally connects multiple thermal transfer structures together (Fig. 3, BEOL layer includes a wire (portion of 220 located on left side of surface of FEOL) that connects multiple thermal transfer structures 222 together).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTO-892) attached herewith.
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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