DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1, 3-5, and 7-22 are pending in this application.
Claim Rejections - 35 USC § 112
Claim 13 and claim 15 112(b) rejections are withdrawn since the claim amendments files 9/11/2025 overcome the rejections.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 7-8, 10-11, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strogies et al. (US 20200139490 A1) in view of Viswanathan (US 20180033716 A1, given in IDS).
Re Claim 1 Strogies teaches a metal layer stack for use in electronic components comprising n bulk metal layers (12, [0029] “…12 consist of a metal foil…”) and n+1 contact material layers (13) [0029], wherein the bulk metal layers and the contact material layers are stacked in an alternating manner, and n is at least two (FIG. 2).
Strogies does not teach at least one of the contact material layers comprises a sinter material, the sinter material being a sinter precursor or a sintered joint.
Viswanathan teaches at least one of the contact material layers (50 and 52) comprises a sinter material ([0032] states, “Sintered bond layers 50, 52 are composed predominately of one or more sintered metals…”), the sinter material being a sinter precursor or a sintered joint ([0013] states, “…by tailoring the formulation of the precursor material from which the sintered layers are produced …”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Viswanathan into the structure of Strogies since both patents teach stacked metal structures for use in electrical components.333
The ordinary artisan would have been motivated to modify + in combination with +++ in the above manner for the motivation of using a sinter material for the contact layers. [0013] states, “Additionally, by controlling sintering parameters and by tailoring the formulation of the precursor material from which the sintered layers are produced, the sintered bond layers can be produced to contain organic materials, such as a strength-enhancing epoxy, or consist essentially of a highly conductive metal (e.g., silver, gold, or copper) lacking non-trace amounts of organic materials. The end result is highly efficient multilayer heat sink fabrication process…”
Re Claim 3 Strogies in view of Viswanathan teaches the metal layer stack according to claim 1, but does not explicitly teach the mean thickness of each contact material layer is in the range from 10 µm to 100 µm.
Viswanathan [0032] teaches, “…the thickness of sintered bond layers 50, 52 will vary amongst embodiments, but may range between about 5 and about 100 μm …”
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal mean thickness of the contact material layer.
Re Claim 4 Strogies in view of Viswanathan teaches the metal layer stack according to claim 1, wherein each bulk metal layer comprises a metal ([0029] “The first layers 12 consist of a metal foil 14, which according to FIG. 1 is produced from a solder material, for example a tin-silver-copper alloy…”) selected from the group consisting of copper, molybdenum, tungsten, silver, aluminium and combinations thereof.
Re Claim 7 Strogies in view of Viswanathan teaches the metal layer stack according to claim 1, wherein the sinter material (Viswanathan, 50 and 52, [0013] states, “…the sintered bond layers can be produced to contain organic materials, such as a strength-enhancing epoxy, or consist essentially of a highly conductive metal (e.g., silver, gold, or copper) lacking non-trace amounts of organic materials.”) comprises a metal selected from the group consisting of silver, copper, aluminium, tin, indium, bismuth, nickel and zinc.
Re Claim 8 Strogies in view of Viswanathan teaches a semiconductor module wherein a first surface of a semiconductor chip (Strogies [0036] states, “The first connection partner 24 according to FIG. 6 consists of power semiconductor components…”) is in contact with a first contact material layer (Strogies FIG. 2 is 11, and 11 and 24 are mechanically connected in FIG. 7 and therefore in contact) of the metal layer stack according to claim 1.
Re Claim 10 Strogies in view of Viswanathan teaches the semiconductor module according to claim 8, wherein further comprising at least one gate runner (Viswanathan 60, [0035] “mount pad bond”) arranged between the semiconductor chip (74) and the metal layer stack (FIG. 7).
Re Claim 11 Strogies in view of Viswanathan teaches the semiconductor module according to claim 8, wherein the metal layer stack (Strogies, 11, FIG. 2) functions as a spacer (FIG. 7).
Re Claim 14 Strogies in view of Viswanathan teaches a precursor for a spacer comprising a metal layer stack according to claim 1, wherein at least the first or the last contact material layer of the metal layer stack comprises a sinter precursor (Viswanathan FIG. 4, [0036] states, “…is also preformed to sinter precursor layers 38 and 40 (FIGS. 3 and 4) and yield sintered bond layers (FIGS. 5 and 6).”)
Re Claim 15 Strogies in view of Viswanathan teaches a process for producing a metal layer stack, preferably according to claim 1, the process comprising the steps of:
a) providing a carrier (Strogies, 25, FIG. 7) [0036],
b) providing a first layer assembly comprising a contact material precursor layer (13 on bottom FIG. 2, FIG.2 is 11 and sits on 25 in FIG. 7) arranged on a bulk metal layer (12),
c) arranging the first layer assembly on the carrier such that the contact material precursor layer is in contact with the carrier (layers are mechanically connected and are therefore in contact, FIG. 7),
d) providing a second further layer assembly comprising a contact material precursor (13 in middle, FIG. 2) arranged on a bulk metal layer (top 12, FIG. 2),
e) arranging the second further layer assembly on the bulk metal layer of the first layer assembly such that the contact material precursor of the second further layer assembly is in contact with the bulk metal layer of the first layer assembly (FIG. 2, and
f) arranging a last contact material precursor layer (13 on top, FIG. 2) on the bulk metal layer of the further layer assembly such that the last contact material precursor layer is in contact with the bulk metal layer of the further layer (layer are mechanically connected, FIG. 7).
Strogies modified FIG. 2 is shown below with parts identified
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Re Claim 16 Strogies in view of Viswanathan teaches the process according to claim 15, comprising: g) converting the contact material precursor layers (Viswanathan, 50 and 52) into layers of joint material ([0031] “sintered bond layers 50, 52”).
Re Claim 21 Strogies in view of Viswanathan teaches the metal layer stack (Viswanathan, FIG. 7) according to claim 1, wherein each of the contact material layers (50, 52) comprise a sinter material ([0031] “sintered bond layers 50, 52”).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strogies et al. (US 20200139490 A1) in view of Viswanathan (US 20180033716 A1, given in IDS) and further in view of Jha et al. (US 5156923 A, given in IDS).
Re Claim 5 Strogies in view of Viswanathan teaches the metal layer stack according to claim 1, but does not teach the mean thickness of the bulk metal layers is in the range from 50 µm to 600 µm.
Jha col 3 line 46 teaches, “…metal layers each have an initial thickness of 0.020 inches (508 µm)…”
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jha into the structure of Strogies in view of Viswanathan to reach optimum bulk metal thickness.
The ordinary artisan would have been motivated to modify + in combination with +++ in the above manner for the motivation of reaching optimal bulk metal thickness.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal bulk metal thickness.
Claim(s) 9 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strogies et al. (US 20200139490 A1) in view of Viswanathan (US 20180033716 A1, given in IDS) and further in view of Otsuka et al. (US 20130001782 A1).
Re Claim 9 Strogies in view of Viswanathan teaches the semiconductor module according to claim 8,
Otsuka teaches a substrate (6) [0058] attached to the last contact material layer (82) [0047] of the metal layer stack (80, FIG. 5).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Otsuka into the structure of Strogies in view of Viswanathan since Otsuka also teaches a metal stack structure for a semiconductor structure.
The ordinary artisan would have been motivated to modify Otsuka in combination with Strogies in view of Viswanathan in the above manner for the motivation of integrating a substrate to the semiconductor module to provide an insulating structure around the device ([0029] “insulating substrate”).
Re Claim 17 Strogies in view of Viswanathan teaches the process according to claim 15, but does not teach, after step e) and before step f), repeating steps d) and e) with one of more additional further layer assemblies.
Otsuka teaches repeating steps d) and e) with one of more additional further layer assemblies (FIG. 1A, use top 82 and 81, [0047]).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Otsuka into the structure of Strogies in view of Viswanathan since Otsuka teaches a semiconductor structure that integrates H01L 23/3735 -- Laminates or multilayers, e.g. direct bond copper ceramic substrates.
The ordinary artisan would have been motivated to modify Koyanagi in combination with Strogies in view of Viswanathan in the above manner for the motivation of adding additional layer assemblies to control the thickness of the metal stack.
Re Claim 18 Strogies in view of Viswanathan and Otsuka teaches the process according to claim 17, further comprising:
g) converting the contact material precursor layers into layers of joint material ([0031] “sintered bond layers 50, 52”, the process applied to 50 and 52 can be repeated).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strogies et al. (US 20200139490 A1) in view of Viswanathan (US 20180033716 A1, given in IDS) and further in view of Tzu (US 20210358876 A1).
Re Claim 12 Strogies in view of Viswanathan teaches the semiconductor module according to claim 8, but does not teach a second surface of the semiconductor chip opposite to the first surface contacts a second substrate.
Tzu teaches a second surface (top) of the semiconductor chip (206) [0064] opposite to the first surface (bottom) contacts a second substrate (204, [0064], FIG. 4A, 206 and 204 are in thermal contact).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Tzu into the structure of Strogies in view of Viswanathan since Tzu teaches a semiconductor structure that integrates H01L 23/3735 -- Laminates or multilayers, e.g. direct bond copper ceramic substrates.
The ordinary artisan would have been motivated to modify Tzu in combination with Strogies in view of Viswanathan in the above manner for the motivation of integrating a 2nd substrate in the device to use direct bond copper substrates to protect the top of the device. [0011] states, “…the first substrate and the second substrate include direct bond copper (DBC) substrates.”
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strogies et al. (US 20200139490 A1) in view of Viswanathan (US 20180033716 A1, given in IDS) and further in view of Yamazaki (US 20140131700 A1).
Re Claim 13 Strogies in view of Viswanathan teaches the semiconductor module according to claim 9, but does not teach one or more substrates of the semiconductor module are selected from the group consisting of the substrate is a metal ceramic substrates substrate, an organic substrates substrate, an insulated metal substrates substrate, a lead frames and frame, or a ceramic substrates substrate.
Yamazaki teaches the substrate (102, FIG. 5C) is a ceramic substrate ([0084] states, “For the substrate 102, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yamazaki into the structure of Strogies in view of Viswanathan since Yamazaki teaches integrating a semiconductor chip with a substrate.
The ordinary artisan would have been motivated to modify Yamazaki in combination with Strogies in view of Viswanathan in the above manner for the motivation of using a ceramic substrate. It is critical to use an optimal material for the substrate if it is used for more than just simply a support structure. [0061] states, “The substrate 102 is not limited to a simple supporting substrate, and may be a substrate where another device such as a transistor is formed.”
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strogies et al. (US 20200139490 A1) in view of Viswanathan (US 20180033716 A1, given in IDS) and further in view of Piao et al. (CN 110943061 A).
Re Claim 19 Strogies in view of Viswanathan teaches the semiconductor module according to claim 8, but does not teach a first additional layer arranged next to the first contact material layer and a second additional layer arranged next to the last contact material layer, the first and second additional layers comprising a prefixing agent.
Piao teaches a first additional layer (150, page 9 par 2 “first adhesive layer”) arranged next to the first contact material layer (144, page 7 par 2 “bonding pad”) and a second additional layer (process can be repeated, concept is the same because it is using a prefixing agent/adhesive to bond metal layer 144 to a substrate 110) arranged next to the last contact material layer, the first and second additional layers comprising a prefixing agent (FIG. 5).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Piao into the structure of Strogies in view of Viswanathan since Piao teaches a semiconductor structure that integrates bonding metals layers to substrates with prefixing agents.
The ordinary artisan would have been motivated to modify Piao in combination with Bo in view of Viswanathan in the above manner for the motivation of using a prefixing agent to secure semiconductor layers to a substrate and ensure stability for the semiconductor structure.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strogies et al. (US 20200139490 A1) in view of Viswanathan (US 20180033716 A1, given in IDS) and Tzu (US 20210358876 A1) and further in view of Yamazaki (US 20140131700 A1).
Re Claim 20 Strogies in view of Viswanathan and Tzu teaches the semiconductor module according to claim 12, but does not teach the second substrate is a metal ceramic substrate, an organic substrate, an insulated metal substrate, a lead frame, or a ceramic substrate.
Yamazaki teaches the second substrate (reuse 102 for top/2nd substrate as Tzu taught 2nd substrate presence, FIG. 5C) is a ceramic substrate ([0084] states, “For the substrate 102, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yamazaki into the structure of Strogies in view of Viswanathan and Tzu since Yamazaki teaches integrating a semiconductor chip with a substrate.
The ordinary artisan would have been motivated to modify Yamazaki in combination with Strogies in view of Viswanathan and Tzu in the above manner for the motivation of using a ceramic substrate. It is critical to use an optimal material for the substrate if it is used for more than just simply a support structure. [0061] states, “The substrate 102 is not limited to a simple supporting substrate, and may be a substrate where another device such as a transistor is formed.”
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strogies et al. (US 20200139490 A1) in view of Viswanathan (US 20180033716 A1, given in IDS) and further in view of Orso et al. (DE 102014221306 A1).
Re Claim 22 Strogies in view of Viswanathan teaches the metal layer stack according to claim 1, but does not explicitly teach the sinter material comprises:
at least 80 wt% of silver or copper; and
up to 20 wt% a metal selected from the group consisting of aluminium, tin, indium, bismuth, nickel and zinc.
Orso teaches the sinter layer (40, page 3 par 1) is made of silver-aluminum (page 3 last par, “The sinter layer is made of nickel or copper and/or silver and/or aluminum and/or alloy.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Orso into the structure of Strogies in view of Viswanathan since Orso teaches bonding semiconductors with adhesive materials.
The ordinary artisan would have been motivated to modify Orso in combination with Strogies in view of Viswanathan in the above manner for the motivation of using a sinter material with silver and aluminum to help reduce manufacturing costs. Page 3 par 6 states, “ADVANTAGE - The surface of the strip conductor and/or the electrical conductive contact is formed by the sinter layer or the solder layer, thus increasing safety of the electrical contact of the electrical and/or electronic element and reducing manufacturing cost of the circuitry carrier in an inexpensive manner.”
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the optimal sinter material is made with at least 80% of its weight being silver and up to 20% of its weight being aluminum.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-4, 7-8, 10-11, and 14-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818