4DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-6 and 8-24 are pending.
Claims 1-3. 8-10, 15, 16, 20, and 21 are amended.
Claim 7 is cancelled.
Claims 22-24 are new.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/27/2026 has been entered.
Response to Arguments/Amendments
Applicant’s arguments, see pages 6-9, filed 02/27/2026, with respect to the rejections of amended independent claims 1, 9, and 20 under 35 USC 102(a)(1) have been fully considered but are not persuasive. Specifically, the introduction of the claim limitation ”a screen layer… is outside of a second area under a second field effect transistor adjacent to the first field effect transistor,” is taught by the prior art of record of Stoffels (US PGPub 2017/0263700), as Stoffels teaches a fully isolated and separated screen layer that is under the first field effect transistor, and wherein that individual screen layer is not under the second field effect transistor. Stoffels teaches a second, separate screen layer under the second field effect transistor, but the examiner notes that this is fully isolated and separated from the first field effect transistor, and the therefore, the first screen layer is outside of the second area under the second field effect transistor. The rejection of claims 1, 9, and 20 is upheld.
Additionally, upon further consideration, a new, additional grounds of rejection is made in view of Izpura (US PGPub 2009/0134435).
Drawings
The objection to the drawings of 12/02/2025 have been overcome by the cancellation of claim 7 in the amended claims filed 02/27/2026. The objection has been withdrawn.
Claim Rejections - 35 USC § 112
The rejection of claim 7 under 35 USC 112 of 12/02/2025 has been overcome by the cancellation of claim 7 in the amended claims filed 02/27/2026. The rejection has been withdrawn.
Election/Restrictions
Newly submitted claims 22-24 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
This application contains claims directed to the following patentably distinct species:
Species 1: Wherein the node is a source, seemingly corresponding to claims 22-24
Species 2: Wherein the node is a drain, seemingly corresponding to claim 2.
The species are independent or distinct because the claims to the different species recite the mutually exclusive characteristics of such species, wherein the node is either a source or a drain of the first FET. In addition, these species are not obvious variants of each other based on the current record.
There is a serious search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply: the species or groupings of patentably indistinct species have acquired a separate status in the art in view of their different classification.
For example, species 1 would require a keyword search including but not limited to: source, p-, n-. Species 2 would require a keyword search including but not limited to, drain, p+, n+.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, Species 2, claims 22-24 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
Amended claims 20 and 21 and new claim 24 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Group 1, claims 1-6, 8, and 22 and Group 3, claims 20, 21, and 24, are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case, the product as claimed can be made by another and materially different process. For example, the microelectronic device of claim 1 could be made by forming a screen layer by a subtractive etching process as opposed to an additive implant process, in order to improve precision of manufacturing. (Note: Groups 1 and 3 were not originally restricted on the merits as there was not, at that time, a search burden between the product and method. Amendment of claims 20 and 21 have introduced a specific method step that now creates support for a restriction and creates a search burden, so the invention of Group 1 has been constructively elected by original presentation.)
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: The inventions have acquired a separate status in the art in view of their different classification, including at least H10W15/01 and H10D30/015.
Group 2, claims 9-19, and 23, was not originally restricted from Group 1, as it did not contain any specific method steps to support a restriction, nor was there any search burden. Similarly, with the recent amendment, no burden has been added, nor reason to support a restriction. Therefore, Groups 1 and 2 are not restrictable and are examined together. Since applicant has received an action on the merits for the originally presented invention, Groups 1 and 2, this invention has been constructively elected by original presentation for prosecution on the merits.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, Group 3, claims 20, 21, and 24 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-13, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stoffels et al. (US PGPub 2017/0263700), herein referred to as Stoffels_A. (Note: Stoffels_A refers to a first interpretation of the prior art of Stoffels).
Regarding claim 1, Stoffels_A teaches (annotated Fig. 2 below) a microelectronic device, comprising: a substrate (1, [0045]); a lower buffer layer (2, [0046]) of III-N semiconductor material over the substrate; a screen layer (10, [0046, 0054]) having free charge carriers ([0054]) over the lower buffer layer; a first field effect transistor (FET) having III-N semiconductor material; and a contact (12, [0047]) electrically connected to the screen layer and to a node (6, [0047]) of the first field effect transistor, wherein the screen layer is localized to a first area under the first field effect transistor (Fig. 6, the screen layer 10 is depicted spanning a horizontal area below the FET of the microelectronic device, deviated from a second FET by an isolation region 20, thus the screen layer 10 is isolated to the FET directly above it), and is outside of a second area under a second field effect transistor adjacent to the first field effect transistor (the screen layer 10 under the first FET is fully separated and isolated from the screen layer 10 under the second FET, thus the first screen layer is outside of a second area under a second FET).
Regarding claim 2, Stoffels_A teaches (Fig. 2) the microelectronic device of claim 1, wherein the node (6, [0047])) is a source of the first field effect transistor ([0047]).
Regarding claim 3, Stoffels_A teaches (Fig. 2) the microelectronic device of claim 1, further including an upper buffer layer (2U) between the screen layer (10) and the first field effect transistor (FET). The field effect transistor is interpreted to be the layers above the buffer and screen layers, as defined by the instant application.
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Regarding claim 4, Stoffels_A teaches (Fig. 2) the microelectronic device, wherein the screen layer (10, [0054-0055]) includes a first conductivity type doped layer (10, [0054]) of III-N semiconductor material.
Regarding claim 5, Stoffels_A teaches (Fig. 2) the microelectronic device of claim 1, wherein the screen layer includes a screen barrier layer (10, [0046]) of III-N semiconductor material on the lower buffer layer (2, [0046]), the screen barrier layer (10) having a higher band gap than the lower buffer layer (2) contacting the screen barrier layer [(0057]). Stoffels_A teaches that at the interface between two layers within the buffer layer, there can be a step in concentration, which can lead to the formation of a hole or electron gas (a 2DEG or 2DHG), and that one of these sublayers within the buffer layer is considered the screen barrier layer ([0057]). In order to form a 2DEG or 2DHG (Fig. 2, 11), there must be a bandgap differential between screen barrier layer (10) and lower buffer layer (2), defined by the step in concentration. Stoffels_A teaches wherein the bandgap of the screen barrier layer can be higher or lower than that of the buffer layer by preferential doping in order to create a 2DEG or 2DHG screen layer that shields the 2DEG of the FET from substrate bias, helping avoid depletion of the 2DEG of the FET ([0050]).
Regarding claim 6, Stoffels_A teaches (Fig. 2) the microelectronic device of claim 5, wherein the screen barrier layer includes aluminum (10, [0056]).
Regarding claim 9, Stoffels_A teaches (Fig. 2) a method, comprising: forming a screen layer (10, [0050]) including gallium nitride ([0055]) over a lower buffer layer (2, [0046]) of III-N semiconductor material, the screen layer including free charge carriers ([0050]), wherein the screen layer is localized to a first area under a first field effect transistor and is outside of a second area under a second field effect transistor adjacent to the first field effect transistor (the screen layer 10 under the first FET is fully separated and isolated from the screen layer 10 under the second FET, thus the first screen layer is outside of a second area under a second FET).
Regarding claim 10, Stoffels_A teaches (annotated Fig. 2 above) the method of claim 9, further including: forming the first field effect transistor (FET, 0043]) having III-N semiconductor material over the screen layer; and forming a contact (12, [0047]) electrically connected to the screen layer and to a node (6, [0046]) of the field effect transistor.
Regarding claim 11, Stoffels_A teaches (annotated Fig. 2 below) the method of claim 9, wherein the lower buffer layer (2L, [0050]) is located over a substrate (1, [0044]).
Regarding claim 12, Stoffels_A teaches (annotated Fig. 2 below) the method of claim 9, further including forming an upper buffer (2U, [0050]) layer over the screen layer (11, [0054]).
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Regarding claim 13, Stoffels_A teaches (Fig. 2) the method of claim 9, wherein forming the screen layer (11, [0054-0055]) includes forming a first conductivity type doped layer (10, [0054]) of the gallium nitride ([0055]).
Regarding claim 17, Stoffels_A teaches (Fig. 2) the method of claim 9, wherein forming the screen layer includes forming a screen barrier layer (10, [0046]) of III-N semiconductor material on the lower buffer layer (2, [0046]), the screen barrier layer (10) having a higher band gap than the lower buffer layer (2) contacting the screen barrier layer [(0057]). Stoffels_A teaches that at the interface between two layers within the buffer layer, there can be a step in concentration, which can lead to the formation of a hole or electron gas (a 2DEG or 2DHG), and that one of these sublayers within the buffer layer is considered the screen barrier layer ([0057]). In order to form a 2DEG or 2DHG (Fig. 2, 11), there must be a bandgap differential between screen barrier layer (10) and lower buffer layer (2), defined by the step in concentration. Stoffels_A teaches wherein the bandgap of the screen barrier layer can be higher or lower than that of the buffer layer by preferential doping in order to create a 2DEG or 2DHG screen layer that shields the 2DEG of the FET from substrate bias, helping avoid depletion of the 2DEG of the FET ([0050]).
Regarding claim 18, Stoffels_A teaches (Fig. 2) the method of claim 17, wherein the screen barrier layer includes aluminum (10, [0056]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Stoffels_A as applied to claim 1 above, and further in view of Lidow et al. (US PGPub 2012/0153300), herein referred to as Lidow.
Regarding claim 8, Stoffels_A teaches (annotated Fig. 6 below) the microelectronic device of claim 1, wherein the first field effect transistor is a high side transistor (FET1, [0071]), and the second field effect transistor is a low side transistor (FET2, [0071]) of III-N semiconductor material in a half bridge configuration ([0071]).
Stoffels_A does not explicitly show wherein a drain of the low side transistor is electrically connected to a source of the high side transistor, however, Stoffels_A does teach that the high side and low side FETs are arranged in a half bridge configuration. A typical half bridge arrangement contains a source of a high side FET connected to a drain of a low side FET.
Lidow teaches (Fig. 12), wherein a drain (125, [0089]) of the low side transistor ([0090]) is electrically connected to a source (129, [0089]) of the high side transistor ([0090]).
Stoffels_A teaches a high side transistor and low side transistor arranged to form a half-bridge device.
Lidow teaches two transistors arranged in a half-bridge configuration, wherein the source of one transistor is connected to the drain of the other transistor. Lidow further teaches that this connection exists to form a half-bridge circuit device.
One of ordinary skill in the art would have understood that the source and drain connection of Lidow could be substituted into the structure of Stoffels_A for the predictable result of forming a half-bridge circuit device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the source-drain connection of Lidow for the source-drain of Stoffels_A for the purpose of forming a half-bridge circuit device. See MPEP 2143(I)(b).
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Claims 14-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Stoffels_A as applied to claims 1, 9, and 13 above, and further in view of Tipirneni et al. (US Patent 8759879), herein referred to as Tipirneni.
Regarding claim 14, Stoffels_A teaches (Fig. 2) the method of claim 13, wherein forming the first conductivity type doped layer (10, [0056]) includes adding dopants ([0058]) during a growth process ([0056]). Stoffels_A does not explicitly teach an epitaxial growth process.
Tipirneni teaches (Fig. 3) forming the first conductivity type doped layer (326, [0030]) including adding dopants during an epitaxial growth process ([0030]).
Because Stoffels_A and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels_A and Tipirneni in order to form a blanket layer with uniform doping (Tipirneni, [0030]).
Regarding claim 15, Stoffels_A in view of Tipirneni teaches (Stoffels_A, Fig. 2) the method of claim 13. Stoffels_A in view of Tipirneni further teaches wherein forming the first conductivity type doped layer (11) includes implanting dopants into the gallium nitride (Stoffels_A, [0055]) of the screen layer (Tipirneni, [[0030]).
Because Stoffels_A and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Stoffels_A and Tipirneni in order to achieve desired doping density ([0030]).
Regarding claim 16, Stoffels_A in view of Tipirneni teaches the method of claim 15, and further teach further including forming an implant mask over the gallium nitride of the screen layer, exposing the gallium nitride in an area for the screen layer, and implanting the dopants into the gallium nitride (Stoffels_A, [0055]) where exposed by the implant mask (Tipirneni, [0030]).
Because Stoffels_A and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Stoffels_A and Tipirneni in order to selectively dope the surface of the device solely on the screen layer, and not on other coplanar layers ([0030]).
Regarding claim 19, Stoffels_A teaches the method of claim 9, but does not explicitly teach further including patterning the screen layer ([0030]).
Tipirneni teaches further including patterning the screen layer ([0030]).
Because Stoffels_A and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels_A and Tipirneni in order to create a screen layer than selectively covers the buffer layer below it (Tipirneni, [0030]).
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Claims 1-6, 9-13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Stoffels_B in view of Izpura (US PGPub 2009/0134435, herein known as Izpura). (Note: Stoffels_B refers to a second interpretation of the prior art of Stoffels).
Regarding claim 1, Stoffels_B teaches (annotated Fig. 2 below) a microelectronic device, comprising: a substrate (1, [0045]); a lower buffer layer (2, [0046]) of III-N semiconductor material over the substrate; a screen layer (10, [0046, 0054]) having free charge carriers ([0054]) over the lower buffer layer; a first field effect transistor (FET) having III-N semiconductor material; and a contact (12, [0047]) electrically connected to the screen layer and to a node (6, [0047]) of the first field effect transistor. Stoffels_B does not explicitly teach wherein the screen layer is localized to a first area under the first field effect transistor and is outside of a second area under a second field effect transistor adjacent to the first field effect transistor.
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Izpura teaches (Fig. 1) a screen layer (2) wherein the screen layer is localized to a first area under the first field effect transistor (10, [0018]) and is outside of a second area under a second field effect transistor (11, [0018]) adjacent to the first field effect transistor.
Because Stoffels_B and Izpura are both directed toward HEMT devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels_B and Izpura to include wherein the screen layer is localized to a first area under the first field effect transistor and is outside of a second area under a second field effect transistor adjacent to the first field effect transistor in order to have regions with isolated devices with very good performances at high frequencies and other regions with very low excess noise devices protected (Izpura, [0018]).
Regarding claim 2, Stoffels_B in view of Izpura teaches (Stoffels_B, Fig. 2) the microelectronic device of claim 1, wherein the node (6, [0047])) is a source of the first field effect transistor ([0047]).
Regarding claim 3, Stoffels_B in view of Izpura teaches (Stoffels_B, annotated Fig. 2 below) the microelectronic device of claim 1, further including an upper buffer layer (2U) between the screen layer (10) and the first field effect transistor (FET). The field effect transistor is interpreted to be the layers above the buffer and screen layers, as defined by the instant application.
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Regarding claim 4, Stoffels_B in view of Izpura teaches (Stoffels_B, Fig. 2) the microelectronic device, wherein the screen layer (10, [0054-0055]) includes a first conductivity type doped layer (10, [0054]) of III-N semiconductor material.
Regarding claim 5, Stoffels_B in view of Izpura teaches (Stoffels_B, Fig. 2) the microelectronic device of claim 1, wherein the screen layer includes a screen barrier layer (10, [0046]) of III-N semiconductor material on the lower buffer layer (2, [0046]), the screen barrier layer (10) having a higher band gap than the lower buffer layer (2) contacting the screen barrier layer [(0057]). Stoffels_B teaches that at the interface between two layers within the buffer layer, there can be a step in concentration, which can lead to the formation of a hole or electron gas (a 2DEG or 2DHG), and that one of these sublayers within the buffer layer is considered the screen barrier layer ([0057]). In order to form a 2DEG or 2DHG (Fig. 2, 11), there must be a bandgap differential between screen barrier layer (10) and lower buffer layer (2), defined by the step in concentration. Stoffels_B teaches wherein the bandgap of the screen barrier layer can be higher or lower than that of the buffer layer by preferential doping in order to create a 2DEG or 2DHG screen layer that shields the 2DEG of the FET from substrate bias, helping avoid depletion of the 2DEG of the FET ([0050]).
Regarding claim 6, Stoffels_B in view of Izpura teaches (Stoffels_B, Fig. 2) the microelectronic device of claim 5, wherein the screen barrier layer includes aluminum (10, [0056]).
Regarding claim 9, Stoffels_B teaches (Fig. 2) a method, comprising: forming a screen layer (10, [0050]) including gallium nitride ([0055]) over a lower buffer layer (2, [0046]) of III-N semiconductor material, the screen layer including free charge carriers ([0050]).
Izpura teaches (Fig. 1) a screen layer (2) wherein the screen layer is localized to a first area under the first field effect transistor (10, [0018]) and is outside of a second area under a second field effect transistor (11, [0018]) adjacent to the first field effect transistor.
Because Stoffels_B and Izpura are both directed toward HEMT devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels_B and Izpura to include wherein the screen layer is localized to a first area under the first field effect transistor and is outside of a second area under a second field effect transistor adjacent to the first field effect transistor in order to have regions with isolated devices with very good performances at high frequencies and other regions with very low excess noise devices protected (Izpura, [0018]).
Regarding claim 10, Stoffels_B in view of Izpura teaches (Stoffels_B, annotated Fig. 2 above) the method of claim 9, further including: forming the first field effect transistor (FET, 0043]) having III-N semiconductor material over the screen layer; and forming a contact (12, [0047]) electrically connected to the screen layer and to a node (6, [0046]) of the field effect transistor.
Regarding claim 11, Stoffels_B in view of Izpura teaches (Stoffels_B, annotated Fig. 2 above) the method of claim 9, wherein the lower buffer layer (2L, [0050]) is located over a substrate (1, [0044]).
Regarding claim 12, Stoffels_B in view of Izpura teaches (Stoffels_B, annotated Fig. 2 above) the method of claim 9, further including forming an upper buffer (2U, [0050]) layer over the screen layer (11, [0054]).
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Regarding claim 13, Stoffels_B in view of Izpura teaches (Stoffels_B, Fig. 2) the method of claim 9, wherein forming the screen layer (11, [0054-0055]) includes forming a first conductivity type doped layer (10, [0054]) of the gallium nitride ([0055]).
Regarding claim 17, Stoffels_B in view of Izpura teaches (Stoffels_B, Fig. 2) the method of claim 9, wherein forming the screen layer includes forming a screen barrier layer (10, [0046]) of III-N semiconductor material on the lower buffer layer (2, [0046]), the screen barrier layer (10) having a higher band gap than the lower buffer layer (2) contacting the screen barrier layer [(0057]). Stoffels_B teaches that at the interface between two layers within the buffer layer, there can be a step in concentration, which can lead to the formation of a hole or electron gas (a 2DEG or 2DHG), and that one of these sublayers within the buffer layer is considered the screen barrier layer ([0057]). In order to form a 2DEG or 2DHG (Fig. 2, 11), there must be a bandgap differential between screen barrier layer (10) and lower buffer layer (2), defined by the step in concentration. Stoffels_B teaches wherein the bandgap of the screen barrier layer can be higher or lower than that of the buffer layer by preferential doping in order to create a 2DEG or 2DHG screen layer that shields the 2DEG of the FET from substrate bias, helping avoid depletion of the 2DEG of the FET ([0050]).
Regarding claim 18, Stoffels_B in view of Izpura teaches (Stoffels_B, Fig. 2) the method of claim 17, wherein the screen barrier layer includes aluminum (10, [0056]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Stoffels_B in view of Izpura as applied to claim 1 above, and further in view of Lidow et al. (US PGPub 2012/0153300), herein referred to as Lidow.
Regarding claim 8, Stoffels_B in view of Izpura teaches (Stoffels_B, annotated Fig. 6 below) the microelectronic device of claim 1, wherein the first field effect transistor is a high side transistor (FET1, [0071]), and the second field effect transistor is a low side transistor (FET2, [0071]) of III-N semiconductor material in a half bridge configuration ([0071]).
Stoffels_B in view of Izpura does not explicitly show wherein a drain of the low side transistor is electrically connected to a source of the high side transistor, however, Stoffels_B in view of Izpura does teach that the high side and low side FETs are arranged in a half bridge configuration. A typical half bridge arrangement contains a source of a high side FET connected to a drain of a low side FET.
Lidow teaches (Fig. 12), wherein a drain (125, [0089]) of the low side transistor ([0090]) is electrically connected to a source (129, [0089]) of the high side transistor ([0090]).
Stoffels_B in view of Izpura teaches a high side transistor and low side transistor arranged to form a half-bridge device.
Lidow teaches two transistors arranged in a half-bridge configuration, wherein the source of one transistor is connected to the drain of the other transistor. Lidow further teaches that this connection exists to form a half-bridge circuit device.
One of ordinary skill in the art would have understood that the source and drain connection of Lidow could be substituted into the structure of Stoffels_B in view of Izpura for the predictable result of forming a half-bridge circuit device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the source-drain connection of Lidow for the source-drain of Stoffels_B in view of Izpura for the purpose of forming a half-bridge circuit device. See MPEP 2143(I)(b).
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Claims 14-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Stoffels_B in view of Izpura as applied to claims 1, 9, and 13 above, and further in view of Tipirneni et al. (US Patent 8759879), herein referred to as Tipirneni.
Regarding claim 14, Stoffels_B in view of Izpura teaches (Stoffels_B, Fig. 2) the method of claim 13, wherein forming the first conductivity type doped layer (10, [0056]) includes adding dopants ([0058]) during a growth process ([0056]). Stoffels_B in view of Izpura does not explicitly teach an epitaxial growth process.
Tipirneni teaches (Fig. 3) forming the first conductivity type doped layer (326, [0030]) including adding dopants during an epitaxial growth process ([0030]).
Because Stoffels_B in view of Izpura and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels_B in view of Izpura and Tipirneni in order to form a blanket layer with uniform doping (Tipirneni, [0030]).
Regarding claim 15, Stoffels_B in view of Izpura and Tipirneni teaches (Stoffels_B, Fig. 2) the method of claim 13. Stoffels_B in view of Tipirneni further teaches wherein forming the first conductivity type doped layer (11) includes implanting dopants into the gallium nitride (Stoffels_B, [0055]) of the screen layer (Tipirneni, [[0030]).
Because Stoffels_B in view of Izpura and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Stoffels_B in view of Izpura and Tipirneni in order to achieve desired doping density ([0030]).
Regarding claim 16, Stoffels_B in view of Izpura and Tipirneni teaches the method of claim 15, and further teach further including forming an implant mask over the gallium nitride of the screen layer, exposing the gallium nitride in an area for the screen layer, and implanting the dopants into the gallium nitride (Stoffels_B, [0055]) where exposed by the implant mask (Tipirneni, [0030]).
Because Stoffels_B in view of Izpura and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Stoffels_B in view of Izpura and Tipirneni in order to selectively dope the surface of the device solely on the screen layer, and not on other coplanar layers ([0030]).
Regarding claim 19, Stoffels_B in view of Izpura teaches the method of claim 9, but does not explicitly teach further including patterning the screen layer ([0030]).
Tipirneni teaches further including patterning the screen layer ([0030]).
Because Stoffels_B in view of Izpura and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels_B in view of Izpura and Tipirneni in order to create a screen layer than selectively covers the buffer layer below it (Tipirneni, [0030]).
Conclusion
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812