DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 2, 4-6, 8-11, and 13-24 are pending.
Claims 20-24 are withdrawn.
Claims 1, 9, 13, 15, and 16 are amended.
Claims 3 and 12 are cancelled.
Response to Arguments
Applicant’s arguments, see pages 7-8, filed 06/24/2026, with respect to amended independent claims 1 and 9 have been fully considered and are persuasive. The rejection of claims 1-6, 9-13, 17, and 18 under 35 USC 102(a)(1) as being anticipated by Stoffels_A (US PGPub 2017/0263700) of 03/26/2026 has been withdrawn. Accordingly, the rejections of dependent claims 8, 14-16, and 19 as rejected utilizing the interpretation Stoffels_A have been withdrawn.
Applicant's arguments filed 06/24/2026 have been fully considered but they are not persuasive. Specifically, the inclusion of new claim language in independent claims 1 and 9 to include “wherein the upper buffer layer comprises a bottom surface that is in contact with a top surface of the lower buffer layer in the second area” does not overcome the prior art of record of Stoffels_B (US PGPub 2017/0263700) in view of Izpura (US PGPub 2009/0134435). Applicant’s arguments, see pages 9-10, address the teachings of the prior art references of Stoffels and Izpura independently, and do not address the combination of references. Stoffels teaches a lower and upper buffer layer sandwiching a screen layer, and Izpura teaches localization of a screen layer to the area underneath an active device to isolate other devices at high frequencies. The rejections of independent claims 1 and 9 are upheld. The rejections of dependent claims 2, 4-6, 10, 11, and 13-19 are upheld, accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 9-11, 13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Stoffels (US PGPub 2017/0263700; herein known as Stoffels) in view of Izpura (US PGPub 2009/0134435; herein known as Izpura).
Regarding claim 1, Stoffels teaches (annotated Fig. 2 below) a microelectronic device, comprising: a substrate (1, [0045]); a lower buffer layer (2L, [0046]) of III-N semiconductor material over the substrate; a screen layer (10, [0046, 0054]) having free charge carriers ([0054]) over the lower buffer layer; a first field effect transistor (FET) having III-N semiconductor material; an upper buffer layer (2U, [0046]) over the screen layer in the first area under the first field effect transistor (FET) and over the lower buffer layer in the second area under the second field effect transistor (8) and a contact (12, [0047]) electrically connected to the screen layer and to a node (6, [0047]) of the first field effect transistor. Stoffels does not explicitly teach wherein the screen layer is localized to a first area under the first field effect transistor and is outside of a second area under a second field effect transistor adjacent to the first field effect transistor, or a bottom surface layer of the layer above the screen layer in contact with a top surface of the layer below the screen layer in the second area.
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Izpura teaches (Fig. 1) a screen layer (2) wherein the screen layer is localized to a first area under the first field effect transistor (10, [0018]) and is outside of a second area under a second field effect transistor (11, [0018]) adjacent to the first field effect transistor. Izpura thus necessarily teaches that the bottom surface layer of the layer above the screen layer is in contact with the top surface of the layer below the screen layer in the second area. See Fig. 1.
Because Stoffels and Izpura are both directed toward HEMT devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels and Izpura to include wherein the screen layer is localized to a first area under the first field effect transistor and is outside of a second area under a second field effect transistor adjacent to the first field effect transistor in order to have regions with isolated devices with very good performances at high frequencies and other regions with very low excess noise devices protected (Izpura, [0018]).
Regarding claim 2, Stoffels in view of Izpura teaches (Stoffels, Fig. 2) the microelectronic device of claim 1, wherein the node (6, [0047])) is a source of the first field effect transistor ([0047]).
Regarding claim 4, Stoffels in view of Izpura teaches (Stoffels, Fig. 2) the microelectronic device, wherein the screen layer (10, [0054-0055]) includes a first conductivity type doped layer (10, [0054]) of III-N semiconductor material.
Regarding claim 5, Stoffels in view of Izpura teaches (Stoffels, Fig. 2) the microelectronic device of claim 1, wherein the screen layer includes a screen barrier layer (10, [0046]) of III-N semiconductor material on the lower buffer layer (2, [0046]), the screen barrier layer (10) having a higher band gap than the lower buffer layer (2) contacting the screen barrier layer [(0057]). Stoffels teaches that at the interface between two layers within the buffer layer, there can be a step in concentration, which can lead to the formation of a hole or electron gas (a 2DEG or 2DHG), and that one of these sublayers within the buffer layer is considered the screen barrier layer ([0057]). In order to form a 2DEG or 2DHG (Fig. 2, 11), there must be a bandgap differential between screen barrier layer (10) and lower buffer layer (2), defined by the step in concentration. Stoffels teaches wherein the bandgap of the screen barrier layer can be higher or lower than that of the buffer layer by preferential doping in order to create a 2DEG or 2DHG screen layer that shields the 2DEG of the FET from substrate bias, helping avoid depletion of the 2DEG of the FET ([0050]).
Regarding claim 6, Stoffels in view of Izpura teaches (Stoffels, Fig. 2) the microelectronic device of claim 5, wherein the screen barrier layer includes aluminum (10, [0056]).
Regarding claim 9, Stoffels teaches (Fig. 2) a method, comprising: forming a screen layer (10, [0050]) including gallium nitride ([0055]) over a lower buffer layer (2, [0046]) of III-N semiconductor material, the screen layer including free charge carriers ([0050]), an upper buffer layer (2U, [0046]) over the screen layer in the first area under the first field effect transistor (FET) and over the lower buffer layer in the second area under the second field effect transistor (8).
Izpura teaches (Fig. 1) a screen layer (2) wherein the screen layer is localized to a first area under the first field effect transistor (10, [0018]) and is outside of a second area under a second field effect transistor (11, [0018]) adjacent to the first field effect transistor. Izpura thus necessarily teaches that the bottom surface layer of the layer above the screen layer is in contact with the top surface of the layer below the screen layer in the second area. See Fig. 1.
Because Stoffels and Izpura are both directed toward HEMT devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels and Izpura to include wherein the screen layer is localized to a first area under the first field effect transistor and is outside of a second area under a second field effect transistor adjacent to the first field effect transistor in order to have regions with isolated devices with very good performances at high frequencies and other regions with very low excess noise devices protected (Izpura, [0018]).
Regarding claim 10, Stoffels in view of Izpura teaches (Stoffels, annotated Fig. 2 above) the method of claim 9, further including: forming the first field effect transistor (FET, 0043]) having III-N semiconductor material over the screen layer; and forming a contact (12, [0047]) electrically connected to the screen layer and to a node (6, [0046]) of the field effect transistor.
Regarding claim 11, Stoffels in view of Izpura teaches (Stoffels, annotated Fig. 2 above) the method of claim 9, wherein the lower buffer layer (2L, [0050]) is located over a substrate (1, [0044]).
Regarding claim 13, Stoffels in view of Izpura teaches (Stoffels, Fig. 2) the method of claim 9, wherein forming the screen layer (11, [0054-0055]) includes forming a first conductivity type doped layer (10, [0054]) of the gallium nitride ([0055]).
Regarding claim 17, Stoffels in view of Izpura teaches (Stoffels, Fig. 2) the method of claim 9, wherein forming the screen layer includes forming a screen barrier layer (10, [0046]) of III-N semiconductor material on the lower buffer layer (2, [0046]), the screen barrier layer (10) having a higher band gap than the lower buffer layer (2) contacting the screen barrier layer [(0057]). Stoffels teaches that at the interface between two layers within the buffer layer, there can be a step in concentration, which can lead to the formation of a hole or electron gas (a 2DEG or 2DHG), and that one of these sublayers within the buffer layer is considered the screen barrier layer ([0057]). In order to form a 2DEG or 2DHG (Fig. 2, 11), there must be a bandgap differential between screen barrier layer (10) and lower buffer layer (2), defined by the step in concentration. Stoffels teaches wherein the bandgap of the screen barrier layer can be higher or lower than that of the buffer layer by preferential doping in order to create a 2DEG or 2DHG screen layer that shields the 2DEG of the FET from substrate bias, helping avoid depletion of the 2DEG of the FET ([0050]).
Regarding claim 18, Stoffels in view of Izpura teaches (Stoffels, Fig. 2) the method of claim 17, wherein the screen barrier layer includes aluminum (10, [0056]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Stoffels in view of Izpura as applied to claim 1 above, and further in view of Lidow et al. (US PGPub 2012/0153300; herein known as Lidow).
Regarding claim 8, Stoffels in view of Izpura teaches (Stoffels, annotated Fig. 6 below) the microelectronic device of claim 1, wherein the first field effect transistor is a high side transistor (FET1, [0071]), and the second field effect transistor is a low side transistor (FET2, [0071]) of III-N semiconductor material in a half bridge configuration ([0071]).
Stoffels in view of Izpura does not explicitly show wherein a drain of the low side transistor is electrically connected to a source of the high side transistor, however, Stoffels in view of Izpura does teach that the high side and low side FETs are arranged in a half bridge configuration. A typical half bridge arrangement contains a source of a high side FET connected to a drain of a low side FET.
Lidow teaches (Fig. 12), wherein a drain (125, [0089]) of the low side transistor ([0090]) is electrically connected to a source (129, [0089]) of the high side transistor ([0090]).
Stoffels in view of Izpura teaches a high side transistor and low side transistor arranged to form a half-bridge device.
Lidow teaches two transistors arranged in a half-bridge configuration, wherein the source of one transistor is connected to the drain of the other transistor. Lidow further teaches that this connection exists to form a half-bridge circuit device.
One of ordinary skill in the art would have understood that the source and drain connection of Lidow could be substituted into the structure of Stoffels in view of Izpura for the predictable result of forming a half-bridge circuit device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the source-drain connection of Lidow for the source-drain of Stoffels in view of Izpura for the purpose of forming a half-bridge circuit device. See MPEP 2143(I)(b).
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Claims 14-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Stoffels in view of Izpura as applied to claim 1 above, and further in view of Tipirneni et al. (US Patent 8,759,879; herein known as Tipirneni).
Regarding claim 14, Stoffels in view of Izpura teaches (Stoffels, Fig. 2) the method of claim 13, wherein forming the first conductivity type doped layer (10, [0056]) includes adding dopants ([0058]) during a growth process ([0056]). Stoffels in view of Izpura does not explicitly teach an epitaxial growth process.
Tipirneni teaches (Fig. 3) forming the first conductivity type doped layer (326, [0030]) including adding dopants during an epitaxial growth process ([0030]).
Because Stoffels in view of Izpura and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels in view of Izpura and Tipirneni in order to form a blanket layer with uniform doping (Tipirneni, [0030]).
Regarding claim 15, Stoffels in view of Izpura and Tipirneni teaches (Stoffels, Fig. 2) the method of claim 13. Stoffels in view of Tipirneni further teaches wherein forming the first conductivity type doped layer (11) includes implanting dopants into the gallium nitride (Stoffels, [0055]) of the screen layer (Tipirneni, [[0030]).
Because Stoffels in view of Izpura and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Stoffels in view of Izpura and Tipirneni in order to achieve desired doping density ([0030]).
Regarding claim 16, Stoffels in view of Izpura and Tipirneni teaches the method of claim 15, and further teach further including forming an implant mask over the gallium nitride of the screen layer, exposing the gallium nitride in an area for the screen layer, and implanting the dopants into the gallium nitride (Stoffels, [0055]) where exposed by the implant mask (Tipirneni, [0030]).
Because Stoffels in view of Izpura and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Stoffels in view of Izpura and Tipirneni in order to selectively dope the surface of the device solely on the screen layer, and not on other coplanar layers ([0030]).
Regarding claim 19, Stoffels in view of Izpura teaches the method of claim 9, but does not explicitly teach further including patterning the screen layer ([0030]).
Tipirneni teaches further including patterning the screen layer ([0030]).
Because Stoffels in view of Izpura and Tipirneni are both directed toward methods of forming a screen layer in a III-N semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Stoffels in view of Izpura and Tipirneni in order to create a screen layer than selectively covers the buffer layer below it (Tipirneni, [0030]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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