DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Applicant’s amendments to claims 1 and 8 in the reply filed on 11 February 2026 are acknowledged. Claims 3, 4, 12, and 13 have been cancelled. Claim 6 was previously cancelled. Claims 5, 7, and 16-20 were previously withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-2, 8-11, and 14-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claims 1 and 8 - The words “...and including...” in the phrase “...and including a top dielectric layer positioned on top of the layer of metal and a bottom dielectric isolation layer located beneath a bottom channel...” leave the connection to the preceding limitation ambiguous. It is unclear whether the intent is to state the single continuous dielectric material includes a top dielectric layer positioned on top of the layer of metal and a bottom dielectric isolation layer located beneath a bottom channel, or the spacer body includes a top dielectric layer positioned on top of the layer of metal and a bottom dielectric isolation layer located beneath a bottom channel. The words “...and including...” will be replaced with --as well as-- for the purpose of examination.
Claim 2 is rejected due to its dependency on claim 1.
Claims 9-11 and 14-15 are rejected due to their dependency on claim 8.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8-9, and 11-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fulford et al (US 20240145595 A1, hereinafter “Fulford”).
Regarding Claim 1 – Fulford discloses a semiconductor device, comprising: a substrate (202 [0025]); a stack of nanosheets supported by the substrate (208 [0027]); a plurality of semiconductor channels (236 [0037]) in the stack of nanosheets, wherein the plurality of semiconductor channels includes a top channel (Top Channel 1 or 2 in annotated Fig. 27); a gate body (270 [0057] or 280 [0060]) coupled to each of the semiconductor channels including the top channel, wherein the gate body comprises a layer of metal (Top Metal Layer 1 or 2 in annotated Fig. 27) positioned on top of the top channel; and a spacer body comprising a single continuous dielectric material surrounding the stack of nanosheets (considered to be first and second dielectric structures, 212 and 214 [0032] and Figs. 27 and 28), as well as a top dielectric layer positioned on top of the layer of metal (considered to be cap layer 210 [0028]) and a bottom dielectric isolation layer located beneath a bottom channel (216 [0033] and Fig. 27), wherein a thickness (T1 in annotated Fig. 27) of the layer of metal above the top channel is based on a distance from a bottom surface of the top dielectric layer to a top surface of the top channel (T1 spans the distance between the underside of 210 to a top channel as shown in annotated Fig. 27).
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Regarding Claim 2 – Fulford discloses the semiconductor device of claim 1, wherein a distance (T2 in annotated Fig. 27) between the top channel and an underlying semiconductor channel (1st Bottom Channel in annotated Fig. 27) is spaced by the distance from the bottom surface of the top dielectric layer to the top surface of the top channel (T1 = T2, because both were determined by sacrificial layer 206 in Fig. 2 [0027]).
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Regarding Claim 8 – Fulford discloses a semiconductor device, comprising: a substrate (202 [0025]); a first fin field effect transistor (FET) (second transistor [0069]) on top of the substrate; a first stack of nanosheets ([0009]) in the first fin FET; a first top semiconductor channel (Top Channel 1 in annotated Fig. 27) in the first stack of nanosheets; a first bottom semiconductor channel (Bottom Channel 1 in annotated Fig. 27) in the first stack of nanosheets; a second fin FET (first transistor [0069]) on top of the substrate; a second stack of nanosheets ([0009]) in the second fin FET; a second top semiconductor channel (Top Channel 2 in annotated Fig. 27) in the second stack of nanosheets; a second bottom semiconductor channel (Bottom Channel 2 in annotated Fig. 27) in the second stack of nanosheets; a gate body (270 [0057] and 280 [0060]) coupled to the first top semiconductor channel, the second top semiconductor channel, the first bottom semiconductor channel, and the second bottom semiconductor channel, and including a layer of metal positioned on top of the first top semiconductor channel (Top Metal Layer 1 in annotated Fig. 27) and on top of the second top semiconductor channel (Top Metal Layer 2 in annotated Fig. 27); and a spacer body comprising a single continuous dielectric material surrounding the first nanosheet stack and the second nanosheet stack (considered to be first and second dielectric structures, 212 and 214 [0032]), as well as a top dielectric layer positioned on top of the layer of metal (considered to be cap layer 210 [0028]) and a bottom dielectric isolation layer located beneath a bottom channel (216 [0033] and Fig. 27), wherein a thickness of the layer of metal (Top Metal Layer 1 in Fig. 27) above the first top semiconductor channel is based on a distance (T1 in annotated Fig. 27) from a bottom surface of the top dielectric layer (underside of 210 in Fig. 27) to a top surface of either the first top semiconductor channel (Top Channel 1 in Fig. 27) or the second top semiconductor channel (Top Channel 2 in Fig. 27) (T1 spans underside of 210 to top channel as shown in Fig. 27).
Regarding Claim 9 – Fulford discloses the semiconductor device of claim 8, wherein the thickness of the layer of metal is uniform across the first fin FET and the second fin FET (Sacrificial layer 206 [0027] defines uniform metal spacing for all FETs as in Fig. 2).
Regarding Claim 11 – Fulford discloses the semiconductor device of claim 8, further comprising a first gate type material (gate dielectric 282 and gate electrode 284 configured for NMOS [0060]) for the first fin FET and a second gate type material (gate dielectric 272 and gate electrode 274 suitable for PMOS [0057]) for the second fin FET.
Regarding Claim 14 – Fulford discloses the semiconductor device of claim 8, wherein the first fin FET is a nFET (gate structure 280 forms NMOS [0060]) and the second fin FET is a pFET (gate structure 270 forms NMOS [0060]).
Regarding Claim 15 – Fulford discloses the semiconductor device of claim 8, wherein the first fin FET includes at least three semiconductor channels (Three channels each as in [0008] and Fig. 27).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being obvious over Fulford et al (US 20240145595 A1, hereinafter “Fulford”), in view of Huang et al (US 20230134379 A1, hereinafter “Huang”).
Regarding Claim 10 – Fulford discloses all the limitations of claim 8.
Fulford further discloses a layer of metal between the first top semiconductor channel (Top Channel 1 or 2 in annotated Fig. 27) and the first bottom semiconductor channel (Middle Channel 1 or 2 in annotated Fig. 27).
Fulford does not disclose said layer of metal has a same thickness as the layer of metal above the first top semiconductor channel.
However, Huang teaches said layer of metal (electrode portion of 228, Huang [0055] and Fig. 2I”) has a same thickness as the layer of metal above the first top semiconductor channel (based on 228 layers replacing 208 layers, which have equal thickness, Huang [0037]).
Just as Fulford, Huang relates to transistors formed with nanosheet channels. Huang teaches using an internal spacer structure that creates equal spacing above and below the channels to minimize parasitic capacitance and shorting between gate electrode and source/drain regions (Huang [0013-0014]). Therefore, it would have been obvious to one skilled in the art prior to the effective filing date of the instant application to consider making the gate metal thicknesses equal above and between the channels to achieve the expected result of minimizing gate to source/drain parasitic capacitance and reduce the probability of gate to source/drain shorting.
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Response to Arguments
The applicant submits that “the combination of Fulford and Huang does not teach or suggest a semiconductor device including, among the other claimed elements, a spacer body comprising a single continuous dielectric material surrounding the surrounding the first nanosheet stack and the second nanosheet stack and including a top dielectric layer positioned on top of the layer of metal and a bottom dielectric isolation layer located beneath a bottom channel”. However, as explained above, the semiconductor device of Fulford includes a spacer body comprising a single, continuous material, as well as a top dielectric layer positioned on top of the layer of metal and a bottom dielectric isolation layer located beneath a bottom channel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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