DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/12/2026 has been entered.
Response to Amendment
The Amendment filed on 01/23/2026 has been entered. Applicant's amendment has overcome the 112 (b) rejections to the Claim 34 previously set forth in the Final Office Action dated on 11/25/2025.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the "Amendment/Req. Reconsideration-After Final Reject" filed on 01/23/2026, have been fully considered, the arguments regarding claims 1, 12 and 30 of “wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad” are moot because do not apply to new ground of rejections with a new reference, US 20180226337 A1 to Liu, being used in the current rejection. The arguments are not persuasive, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim(s) 1-3, 5-6, 9,11 and 36-37 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Gao et al. (US 20190385966 A1, hereinafter Gao, of the record) in view of Liu et al. (US 20180226337 A1, hereinafter Liu).
Re: Independent Claim 1, Gao discloses a semiconductor device comprising:
a lower structure (104lower, 106lower a lower substrate 104 and a lower insulating layer 106 in [0043], Fig. 7-Annotated); and
an upper structure (104upper, 106upper an upper substrate 104 and an upper insulating layer 106 in [0043], Fig. 7-Annotated),
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Gao’s Figure 7-Annotated.
wherein the lower structure (104lower, 106lower) includes:
a first semiconductor substrate (104lower a lower substrate 104 comprising silicon in [0043], Fig.7-Annotated);
a first insulating layer (106lower a lower insulating layer 106 in [0043], Fig. 7-Annotated) on the first semiconductor substrate (104lower); and
a first pad (302lower a contact pad in [0057], Fig. 7-Annotated) including a portion that is in the first insulating layer (106lower),
wherein the upper structure (104upper, 106upper) includes:
a second semiconductor substrate (104upper an upper substrate 104 comprising silicon in [0043], Fig.7-Annotated);
a second insulating layer (106upper an upper insulating layer 106 in [0043], Fig.7-Annotated) on the second semiconductor substrate (104upper); and
a second pad (302upper a contact pad in [0057], Fig. 7-Annotated) including a portion that is in the second insulating layer (106upper),
wherein the first pad (302lower) and the second pad (302upper) are in contact with each other (Fig. 7), and the first insulating layer (106lower) and the second insulating layer (106upper) are in contact with each other (Fig. 7),
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Gao’s Figure 8-Annotated, with an additional upper structure for explanation.
wherein the first insulating layer (106lower) includes a first recess (lower-recess a recess in the 106lower, wherein additionally, the dielectric 106 around the metal pad 302 is shaped to allow room for the metal of the pad 302 to expand in [0057, 0059], Figs. 7-8-Annotated) connected (Fig. 7-Annotated) to the first pad (302lower),
wherein the second insulating layer (106upper) includes a second recess (upper-recess a recess in the 106upper in [0057, 0059], Figs. 7-8-Annotated) that is connected (Fig. 7-Annotated) to the second pad (302upper) and overlaps (Figs. 7-8-Annotated) the first recess (lower-recess), and
wherein the first recess (lower-recess) and the second recess (upper-recess) define a cavity (cavity formed by lower-recess and upper-recess Fig. 8-Annotated) that includes particles of a metallic material (the metallic material from 302lower and 302upper is expanded to the cavity in [0057,0059]) constituting the first (302lower) and second pads (302upper).
and wherein the cavity (cavity) comprises opposing edge portions that extend outward (Fig. 8-Annotated) from a widest point of the first and/or second pads (302lower-upper), the edge portions each having a tapered shape (Fig. 8-Annotated).
Gao does not expressly disclose wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad.
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Liu’s Figure 3F-Annotated
However, in the same semiconductor device field of endeavor, Liu discloses wherein the first (116a a metal layer in [0015], Fig. 3E-3F-Annotated) and second (116b a metal layer in [0015], Fig. 3E-3F-Annotated) pads are arranged such that a first surface of the first pad (116a, Fig. 3E-3F-Annotated) faces a first surface of the second pad (116b, Fig. 3E-3F-Annotated); wherein a second surface of the first pad (116a, Fig. 3E-3F-Annotated) is disposed opposite the first surface of the first pad (116a, Fig. 3E-3F-Annotated) and a width (Fig. 3F-Annotated) of the first pad (116a, Fig. 3E-3F-Annotated) increases (Fig. 3F-Annotated) from the second surface of the first pad (116a, Fig. 3E-3F-Annotated) to the first surface of the first pad (116a, Fig. 3E-3F-Annotated) such that the second surface of the first pad (116a, Fig. 3E-3F-Annotated) has a width that is less (Fig. 3F-Annotated) than a width of the first surface of the first pad (116a, Fig. 3E-3F-Annotated); a second surface of the second pad (116b, Fig. 3E-3F-Annotated) is disposed opposite the first surface of the second pad (116b, Fig. 3E-3F-Annotated) and a width of the second pad (116b, Fig. 3E-3F-Annotated) increases (Fig. 3F-Annotated) from the second surface of the second pad (116b, Fig. 3E-3F-Annotated) to the first surface of the second pad (116b, Fig. 3E-3F-Annotated) such that the second surface of the second pad (116b, Fig. 3E-3F-Annotated) has a width that is less (Fig. 3F-Annotated) than a width of the first surface of the second pad (116b, Fig. 3E-3F-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Liu’s feature of wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad to Gao’s device to reduce the cost processing of the wafer for improving the interconnection of the metal layers ([0003], Liu).
Regarding Claim 2, Gao modified by Liu discloses the semiconductor device of claim 1, wherein the first recess (lower-recess, Gao) extends around the first pad (302lower, Gao) in plan view (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat to allow room for material expansion in [0057], Gao), wherein the second recess (upper-recess, Gao) extends around the second pad (302upper, Gao) in plan view (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat, forming recess to allow room for material expansion in [0057] , Gao).
Regarding Claim 3, Gao modified by Liu discloses the semiconductor device of claim 1, wherein each of the first pad (302lower, Gao) and the second pad (302upper, Gao) has a circular shape or a quadrangular shape in plan view (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat to allow room for material expansion in [0057], Gao), and wherein each of the first recess (lower-recess, Gao) and the second recess has a circular ring shape or a quadrangular ring shape in plan view (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat, forming recess to allow room for material expansion in [0057] , Gao), the first recess (lower-recess, Gao) is larger (due to 302lower is etched to form the recess around the 302lower, the top view of the lower recess is larger than 302lower, Fig.7-Annotated, Gao) than the first pad (302lower, Gao) in plan view , and the second recess (upper-recess, Gao) is larger (due to 302upper is etched to form the recess around the 302upper, the top view of the upper recess is larger than 302upper, Fig.7-Annotated, Gao) than the second pad (302upper, Gao) in plan view.
Regarding Claim 4, Gao modified by Liu discloses the semiconductor device of claim 1, wherein the first pad (302lower, Gao) and the second pad (302upper, Gao) are stacked in a first direction (Fig. 7-Annotated, Gao),
Gao modified by Liu does not expressly disclose a widest width of the cavity in a second direction is from 0.1 µm to 5 µm, and the second direction is perpendicular to the first direction.
However, the Applicant has not presented persuasive evidence that the claimed
“widest width of the cavity in a second direction is from 0.1 µm to 5 µm, and the second direction is perpendicular to the first direction” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of the widest width of the cavity in a second direction). Also, the applicant has not shown that the claimed “difference of widest width of the cavity in a second direction” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Gao discloses “302 … is recessed a predetermined or predictable amount, the recess provides room for material expansion without delamination” [0053], therefore, the widest width of the cavity is a result effective variable. It has been held that is not inventive to discover the optimum widest width of the cavity in a second direction by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add widest width of the cavity in a second direction is from 0.1 µm to 5 µm to the rest of the claimed invention to allow more room for expansion of the metal, which can reduce or eliminate delamination that could occur otherwise when the metal expands ([0031], Gao).
Regarding Claim 5, Gao modified by Liu discloses the semiconductor device of claim 1, wherein the metallic material includes copper (Cu) (302lower and 302upper comprising copper expanded to first and the second recess in [0054], Gao), and wherein the first insulating layer (106lower, Gao) and the second insulating layer (106upper, Gao) include an oxide, nitride, or oxynitride (106lower and 106upper including oxide, nitride, oxynitride, oxycarbide, glasses in [0043], Gao) and include a material constituting (104lower and 104upper including silicon, germanium, glass, quartz, a dielectric surface in [0043] , Gao) the first (104lower, Gao) and second (104upper, Gao) semiconductor substrates.
Regarding Claim 6, Gao modified by Liu discloses the semiconductor device of claim 1, wherein an interface (108 a bonding surface between 106lower and 106upper in [0044], Figs.7-8-Annotated, Gao) between the first insulating layer (106lower, Gao) and the second insulating layer (106upper, Gao) includes: a first region (first region a region next to the cavity, Figs.7-8-Annotated, Gao) adjacent to the cavity (cavity, Figs.7-8-Annotated, Gao); and a second region (second region a region next to the first region, Figs.7-8-Annotated, Gao), wherein the first region (first region, Gao) is between the cavity and the second region (second region, Gao), and a concentration of the metallic material in the first region (first region, Gao) is less than a concentration (due the metal contact pads are planarized in [0034], metal particles from the metal contact pads are disposed in 108, having a first region close to the cavity and a second region far away of the cavity, then after the bonding/annealing process some metallic particles from the first region are moved into the cavity, resulting in, less metallic particles in the first region than of the second region, Figs.7-8-Annotated, Gao) of the metallic material in the second region
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(second region, Gao).
Gao’s Figure 8-Annotated.
Regarding Claim 9, Gao modified by Liu discloses the semiconductor device of claim 1, wherein a depth (a vertical line in the lower recess, Fig. 8-Annotated, Gao) of the first recess (lower-recess, Gao) and a depth (a vertical line in the upper recess, Fig. 8-Annotated, Gao) of the second recess (upper-recess, Gao) decrease or remain constant as a distance from the first pad or the second pad (302lower-upper) increases (including a recess 802 or other gap that provides room for metal expansion [0059], Gao).
Regarding Claim 11, Gao modified by Liu discloses the semiconductor device of claim 1, wherein the first pad (302lower, Gao) and the second pad (302upper, Gao) include the same material (302lower and 302upper including comprising copper in [0054], Gao) and collectively constitute a monolithic layer (the metal is heated during annealing, the metal from both bonding surfaces forms a unified conductive structure in [0010], as showed in Fig. 7(B), Gao).
Regarding Claim 36, Gao modified by Liu discloses the semiconductor device of claim 1, wherein the first recess (lower-recess, Gao) encloses the first pad (302lower, Gao) in plan view (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat to allow room for material expansion in [0057], Gao), and the second recess (upper-recess, Gao) encloses the second pad (302upper, Gao) in plan view (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat, forming recess to allow room for material expansion in [0057] , Gao).
Regarding Claim 37, Gao modified by Liu discloses the semiconductor device of claim 1, wherein an interface (108 a bonding surface between 106lower and 106upper in [0044], Fig.7-Annotated, Gao) between the first insulating layer (106lower, Gao) and the second insulating layer (106upper, Gao) is spaced apart (Figs.7-8Annotated, Gao) from the first (302lower, Gao) and second (302upper, Gao) pads.
Claims 12-14,18-20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (of the record) in view of Shao et al. (US 20200091039 A1, hereinafter Shao, of the record) and further in view of Liu.
Regarding Independent Claim 12, Gao teaches a semiconductor device comprising:
a lower structure (104lower, 106lower a lower substrate 104 and a lower insulating layer 106 in [0043], Fig. 7-Annotated) including a first substrate (104lower a lower substrate 104 in [0043], Fig.7-Annotated), a first insulating layer (106lower a lower insulating layer 106 in [0043], Fig. 7-Annotated), and a first pad (302lower a contact pad in [0057], Fig. 7-Annotated) that includes a metallic material (302lower comprising copper in [0054]), includes a portion (a bottom portion of 302lower is not in contact with 106lower, Fig.7-Annotated) not contacted by the first insulating layer (106lower);
an upper structure (104upper, 106upper an upper substrate 104 and an upper insulating layer 106 in [0043], Fig. 7-Annotated) including a second substrate (104upper an upper substrate 104 in [0043], Fig.7-Annotated), a second insulating layer (106upper an upper insulating layer 106 in [0043], Fig.7-Annotated), and a second pad (302upper a contact pad in [0057], Fig. 7-Annotated) that includes the metallic material (302upper comprising copper in [0054]), includes a portion (a bottom portion of 302upper is not in contact with 106upper, Fig.7-Annotated) not contacted by the second insulating layer (106upper), wherein the upper structure (104upper, 106upper) contacts (Fig. 7) the lower structure (104lower, 106lower); and
a cavity (cavity formed by lower-recess and upper-recess, Fig. 8-Annotated) that extends around (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat, forming recess to allow room for material expansion in [0057,0059]) the first pad (302lower) and the second pad (302upper) in plan view and is defined (Fig. 7-Annotated) by the first insulating layer (106lower) and the second insulating layer (106upper), wherein the cavity (cavity) comprises opposing edge portions that extend outward (Fig. 8-Annotated) from a widest point of the first and/or second pads, the edge portions each having a tapered shape (Fig. 8-Annotated),
wherein the second pad (302upper) and the first pad (302lower) contact each other (Fig. 7-Annotated), include the same material (302lower and 302upper comprising copper in [0054]) and collectively constitute a monolithic layer (the metal is heated during annealing, the metal from both bonding surfaces forms a unified conductive structure in [0010], as showed in Fig. 7(B)), and
wherein an interface (108) between the first insulating layer (106lower) and the second insulating layer (106upper) includes: a first region (first region a region next to the cavity, Fig.8-Annotated) extending around the cavity (cavity, Fig. 8-Annotated); and a second region (second region a region next to the first region, Fig.8-Annotated), wherein the first region (first region) is between (Fig.8-Annotated) the cavity (cavity, Fig. 8-Annotated) and the second region (second region), and a concentration of the metallic material in the first region (first region) is less than a concentration (due the metal contact pads are planarized in [0034], metal particles from the metal contact pads are disposed in 108, having a first region close to the cavity and a second region far away of the cavity, then after the bonding/annealing process some metallic particles from the first region are moved into the cavity, resulting in, less metallic particles in the first region than of the second region, Fig.8-Annotated) of the metallic material in the second region (second region).
Gao does not expressly disclose a first circuit pattern on the first substrate (104lower), a first insulating layer (106 lower) on the first circuit pattern and the first pad (302lower) is electrically connected to the first circuit pattern, a second circuit pattern on the second substrate (104upper), a second insulating layer (106upper) on the second circuit pattern and the second pad (302upper) is electrically connected to the second circuit pattern, wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad.
However, in the same semiconductor device field of endeavor, Shao discloses a first circuit pattern (103 a first device region including a transistor in [0017], Fig.1G-Annotated) on the first substrate (102 a first substrate in [0017], Fig.1G-Annotated), a first insulating layer (154 a first dielectric layer in [0018], Fig.1G-Annotated) on the first circuit pattern (103) and the first pad (152 a first metal layer made of copper in [0018, 0019], Fig.1G-Annotated) is electrically connected (152 bottom surface is in electrical contact with 103, Fig.1G) to the first circuit pattern (103), a second circuit pattern (203 a second device region including a transistor in [0034, 0087], Fig.1G-Annotated) on the second substrate (202 a second substrate in [0034], Fig.1G-Annotated), a second insulating layer (254 a dielectric layer in [0034], Fig.1G-Annotated) on the second circuit pattern (203) and the second pad (252 a second metal layer made of copper in [0034, 0035], Fig.1G-Annotated) is electrically connected (252 bottom surface is in electrical contact with 203, Fig.1G) to the second circuit pattern (203).
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Shao’s Figure 1G-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Shao’s feature a first circuit pattern on the first substrate, a first insulating layer on the first circuit pattern and the first pad is electrically connected to the first circuit pattern, a second circuit pattern on the second substrate, a second insulating layer on the second circuit pattern and the second pad is electrically connected to the second circuit pattern to Gao’s device to provide electrical devices.
Still, Gao modified by Shao does not expressly disclose wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad.
However, in the same semiconductor device field of endeavor, Liu discloses wherein the first (116a a metal layer in [0015], Fig. 3E-3F-Annotated) and second (116b a metal layer in [0015], Fig. 3E-3F-Annotated) pads are arranged such that a first surface of the first pad (116a, Fig. 3E-3F-Annotated) faces a first surface of the second pad (116b, Fig. 3E-3F-Annotated); wherein a second surface of the first pad (116a, Fig. 3E-3F-Annotated) is disposed opposite the first surface of the first pad (116a, Fig. 3E-3F-Annotated) and a width (Fig. 3F-Annotated) of the first pad (116a, Fig. 3E-3F-Annotated) increases (Fig. 3F-Annotated) from the second surface of the first pad (116a, Fig. 3E-3F-Annotated) to the first surface of the first pad (116a, Fig. 3E-3F-Annotated) such that the second surface of the first pad (116a, Fig. 3E-3F-Annotated) has a width that is less (Fig. 3F-Annotated) than a width of the first surface of the first pad (116a, Fig. 3E-3F-Annotated); a second surface of the second pad (116b, Fig. 3E-3F-Annotated) is disposed opposite the first surface of the second pad (116b, Fig. 3E-3F-Annotated) and a width of the second pad (116b, Fig. 3E-3F-Annotated) increases (Fig. 3F-Annotated) from the second surface of the second pad (116b, Fig. 3E-3F-Annotated) to the first surface of the second pad (116b, Fig. 3E-3F-Annotated) such that the second surface of the second pad (116b, Fig. 3E-3F-Annotated) has a width that is less (Fig. 3F-Annotated) than a width of the first surface of the second pad (116b, Fig. 3E-3F-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Liu’s feature of wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad to the combination of Gao and Shao to reduce the cost processing of the wafer for improving the interconnection of the metal layers ([0003], Liu).
Regarding Claim 13, Gao modified by Shao and Liu discloses the semiconductor device of claim 12, wherein particles of the metallic material constituting the first (302lower, Gao) and second (302upper, Gao) pads are in the cavity (the metallic material from 302lower and 302upper is expanded to the cavity in [0057], Gao).
Regarding Claim 14, Gao modified by Shao and Liu discloses the semiconductor device of claim 13, wherein the particles of the metallic material are adjacent to a farthest portion of the cavity (the metallic material from 302lower and 302upper is expanded to the cavity in [0057], Gao) from the first pad (302lower, Gao) and the second pad (302upper, Gao).
Regarding Claim 18, Gao modified by Shao and Liu discloses the semiconductor device of claim 12, wherein each of the first pad (302lower, Gao) and the second pad (302upper, Gao) has a circular shape or a quadrangular shape in plan view (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat to allow room for material expansion in [0057], Gao), and wherein the cavity has a circular ring shape or a quadrangular ring shape in plan view (the top surface of the pad 302 formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat forming a cavity to allow room for material expansion in [0057], Gao), and the cavity (cavity, Fig. 8-Annotated, Gao) is larger (due to 302lower-upper are etched to form the recess around the 302upper-lower, then the cavity formed by these two recess in the top view is larger than 302upper and 302lower, [0059], Fig.8-Annotated, Gao) than the first (302lower, Gao) and second (302upper, Gao) pads in plan view.
Regarding Claim 19, Gao modified by Shao and Liu discloses the semiconductor device of claim 12, wherein the lower structure (104lower, 106lower, Gao) and the upper structure (104upper, 106upper, Gao) are stacked in a vertical direction (Fig.7-Annotated, Gao),
Gao modified by Shao and Liu does not expressly disclose a widest width of the cavity in a horizontal direction is from 0.1 µm to 5 µm.
However, the Applicant has not presented persuasive evidence that the claimed
“widest width of the cavity in a horizontal direction is from 0.1 µm to 5 µm is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of the widest width of the cavity in a horizontal direction). Also, the applicant has not shown that the claimed “difference of widest width of the cavity in a horizontal direction” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Gao discloses “302 … is recessed a predetermined or predictable amount, the recess provides room for material expansion without delamination” [0053], therefore, the widest width of the cavity is a result effective variable. It has been held that is not inventive to discover the optimum widest width of the cavity in a horizontal direction by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a widest width of the cavity in a horizontal direction from 0.1 µm to 5 µm to the rest of the claimed invention to allow more room for expansion of the metal, which can reduce or eliminate delamination that could occur otherwise when the metal expands ([0031], Gao).
Regarding Claim 20, Gao modified by Shao and Liu discloses the semiconductor device of claim 12, wherein the metallic material includes copper (Cu) (302lower and 302upper comprising copper expanded to first and the second recess in [0054], Gao), and wherein the first insulating layer (106lower, Gao) and the second insulating layer (106upper, Gao) include an oxide, nitride, or oxynitride (106lower and 106upper including oxide, nitride, oxynitride, oxycarbide, glasses in [0043], Gao) and include a material constituting (104lower and 104upper including silicon, germanium, glass, quartz, a dielectric surface in [0043], Gao) the first (104lower, Gao) and second (104upper, Gao) substrates.
Regarding Claim 22, Gao modified by Shao and Liu discloses the semiconductor device of claim 12, wherein the lower structure (104lower, 106lower, Gao) and the upper structure (104upper, 106upper, Gao) are stacked in a vertical direction (Fig.7-Annotated, Gao), and a width of the cavity (cavity, Fig. 8-Annotated) in a horizontal direction decreases or remains constant as a distance from the first pad or the second pad (302lower-upper, Gao) increases (including a recess 802 or other gap that provides room for metal expansion [0059], Gao).
Claims 30 and 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over Hou et al. (US 20220093555 A1, hereinafter Hou, of the record) in view of Gao (of the record) and further in view of Liu.
Re: Independent Claim 30, Hou discloses a semiconductor device comprising:
a substrate (908 first substrate in [0229], Fig. 11C);
a substrate pad (988 first bonding pad in [0226], Fig. 11C) on an upper surface of the substrate (908);
a conductive pattern (10, 488,980 semiconductor channel layer 10, through-memory-level via structure 488, first metal interconnect structures 980 in [0117-0118], Fig. 11C) on the upper surface of the substrate (908) and connected to a lower surface of the substrate pad (988);
a first insulating layer (65, 960, 984 dielectric material portions 65, first interconnect-level dielectric material layer 960, first pad-level dielectric layer 984 in [0117-0118, 0133-0134, 0228], Fig. 11C) surrounding the substrate pad (988) on the substrate (908), wherein the conductive pattern (10, 488,980) is in the first insulating layer (65, 960, 984P-D); and
a semiconductor chip (700-chip a portion of 700 in [0201], Fig. 11C-Annotated) on the upper surface of the substrate (908), wherein the semiconductor chip (700-chip) includes:
a semiconductor substrate (708 a second substrate in [0201], Fig. 11C);
a wiring layer (700-w wiring pattern in a portion of 700 in [0201], Fig. 11C-Annotated) that is on a lower surface of the semiconductor substrate (708) and includes a wiring pattern (780, 778 second metal interconnect structures 780, second pad base portions 778 in [0201], Fig. 11C-Annotated);
a bonding pad (788 second pad pillar portion in [0207], Fig. 11C) connected to a lower surface of the wiring pattern (780, 778);
a second insulating layer (760, 784 second interconnect-level dielectric material layers 760, second pad-level dielectric layer 784 in [0209, 0133-0134], Fig. 11C) surrounding the bonding pad (788) on the lower surface of the wiring pattern (780, 778),
wherein the bonding pad (788) contacts the substrate pad (988),
Hou does not expressly disclose wherein the first insulating layer includes a first region and a second region, the first region extends around the substrate pad and is between the substrate pad and the second region, wherein the first region of the first insulating layer is spaced apart from the second insulating layer, and the second region of the first insulating layer is in contact with the second insulating layer, wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad and wherein particles of a metallic material that constitutes the substrate pad and the bonding pad are disposed between the first region of the first insulating layer and the second insulating layer.
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Gao’s Figure 7-Annotated.
However, in the same semiconductor device field of endeavor, Gao discloses wherein the first insulating layer (106lower a lower insulating layer 106 in [0043], Fig. 7-Annotated) includes a first region (first region a region including the cavity, Fig.7-Annotated) and a second region (second region a region next to the first region, Fig.7-Annotated), the first region extends around the substrate pad (302lower a contact pad made of copper in [0054,0057], Fig. 7-Annotated) and is between the substrate pad (302lower) and the second region (second region), wherein the first region (first region) of the first insulating layer (106lower) is spaced apart from the second insulating layer (106upper an upper insulating layer 106 in [0043], Fig.7-Annotated), and the second region (second region) of the first insulating layer (106lower) is in contact with the second insulating layer (106upper), and wherein particles of a metallic material that constitutes the substrate pad (302lower) and the bonding pad (302upper a contact pad made of copper in [0054,0057], Fig. 7-Annotated) are disposed between the first region (first region) of the first insulating layer (106lower) and the second insulating layer (106upper).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gao’s feature wherein the first insulating layer includes a first region and a second region, the first region extends around the substrate pad and is between the substrate pad and the second region, wherein the first region of the first insulating layer is spaced apart from the second insulating layer, and the second region of the first insulating layer is in contact with the second insulating layer, and wherein particles of a metallic material that constitutes the substrate pad and the bonding pad are disposed between the first region of the first insulating layer and the second insulating layer to Hou’s device to provide a desired recess depth (to accommodate a predicted metal expansion) ([0057], Gao).
Still, Hou modified by Gao does not expressly disclose wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad.
However, in the same semiconductor device field of endeavor, Liu discloses wherein the first (116a a metal layer in [0015], Fig. 3E-3F-Annotated) and second (116b a metal layer in [0015], Fig. 3E-3F-Annotated) pads are arranged such that a first surface of the first pad (116a, Fig. 3E-3F-Annotated) faces a first surface of the second pad (116b, Fig. 3E-3F-Annotated); wherein a second surface of the first pad (116a, Fig. 3E-3F-Annotated) is disposed opposite the first surface of the first pad (116a, Fig. 3E-3F-Annotated) and a width (Fig. 3F-Annotated) of the first pad (116a, Fig. 3E-3F-Annotated) increases (Fig. 3F-Annotated) from the second surface of the first pad (116a, Fig. 3E-3F-Annotated) to the first surface of the first pad (116a, Fig. 3E-3F-Annotated) such that the second surface of the first pad (116a, Fig. 3E-3F-Annotated) has a width that is less (Fig. 3F-Annotated) than a width of the first surface of the first pad (116a, Fig. 3E-3F-Annotated); a second surface of the second pad (116b, Fig. 3E-3F-Annotated) is disposed opposite the first surface of the second pad (116b, Fig. 3E-3F-Annotated) and a width of the second pad (116b, Fig. 3E-3F-Annotated) increases (Fig. 3F-Annotated) from the second surface of the second pad (116b, Fig. 3E-3F-Annotated) to the first surface of the second pad (116b, Fig. 3E-3F-Annotated) such that the second surface of the second pad (116b, Fig. 3E-3F-Annotated) has a width that is less (Fig. 3F-Annotated) than a width of the first surface of the second pad (116b, Fig. 3E-3F-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Liu’s feature of wherein the first and second pads are arranged such that a first surface of the first pad faces a first surface of the second pad; wherein a second surface of the first pad is disposed opposite the first surface of the first pad and a width of the first pad increases from the second surface of the first pad to the first surface of the first pad such that the second surface of the first pad has a width that is less than a width of the first surface of the first pad; a second surface of the second pad is disposed opposite the first surface of the second pad and a width of the second pad increases from the second surface of the second pad to the first surface of the second pad such that the second surface of the second pad has a width that is less than a width of the first surface of the second pad to the combination of Hou and Gao to reduce the cost processing of the wafer for improving the interconnection of the metal layers ([0003], Liu).
Regarding Claim 34, Hou modified by Gao and Liu discloses the semiconductor device of claim 30,
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Hou modified by Gao and Liu does not expressly disclose wherein a distance between the first region of the first insulating layer and the second insulating layer decreases or remains constant as a distance from the substrate pad increases.
Gao’s Figure 8-Annotated.
However, in the same semiconductor device field of endeavor, Gao discloses wherein a distance (distance a vertical line, Fig. 8-Annotated) between the first region (first region) of the first insulating layer (106lower) and the second insulating layer (106upper) decreases or remains constant as a distance from the substrate pad (302lower) increases (including a recess 802 or other gap that provides room for metal expansion [0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gao’s feature wherein a distance between the first region of the first insulating layer and the second insulating layer decreases or remains constant as a distance from the substrate pad increases to Hou’s device to provide a desired recess depth (to accommodate a predicted metal expansion) ([0057], Gao).
Regarding Claim 35, Hou modified by Gao and Liu discloses the semiconductor device of claim 30, wherein the substrate pad (302lower, Gao) is a monolithic layer (302lower made of copper and after the metal is bonding with other pad forms a unified conductive structure in [0010], as showed in Fig. 7(B), Gao).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Liao et al. (US 12131951 B2) teaches “SEMICONDUCTOR PACKAGING METHOD AND SEMICONDUCTOR STRUCTURE”. This document is related to a semiconductor packaging method and a semiconductor structure. The semiconductor packaging method includes: providing a substrate; forming a metal pad on the substrate, where there is a gap between a sidewall of the metal pad and the substrate; and connecting multiple metal pads on substrates to each other.
Yu et al. (US 20210407942 A1) teaches “PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF”. This document is related to a semiconductor device including a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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