Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/26/2026 has been entered.
Response to Amendment
The amendment filed 1/26/2026 has been entered. Claims 1-5 and 7-22 remain pending.
Response to Arguments
Applicant's arguments with respect to Claim 1 have been fully considered but they are not persuasive.
Applicant mainly argues that neither Jones or Viswanathan disclose every feature of the amended Claim 1. However, Examiner is relying on the combination of references. Specifically, Examiner is arguing that a person of ordinary skill in the art would find Applicant’s invention obvious in light of both Jones and Viswanathan (see also MPEP 2145 (IV)). Thus, Claim 1 remains rejected as obvious in light of the teachings of both references. See Claim Rejections below for more information.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 20, Applicant states in part “…is less than a distance between the first side of the first power transistor die and a side of the first thermal dissipation structure that extends between the first and second surfaces of the first thermal dissipation structure.” Examiner is unsure as to what this means. As far as Examiner can determine, the only disclosure pertaining to distance are in Paras. [0048] and [0082], which define “close proximity” to mean that “a physical distance between a side of a power transistor die and aside of a ground terminal is less than half the width of the die to which the ground terminal is adjacent.” Alternatively, close proximity could mean “…an electrical length…less than lambda/5…or less than lambda/16”. For the purposes of this examination, Examiner is assuming that applicant means that the distance between the first side of the first power transistor die and the first interior ground terminal is less than lambda/16 (making it an extremely short ground path).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over US20220208670A1 (Jones) in view of US20160150632A1 (Viswanathan).
Regarding Claim 1, Jones discloses an amplifier module (Figs. 2, 3, and 4A, Para. [0036]) comprising, a module substrate (Fig. 3, el. 210, Para. [0037]) with a mounting surface (Fig. 3, el. 209, Para. [0037]), a first thermal dissipation structure (Figs. 3, el. 316, Para. [0044]) extending through the module substrate 210 (Para. [0044]), wherein the first thermal dissipation structure 316 has a first surface (Fig. 3, el. 317, Para. [0044]) and a second surface (Fig. 3, el. 318, Para. [0044]), wherein the first surface 317 is exposed at the mounting surface 209 of the module substrate 210 (Para. [0044]), a first power transistor die (Figs. 3 and 4A, el. 234, Para. [0044]) with a first ground contact (Fig. 4A, el. 434, Para. [0064]), wherein the first ground contact 434 is coupled to the first surface 317 of the first thermal dissipation structure 316 (Figs. 3 and 4A, Para. [0054]), encapsulant material (Fig. 3, el. 380, Para. [0037]) covering the mounting surface 209 of the module substrate 210 and the first power transistor die 234 (Fig. 3, Para. [0037]), wherein a surface (Fig. 3, el. 382, Para. [0037]) of the encapsulant material 380 defines the contact surface 382 of the amplifier module 200 (Para. [0038]), and a first interior ground terminal (Figs. 3 and 4A, el. 244, Para. [0063]) embedded within the encapsulant material 380 (Para. [0037]), wherein the first interior ground terminal 244 has a proximal end (Figs. 3 and 4A, not numbered, Para. [0067]) connected to the first thermal dissipation structure 316 (Para. [0064]) directly adjacent to a first side of the first power transistor die (Fig. 4A, Para. [0064]) with only a portion of the encapsulant material and no other circuitry present between the first side of the first power transistor die and the first interior ground terminal (Fig. 4A), and a distal end (Figs. 3 and 4A, not numbered, Para. [0067]) exposed at the contact surface 382 (Para. [0067]), and wherein the first interior ground terminal 244 is electrically coupled to the first ground contact 434 of the first power transistor die 234 through a first conductive path through thermal dissipation structure 316 (Fig. 4A, Para. [0064]).
Jones does not disclose that the first interior ground terminal has a proximal end directly connected to the first thermal dissipation structure.
Viswanathan discloses a system (Fig. 5, el. 500, Para. [0049]) with a thermal dissipation structure (Fig. 5, el. 522, Para. [0049] – note that although this is referred to as a substrate, it can be a thermal dissipation structure, similar to Fig. 3, el. 322, Para. [0039]), an interior terminal (Fig. 5, el. 563, Para. Para. [0050]) that can serve as a ground terminal (in Fig. 5, conductive pad 512 can be grounded, and thus internal terminal 563 will be grounded as well), wherein the interior terminal has a proximal end connected to the heat dissipation structure (Fig. 5, Para. [[0050) and a distal end exposed at a contact surface (Fig. 5, Para. [0050]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to attach the ground terminal of Jones directly to the heat dissipation structure (as in Viswanathan). One benefit would be to provide a lower inductance ground path for high frequency signals, since the ground terminal would be directly connected to a large heat dissipation structure, and so the signal would not have to travel through narrow conductive structures.
Regarding Claim 2, Jones in view of Viswanathan discloses the amplifier module 200 of claim 1, wherein the first thermal dissipation structure 316 includes a metallic coin embedded in the module substrate 210 (Para. [0044]).
Regarding Claim 3, Jones in view of Viswanathan discloses the amplifier module 200 of claim 1, wherein the first interior ground terminal 244 comprises a conductive pillar (Para. [0067]).
Regarding Claim 4, Jones in view of Viswanathan discloses the amplifier module 200 of claim 1, further comprising: an interposer terminal (Fig. 4B, el. 491, Para. [0071]) that includes a dielectric body (Fig. 4B, el. 492, Para. [0071]) with a top surface (Fig. 4B, el. 493, Para. [0071]) and a bottom surface (Fig. 4B, el. 494, Para. [0071]), and a conductive via (Fig. 4B, el. 495, Para. [0071]) extending between the top 493 and bottom 494 surfaces of the dielectric body 492 (Fig. 4B, Para. [0071]), wherein the conductive via 495 corresponds to the first interior ground terminal 244’ (Paras. [0070] and [0071], 244’ corresponds to 244).
Regarding Claim 5, Jones in view of Viswanathan discloses the amplifier module 200 of claim 4, wherein the first interposer terminal 244’ further comprises: a first conductive pad (Fig. 4B, el. 496, Para. [0071]) on the top surface 493 of the dielectric body 492 (Para. [0071]) and connected to a first end of the conductive via 495 (Para. [0071]), wherein the first conductive pad 496 corresponds to the distal end of the first interior ground terminal 244’ (the first conductive pad 496 is away from the substrate 210); and a second conductive pad (Fig. 4B, el. 497, Para. [0071]) on the bottom surface 494 of the dielectric body 492 and connected to a second end of the conductive via 495 (Para. [0071]), wherein the second conductive pad 497 corresponds to the proximal end of the first interior ground terminal 244’ (the second conductive pad 497 is on the substrate 210).
Regarding Claim 8, Jones in view of Viswanathan discloses the amplifier module 200 of claim 6, further comprising: a second interior ground terminal (Fig. 4A, el. 243, Para. [0063]) connected to the first thermal dissipation structure 316 in close proximity to a second side of the first power transistor die 234 (Fig. 4A, Para. [0064]).
Regarding Claim 9, Jones in view of Viswanathan discloses the amplifier module 200 of claim 1, further comprising: a second thermal dissipation structure extending through the module substrate, wherein the second thermal dissipation structure has a first surface and a second surface, wherein the first surface is exposed at the mounting surface of the module substrate (see Para. [0056], which describes a second thermal dissipation structure that has the same characteristics as the first thermal dissipation structure 316); a second power transistor die (Fig. 2, el. 254, Para. [0057]) with a second ground contact (Para. [0057]), wherein the second ground contact is coupled to the first surface of the second thermal dissipation structure (see Fig. 4A, which first ground contact 434 coupled to the first thermal dissipation structure; since the second transistor die, second ground contact, etc. is analogous to the first transistor die, first ground contact, etc., it will have the same configuration) and a second interior ground terminal (Fig. 2, el. 247, Para. [0066]) embedded within the encapsulant material (Para. [0061]), wherein the second interior ground terminal 247 has a proximal end connected to the second thermal dissipation structure (Para. [0067], which discloses that the proximal end of second interior ground terminal 247 is connected to a terminal pad, which in turn is connected to the second thermal dissipation structure, just like the first interior ground terminal 244) and a distal end exposed at the contact surface (Para. [0067]), and wherein the second interior ground terminal 247 is electrically coupled to the second ground contact of the second power transistor die through the second thermal dissipation structure (Para. [0056]).
Regarding Claim 10, Jones in view of Viswanathan discloses the amplifier module of claim 9, wherein: the first power transistor die is a carrier amplifier die of a Doherty power amplifier (el. 232, Para. [0045]); the second power transistor die is a peaking amplifier die of a Doherty power amplifier (el. 252, Para. [0055]); and the amplifier module further includes a phase delay and impedance inversion element electrically connected between outputs of the first and second power transistor dies (el. 270, Para. [0058]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan.
Regarding Claim 7, Jones in view of Viswanathan discloses the amplifier module 200 of claim 1, wherein a distance between the first power transistor die 234 and the first interior ground terminal 244 is less than a width of the first power transistor die 234 (Para. [0064]).
Jones in view of Viswanathan does not disclose that the distance is less than half a width of the first power transistor die.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to move the first interior ground terminal and position it such that its distance from the first power transistor die is less than half a width of the first power transistor die. Doing so would be the result of routine optimization (see MPEP 2144.05(II)(B)). As noted in Jones, the ground terminal 244 may be positioned at additional or different locations to minimize or eliminate the RF return current spreading across the module substrate (Para. [0064]), so a person of ordinary skill in the art would be motivated to experiment with the distance. In particular, they would have been motivated to move it closer, since this would reduce the inductance in the ground path. Further, by moving it from a distance of less than a width of the die to less than half a width of the die, a person of ordinary skill in the art would have had a reasonable expectation of success to minimize the RF return current, since the path length would be reduced.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan and US20210328551A1 (Maalouf).
Regarding Claim 19, Jones in view of Viswanathan discloses the amplifier module of claim 1.
Jones in view of Viswanathan does not disclose peripheral ground terminal embedded within the encapsulant material, wherein the peripheral ground terminal has a proximal end directly connected to the mounting surface of the module substrate, and a distal end exposed at the contact surface, and wherein the peripheral ground terminal is electrically coupled to the first ground contact of the first power transistor die through a second conductive path through the first thermal dissipation structure and through a ground layer within the module substrate that contacts the first thermal dissipation structure.
Maalouf discloses an amplifier module (Fig. 1, el. 110, Para. [0017]) comprising a heat dissipation structure (Fig. 1, el. 610, Para. [0018]), a power transistor die (Fig. 1, el. 310, Para. [0018]), and a peripheral ground terminal (Fig. 1, el. 620, Para. [0023]) that has a distal end exposed at the contact surface (Fig. 7).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add a peripheral ground terminal, similar to Maalouf, to the amplifier module of Jones in view of Viswanathan. Doing so would have the benefit of providing better grounding, as well as facilitating connection of the module to another substrate (as in Maalouf, Fig. 10).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan.
Regarding Claim 20, Jones in view of Viswanathan discloses the amplifier module 200 of claim 1, wherein a distance between the first power transistor die 234 and the first interior ground terminal 244 is less than a width of the first power transistor die 234 (Para. [0064]).
Jones in view of Viswanathan does not disclose that the distance between the first side of the first power transistor die and the first interior ground terminal is less than a distance between the first side of the first power transistor die and a side of the first thermal dissipation structure that extends between the first and second surfaces of the first thermal dissipation structure.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to move the first interior ground terminal and position it such that its distance from the first power transistor die is extremely short (see claim interpretation under Claim Rejections – 112). Doing so would be the result of routine optimization (see MPEP 2144.05(II)(B)). As noted in Jones, the ground terminal 244 may be positioned at additional or different locations to minimize or eliminate the RF return current spreading across the module substrate (Para. [0064]), so a person of ordinary skill in the art would be motivated to experiment with the distance. In particular, they would have been motivated to move it closer, since this would reduce the inductance in the ground path. Further, by moving it extremely close to a first side of the die, a person of ordinary skill in the art would have had a reasonable expectation of success to minimize the RF return current, since the path length would be reduced.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan.
Regarding Claim 11, Jones discloses an amplifier system (Fig. 6, el. 600, Para. [0076]) comprising a system substrate (Fig. 6, el. 610, Para. [0077]) with a mounting surface (Fig. 6, el. 609, Para. [0076]), a first signal conducting layer (Fig. 6, el. 601, Para. [0079]), a first ground layer (Fig. 6, el. 602, Para. [0080]), and a ground pad (Fig. 6, el. 641, Para. [0080]) at the mounting surface 609 (Para. [0081]), wherein the ground pad 641 is electrically coupled to the first ground layer 602 (Para. [0084]); and an amplifier module (Fig. 6, el. 200, Para. [0076]) with a contact surface (Fig. 6, el. 382, Para. [0081]) and a heat sink attachment surface (Fig. 6, el. 211, Para. [0082]), wherein the amplifier module 200 is coupled to the system substrate 610 with the mounting surface 609 of the system substrate 610 facing the contact surface 382 of the amplifier module 200 (Fig. 6, Para. [0081]), and wherein the amplifier module 200 further includes a module substrate (Figs. 3 and 6, el. 210, Para. [0037]) with a mounting surface (Figs. 3 and 6, el. 209, Para. [0037]), a first thermal dissipation structure (Figs. 3 and 6, el. 316, Para. [0044]) extending through the module substrate 210 (Para. [0044]), wherein the first thermal dissipation structure 316 has a first surface (Fig. 3, el. 317, Para. [0044]) and a second surface (Fig. 3, el. 318, Para. [0044]), wherein the first surface 317 is exposed at the mounting surface 209 of the module substrate 210 (Para. [0044]), a first power transistor die (Figs. 3, 4A and 6, el. 234, Para. [0044]) with a first ground contact (Fig. 4A, el. 434, Para. [0064]), wherein the first ground contact 434 is coupled to the first surface 317 of the first thermal dissipation structure 316 (Figs. 3 and 4A, Para. [0054]), encapsulant material (Figs. 3 and 6, el. 380, Para. [0037]) covering the mounting surface 209 of the module substrate 210 and the first power transistor die 234 (Figs. 3 and 6, Para. [0037]), wherein a surface (Fig. 3, el. 382, Para. [0037]) of the encapsulant material 380 defines the contact surface 382 of the amplifier module 200 (Para. [0038]), and a first interior ground terminal (Figs. 3, 4A and 6, el. 244, Para. [0063]) embedded within the encapsulant material 380 (Para. [0037]), wherein the first interior ground terminal 244 has a proximal end (Figs. 3 and 4A, not numbered, Para. [0067]) connected to the first thermal dissipation structure 316 (Para. [0064]) ]) directly adjacent to a first side of the first power transistor die (Fig. 4A, Para. [0064]) with only a portion of the encapsulant material and no other circuitry present between the first side of the first power transistor die and the first interior ground terminal (Fig. 4A), and a distal end (Figs. 3 and 4A, not numbered, Para. [0067]) exposed at the contact surface 382 (Para. [0067]), and wherein the first interior ground terminal 244 is electrically coupled to the first ground contact 434 of the first power transistor die 234 through a first conductive path through the thermal dissipation structure 316 (Fig. 4A, Para. [0064]).
Jones does not disclose that the first interior ground terminal has a proximal end directly connected to the first thermal dissipation structure.
Viswanathan discloses a system (Fig. 5, el. 500, Para. [0049]) with a thermal dissipation structure (Fig. 5, el. 522, Para. [0049] – note that although this is referred to as a substrate, it can be a thermal dissipation structure, similar to Fig. 3, el. 322, Para. [0039]), an interior terminal (Fig. 5, el. 563, Para. Para. [0050]) that can serve as a ground terminal (in Fig. 5, conductive pad 512 can be grounded, and thus internal terminal 563 will be grounded as well), wherein the interior terminal has a proximal end connected to the heat dissipation structure (Fig. 5, Para. [[0050) and a distal end exposed at a contact surface (Fig. 5, Para. [0050]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to attach the ground terminal of Jones directly to the heat dissipation structure (as in Viswanathan). One benefit would be to provide a lower inductance ground path for high frequency signals, since the ground terminal would be directly connected to a large heat dissipation structure, and so the signal would not have to travel through narrow conductive structures.
Regarding Claim 12, Jones in view of Viswanathan discloses the amplifier system 600 of claim 11, wherein the distal end of the interior ground terminal 244 is coupled to the ground pad 641 of the system substrate 610 (Para. [0084]).
Regarding Claim 13, Jones in view of Viswanathan discloses the amplifier system 600 of claim 11, further comprising: a heat sink (Fig. 6, el. 616, Para. [0082]) coupled to the heat sink attachment surface 211 (Para. [0082]).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan.
Regarding Claim 14, Jones in view of Viswanathan discloses the amplifier system 600 of claim 11, wherein a distance between the first side of the first power transistor die 234 and the first interior ground terminal 244 is less than a width of the first power transistor die 234 (Para. [0064]).
Jones in view of Viswanathan does not disclose that the distance is less than half a width of the first power transistor die.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to move the first interior ground terminal and position it such that its distance from the first power transistor die is less than half a width of the first power transistor die. Doing so would be the result of routine optimization (see MPEP 2144.05(II)(B)). As noted in Jones, the ground terminal 244 may be positioned at additional or different locations to minimize or eliminate the RF return current spreading across the module substrate (Para. [0064]), so a person of ordinary skill in the art would be motivated to experiment with the distance. In particular, they would have been motivated to move it closer, since this would reduce the inductance in the ground path. Further, by moving it from a distance of less than a width of the die to less than half a width of the die, a person of ordinary skill in the art would have had a reasonable expectation of success to minimize the RF return current, since the path length would be reduced.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan and Maalouf.
Regarding Claim 21, Jones in view of Viswanathan discloses the amplifier module of claim 11.
Jones in view of Viswanathan does not disclose peripheral ground terminal embedded within the encapsulant material, wherein the peripheral ground terminal has a proximal end directly connected to the mounting surface of the module substrate, and a distal end exposed at the contact surface, and wherein the peripheral ground terminal is electrically coupled to the first ground contact of the first power transistor die through a second conductive path through the first thermal dissipation structure and through a ground layer within the module substrate that contacts the first thermal dissipation structure.
Maalouf discloses an amplifier module (Fig. 1, el. 110, Para. [0017]) comprising a heat dissipation structure (Fig. 1, el. 610, Para. [0018]), a power transistor die (Fig. 1, el. 310, Para. [0018]), and a peripheral ground terminal (Fig. 1, el. 620, Para. [0023]) that has a distal end exposed at the contact surface (Fig. 7).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add a peripheral ground terminal, similar to Maalouf, to the amplifier module of Jones in view of Viswanathan. Doing so would have the benefit of providing better grounding, as well as facilitating connection of the module to another substrate (as in Maalouf, Fig. 10).
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan.
Regarding Claim 15, Jones discloses a method of fabricating a power amplifier (Fig. 7, Para. [0087]), the method comprising: coupling a power transistor die to a thermal dissipation structure that extends through a module substrate (see analysis of claim 1), wherein the module substrate has a mounting surface (see analysis of claim 1), a first surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate (see analysis of claim 1), and the power transistor die has a ground contact (see analysis of claim 1), wherein the ground contact is connected to the first surface of the thermal dissipation structure (see analysis claim 1); coupling a proximal end of an interior ground terminal to the thermal dissipation structure directly adjacent to a first side of the power transistor die (see analysis of claim 1 and Fig. 4A, Para. [0064] where the interior ground terminal is connected to the thermal dissipation structure through via 444); and covering the mounting surface of the module substrate and the power transistor die with an encapsulant material to form an amplifier module (Fig. 7, step 706, Para. [0087, also see analysis of claim 1), wherein a surface of the encapsulant material defines a contact surface of the amplifier module (see analysis of claim 1), a distal end of the interior ground terminal is exposed at the contact surface (see analysis of claim 1), only a portion of the encapsulant material and no other circuitry is present between the first side of the power transistor die and the interior ground terminal (see analysis of Claim 1) and the interior ground terminal is electrically coupled to the ground contact of the power transistor die through a first conductive path through the thermal dissipation structure (see analysis of claim 1).
Jones does not disclose the step of directly connecting a proximal end of an interior ground to the first thermal dissipation structure.
Viswanathan discloses a method (Fig. 9, Para. [0064]) with a step (Fig. 9, el. 904, Para. [0068]) of applying ground termination pins to a substrate. Note that this method can apply to Fig. 5, which discloses a thermal dissipation structure (Fig. 5, el. 522, Para. [0049] – note that although this is referred to as a substrate, it can be a thermal dissipation structure, similar to Fig. 3, el. 322, Para. [0039]), an interior terminal (Fig. 5, el. 563, Para. Para. [0050]) that can serve as a ground terminal (in Fig. 5, conductive pad 512 can be grounded, and thus internal terminal 563 will be grounded as well), wherein the interior terminal has a proximal end connected to the heat dissipation structure (Fig. 5, Para. [[0050) and a distal end exposed at a contact surface (Fig. 5, Para. [0050]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to include the step of attaching the ground terminal of Jones directly to the heat dissipation structure (as in Viswanathan). One benefit would be to provide a lower inductance ground path for high frequency signals, since the ground terminal would be directly connected to a large heat dissipation structure, and so the signal would not have to travel through narrow conductive structures.
Regarding claim 16, Jones in view of Viswanathan discloses the method of claim 15, further comprising coupling the amplifier module to a system substrate with a mounting surface of the system substrate facing the contact surface of the amplifier module (Fig. 7, step 708, Para. [0088]), wherein the system substrate further includes a second signal conducting layer, a second ground layer, and a ground pad, wherein the ground pad is electrically coupled to the second ground layer, and wherein the distal end of the interior ground terminal is coupled to the ground pad (see analysis of claim 11).
Regarding claim 17, Jones in view of Viswanathan discloses the method of claim 15, wherein the amplifier module 200 has a heat sink attachment surface (Fig. 6, el. 211, Para. [0082]) opposite the contact surface (Fig. 6, el. 382, Para. [0081]), and the method further comprises: coupling a heat sink to the heat sink attachment surface of the amplifier module (Fig. 7, step 710, Para. [0089]).
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan.
Regarding claim 18, Jones in view of Viswanathan discloses the method of claim 15, wherein a distance between the first side of the first power transistor die 234 and the first interior ground terminal 244 is less than a width of the first power transistor die 234 (Para. [0064]).
Jones in view of Viswanathan does not disclose that the distance is less than half a width of the first power transistor die.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to move the first interior ground terminal and position it such that its distance from the first power transistor die is less than half a width of the first power transistor die. Doing so would be the result of routine optimization (see MPEP 2144.05(II)(B)). As noted in Jones, the ground terminal 244 may be positioned at additional or different locations to minimize or eliminate the RF return current spreading across the module substrate (Para. [0064]), so a person of ordinary skill in the art would be motivated to experiment with the distance. In particular, they would have been motivated to move it closer, since this would reduce the inductance in the ground path. Further, by moving it from a distance of less than a width of the die to less than half a width of the die, a person of ordinary skill in the art would have had a reasonable expectation of success to minimize the RF return current, since the path length would be reduced.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Viswanathan and Maalouf.
Regarding Claim 22, Jones in view of Viswanathan discloses the method of claim 15.
Jones in view of Viswanathan does not disclose the steps of before covering the mounting surface of the module substrate and the power transistor die with the encapsulant material, directly connecting a proximal end of a peripheral ground terminal to the mounting surface of the module substrate, wherein the peripheral ground terminal is electrically coupled to the ground contact of the power transistor die through a second conductive path through the thermal dissipation structure and through a ground layer within the module substrate that contacts the thermal dissipation structure, and wherein after covering the mounting surface of the module substrate and the power transistor die with the encapsulant material, a distal end of the peripheral ground terminal is exposed at the contact surface.
Maalouf discloses an amplifier module (Fig. 1, el. 110, Para. [0017]) comprising a heat dissipation structure (Fig. 1, el. 610, Para. [0018]), a power transistor die (Fig. 1, el. 310, Para. [0018]), and a peripheral ground terminal (Fig. 1, el. 620, Para. [0023]) that has a distal end exposed at the contact surface (Fig. 7).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add the steps of connecting a peripheral ground terminal, similar to Maalouf, to the amplifier module of Jones in view of Viswanathan. Doing so would have the benefit of providing better grounding, as well as facilitating connection of the module to another substrate (as in Maalouf, Fig. 10).
Conclusion
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899