DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 19 Dec 2022 for application number 18/067,968. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-20 are presented for examination. Elected claims 1-15 are examined below; non-elected claims 16-20 have been withdrawn
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 19 Dec 2022 was filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Invention I. in the reply filed on 04 May 2026 is acknowledged. The traversal is on the ground(s) that a serious search burden would not exist. This is not found persuasive because, as expressed in the Requirement for Restriction/Election filed 12 Mar 2026, the semiconductor memory device of claims 1 and 9 could be made by materially different processes compared to compared to the method of claim 16, for instance using deposition instead of etching; this would create a serious search and examination burden, as various classifications and search strategies would be required.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yim et al. [hereinafter as Yim] (US 2022/0367658 A1).
In reference to claim 1, Yim teaches A semiconductor device, comprising:
a lower semiconductor device [lower nanosheets NS-L; Fig. 2B, para 0045] over a substrate [substrate 290; Fig. 2B, para 0047], the lower semiconductor device having a first width [NS-L has a width];
an upper semiconductor device [upper nanosheets NS-U; Fig. 2B, para 0045] over the lower semiconductor device [NS-L], the upper semiconductor device having a second width smaller than the first width [width of NS-U is smaller than width of NS-L]; and
a dielectric structure [insulation region 260; Fig. 2B, para 0043] over the lower semiconductor device [NS-L], the dielectric structure [260] having a first sidewall [left side of 260; Fig. 2B] of the dielectric structure [260] that faces the upper semiconductor device [NS-U] and a second sidewall [right side of 260] of the dielectric structure [260] that aligns vertically [right side of 260 aligns vertically with right side of NS-L] with a sidewall of the lower semiconductor device [NS-L].
In reference to claim 8, Yim teaches The semiconductor device of claim 1, wherein the lower semiconductor device [NS-L] comprises a lower plurality of channel layers [nanosheets of NS-L], wherein the upper semiconductor device [NS-U] comprises an upper plurality of channel layers [nanosheets of NS-U], and wherein the semiconductor device further comprises a shared gate [para 0031 discloses that Fig. 2B discloses a gate-all-around transistor] around the lower plurality of channel layers [nanosheets of NS-L], the upper plurality of channel layers [nanosheets of NS-U], and the dielectric structure [260].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-4, 7, 9-11, and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Tsai et al. [hereinafter as Tsai] (US 2024/0170533 A1).
In reference to claim 2, Yim teaches the invention of claim 1.
Yim further teaches The semiconductor device of claim 1, further comprising a dielectric liner [spacer; see annotated Fig. 2B below; para 0043], wherein the dielectric liner [spacer] is formed from a first dielectric material different from [para 0054 discloses that the spacer may be an oxide or nitride, and the insulating material, i.e. 260, may be the other of an oxide or nitride] a second dielectric material of the dielectric structure [260].
Yim does not explicitly teach that the dielectric liner is between the dielectric structure and the upper semiconductor device.
Yim and Tsai teach that the dielectric liner [NS-U of Yim; analogously, first part 161 of dielectric wall 16; Fig. 10, para 0041 of Tsai] is between the dielectric structure [260 of Yim; analogously, second part 162 of 16; Fig. 10, para 0041 of Tsai] and the upper semiconductor device [NS-U of Yim; analogously, channel features 121B; Fig. 10, para 0041 of Tsai].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yim and Tsai before the effective filing date of the claimed invention, to include the position of the dielectric liner as disclosed by Tsai into the semiconductor device of Yim in order to obtain a semiconductor device with a dielectric liner between channels and a dielectric structure.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with a dielectric liner between channels and a dielectric structure to provide the predictable result of enhancing performance by minimizing leakage among different components [Tsai, para 0002].
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In reference to claim 3, Yim and Tsai teach the invention of claim 2.
Yim and Tsai teach The semiconductor device of claim 2, wherein the upper semiconductor device [NS-U of Yim] comprises a plurality of channel layers [nanosheet layers of NS-U of Yim], and wherein the dielectric liner [161 of Tsai; analogously, spacer of Yim] has an L-shaped profile [161 of Tsai is L-shaped; Fig. 10], with a first sidewall of the dielectric liner [left side of 161 of Tsai] on the plurality of channel layers [121B of Tsai; analogously, nanosheets of NS-U of Yim] and a second sidewall of the dielectric liner [right side of spacer of Yim; analogously, 161 of Tsai] that aligns vertically with the sidewall of the lower semiconductor device [NS-L of Yim] and the second sidewall of the dielectric structure [right side of 260 of Yim].
In reference to claim 4, Yim and Tsai teach the invention of claim 2.
Yim teaches The semiconductor device of claim 2, wherein the upper semiconductor device [NS-U] comprises a plurality of channel layers [nanosheets of NS-U], and wherein the dielectric liner [spacer] has a top surface above a top surface of an uppermost channel layer of the plurality of channel layers [nanosheets of NS-U].
In reference to claim 7, Yim and Tsai teach the invention of claim 2.
Yim teaches The semiconductor device of claim 2, wherein the first dielectric material is selected from the group consisting of silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, and silicon carbide [para 0034 discloses that the spacer may be silicon nitride], and wherein second dielectric material is selected from the group consisting of silicon nitride, silicoboron carbonitride, and silicon oxycarbonitride [para 0054 discloses that the insulating material, i.e. 260, may be silicon nitride].
In reference to claim 9, Yim teaches A semiconductor device, comprising:
a lower semiconductor device [lower nanosheets NS-L; Fig. 2B, para 0045] over a substrate [substrate 290; Fig. 2B, para 0047], the lower semiconductor device having a first width [NS-L has a width];
an upper semiconductor device [upper nanosheets NS-U; Fig. 2B, para 0045] over the lower semiconductor device [NS-L], the upper semiconductor device having a second width smaller than the first width and comprising a plurality of channel layers [width of NS-U is smaller than width of NS-L];
a dielectric liner [spacer; see annotated Fig. 2B above; para 0043], the dielectric liner being formed from a first dielectric material; and
a dielectric structure [insulation region 260; Fig. 2B, para 0043] over the lower semiconductor device [NS-L], the dielectric structure [260] having a first sidewall [left side of 260; Fig. 2B] of the dielectric structure [260] that faces the upper semiconductor device [NS-U] and a second sidewall [right side of 260] of the dielectric structure [260] that aligns vertically with a sidewall of the lower semiconductor device [right side of 260 aligns vertically with right side of NS-L], the dielectric structure [260] being formed from a second dielectric material different from the first dielectric material [para 0054 discloses that the spacer may be an oxide or nitride, and the insulating material, i.e. 260, may be the other of an oxide or nitride].
However, Yim does not explicitly teach:
a dielectric liner on the plurality of channel layers;
a first sidewall of the dielectric structure that faces the upper semiconductor device and the dielectric liner.
Yim and Tsai teach:
a dielectric liner [first part 161 of dielectric wall 16; Fig. 10, para 0041; analogously, NS-U of Yim] on the plurality of channel layers [121B of Tsai; analogously, nanosheets of NS-U of Yim];
a first sidewall [left side of second part 162 of 16; Fig. 10, para 0041 of Tsai] of the dielectric structure [162] that faces the upper semiconductor device [channel features 121B; Fig. 10, para 0041 of Tsai] and the dielectric liner [161].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yim and Tsai before the effective filing date of the claimed invention, to include the position of the dielectric liner as disclosed by Tsai into the semiconductor device of Yim in order to obtain a semiconductor device with a dielectric liner between channels and a dielectric structure.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with a dielectric liner between channels and a dielectric structure to provide the predictable result of enhancing performance by minimizing leakage among different components [Tsai, para 0002].
In reference to claim 10, Yim and Tsai teach the invention of claim 9.
Yim and Tsai teach The semiconductor device of claim 9, wherein the dielectric liner [161 of Tsai; analogously, spacer of Yim] has an L-shaped profile [161 of Tsai is L-shaped; Fig. 10], with a first sidewall [left side of 161 of Tsai] of the dielectric liner [161] on the plurality of channel layers [121B of Tsai; analogously, nanosheets of NS-U of Yim] and a second sidewall of the dielectric liner [right side of spacer of Yim; analogously, 161 of Tsai] that aligns vertically with the sidewall of the lower semiconductor device [NS-L of Yim] and the second sidewall of the dielectric structure [right side of 260 of Yim].
In reference to claim 11, Yim and Tsai teach the invention of claim 9.
Tsai teaches The semiconductor device of claim 9, wherein the dielectric liner [161] has a top surface above a top surface of an uppermost channel layer [uppermost 121B] of the plurality of channel layers.
In reference to claim 14, Yim and Tsai teach the invention of claim 9.
Yim teaches The semiconductor device of claim 9, wherein the first dielectric material is selected from the group consisting of silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, and silicon carbide [para 0034 discloses that the spacer may be silicon nitride]s and wherein the second dielectric material is selected from the group consisting of silicon nitride, silicoboron carbonitride, and silicon oxycarbonitride [para 0054 discloses that the insulating material, i.e. 260, may be silicon nitride].
In reference to claim 15, Yim and Tsai teach the invention of claim 9.
The semiconductor device of claim 9, wherein the lower semiconductor device [NS-L] comprises a lower plurality of channel layers [nanosheets of NS-L], and wherein the semiconductor device further comprises a shared gate [para 0031 discloses that Fig. 2B discloses a gate-all-around transistor] around the lower plurality of channel layers [nanosheets of NS-L], the plurality of channel layers [nanosheets of NS-U], and the dielectric structure [260].
Allowable Subject Matter
Claims 5-6 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Thomas et al. (US-20230132749-A1) discloses insulating layer 112 and internal spacers 118 [Fig. 1A].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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