DETAILED ACTION
Claims 1-3, 9-12, and 20-32 are pending.
Claims 1-3, 9-12, 20, and 32 have been examined.
Claims 21-31 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 3, 2025, has been entered.
Specification
The amended title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. At this point in time, the examiner recommends --ENHANCED OFFLOAD TO A HARDWARE ACCELERATOR FUNCTION MAPPED TO A MEMORY LOCATION--
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 10 is objected to because of the following informalities:
In the last line, delete “the function provided by” since this language does not previously appear.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claims 1, 10-11, 20, and 32, “processing unit configured to write an operand…” (and the like). Per paragraphs [0022]-[0023] of the specification, and claim 2, such a processing unit may be a CPU or a core in a CPU system, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
At least one claim is identified as including a non-limiting contingent limitation. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.” See MPEP 2111.04(II).
Regarding claim 11, when the first memory location is not mapped to the function of the first accelerator, the writing of the last paragraph does not occur. As such, the broadest reasonable interpretation (BRI) of claim 11 includes only the receiving and determining steps. For this claim, the examiner recommends replacing “whether or not” with --that--. This ensures that all steps are performed.
Regarding claim 32, when the writing of claim 11 does not happen, then the delaying of claim 32 does not happen. Thus, the BRI of claim 32 includes the receiving and determining steps of claim 11 plus the receiving step of claim 32. The proposed amendment to claim 11 would also require all steps of claim 32.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maher et al., U.S. Patent No. 5,420,989.
Referring to claim 11, Maher has taught a method, comprising:
receiving, at a memory adaptor bridge (FIGs.1-3, at least 24 and/or 28), an attempt by a processing unit to write an operand to a first memory location (from column 1, lines 35-53, a processor executing a WRITE instruction is configured to write an operand to a first memory location);
determining, by the memory adaptor bridge, whether or not the first memory location is mapped to a function of a first hardware accelerator (see column 1, lines 35-53, and FIG.3. Component 28 will determine if the address (first memory location) of the memory mapped instruction corresponds to a function of the accelerator. That is, component 28 (at least in part using decoder 36) looks at the address and determines if it corresponds to a function. If not, then a normal memory write/store will occur (the coprocessor functions are in a particular block of the address space, so the remaining address space is for storing data);
(as described above, this is a non-limiting contingent limitation under BRI).
Referring to claim 32, Maher has taught the method of claim 11, further comprising: receiving, by the memory adaptor bridge, an attempt by the processing unit to write a second operand to a third memory location not mapped to the function of the first hardware accelerator (from column 1, lines 35-53, the address space contains a number of locations to store data or to map to coprocessor functions. Any number of WRITE instructions targeting any of the memory locations is within the scope of teachings of Maher. That is, a normal WRITE to store data to a location not mapped to a coprocessor may be executed to store data. Or, a different function of a coprocessor may be written to if something other than cosine is to be performed)(as described above, this is a non-limiting contingent limitation under BRI).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 9-11, 20, and 32 are rejected under 35 U.S.C. 103 as obvious over Maher in view of Treichler et al., U.S. Patent No. 7,240,179.
Referring to claim 1, Maher has taught a system (FIG.1), comprising;
a processing unit (see FIG.1, microprocessor 12, which is an equivalent of a CPU or a core (see 112(f) interpretation above)) configured to write an operand to a first memory location (from column 1, lines 35-53, a processor executing a WRITE instruction is configured to write an operand to a first memory location. When the first memory location corresponds to a function of an accelerator, the accelerator performs the function on the operand);
a first hardware accelerator (FIGs.2-5, core 26); and
a memory adaptor bridge (FIGs.1-3, at least 24 and/or 28) coupled to the processing unit and configured to:
determine whether or not the first memory location is mapped to a function of the first hardware accelerator (see column 1, lines 35-53, and FIG.3. Component 28 will determine if the address (first memory location) of the memory mapped instruction corresponds to a function of the accelerator. That is, component 28 (at least in part using decoder 36) looks at the address and determines if it corresponds to a function. If so, the corresponding function is ultimately outputted to core 26); and
based on determining that the first memory location is mapped to the function of the first hardware accelerator, write the operand to a second memory location accessible by the first hardware accelerator so as to cause the first hardware accelerator to perform the function on the operand to generate a result (see FIG.3 and column 6, lines 10-16 and 39-43. When the address is determined to correspond to a function, the operand of the memory-mapped instruction is written to latch memory location 54 for access by the accelerator to perform the function. From the example above, if the address corresponds to a cosine, the accelerator will perform a cosine on the operand to generate a result).
Maher has not explicitly taught wherein the second memory location is different from the first memory location which the processing unit initially intends to write the operand to. However, Treichler, in the same memory-mapped I/O field of endeavor, has taught that a writable address (location) in memory/RAM would become inaccessible/unusable as part of a memory hole when that location need to be mapped to an I/O device (see the “Background of Invention” section through the explanation of FIG.1A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Maher such that the first memory location corresponds to an actual location in physical RAM space. This is useful because for systems with fewer-memory mapped devices, more RAM would be available for storage. Given this modification, Maher’s WRITE instruction would specify a first memory location; thus, it intends to write an operand to this location in physical RAM space. However, because this location has been mapped to an I/O device (e.g. latch 54), instead of writing to the now inaccessible first memory location, component causes the write to occur to the second memory location 54. Note that intent is a matter of perspective. From the processor’s perspective, since a WRITE to a first memory location is present, its intention is to write to that first memory location. However, that location has been mapped to a second location and therefore an external component 28 re-routes the operand to the second location 54.
Referring to claim 3, Maher, as modified, has taught the system of claim 1, wherein the memory adaptor bridge is configured to: provide the result to a memory location accessible by the processing unit (see column 11, lines 15-21).
Referring to claim 9, Maher, as modified, has taught the system of claim 1, wherein the first hardware accelerator is configured to perform the function in a predetermined number of clock cycles after the memory adaptor bridge writes the operand to the memory location accessible by the first hardware accelerator (assuming the coprocessor is not busy with another operation, the fixed, clocked logic of the accelerator will complete the function in a predetermined number of cycles after the value in memory 54 is sent to the co-processor. This is the nature of clocked logic).
Referring to claim 10, Maher, as modified, has taught the system of claim 1, wherein the processing unit is configured to write a second operand to a third memory location not mapped to the function of the first hardware accelerator, and wherein the memory adaptor bridge is configured to delay the write of the second operand to the third memory location until after the memory adaptor bridge obtains the result of the function provided by the first hardware accelerator (see column 7, line 31, to column 8, line 19. If a second memory mapped instruction is encountered (where the second memory mapped instruction may specify an address that is not associated with the cosine function, but with another function (e.g. sine)), and the accelerator is busy with a previous memory mapped instruction, a hold/wait mechanism is implemented until the coprocessor is not busy (e.g. a result is obtained). From column 10, line 32, to column 11, line 34, the next operation would be latched in state M, which occurs after states K and L, when result data is placed in a temporary register for retrieval).
Claim 11, when the first memory location is mapped to the function of the first hardware accelerator, is rejected for similar reasoning as claim 1.
Referring to claim 20, Maher has taught a memory adaptor bridge (FIGs.1-3, at least 24 and/or 28), comprising;
first circuitry to:
receive an attempt by a processing unit to write an operand to a first memory location (from FIGs.1-3 and column 1, lines 35-53, microprocessor 12, which is an equivalent of a CPU or a core (see 112(f) interpretation above), sends a WRITE instruction to the bridge to writes an operand to a logical memory location);
determine whether or not the first memory location is mapped to a function of a hardware accelerator (see column 1, lines 35-53, and FIG.3. Component 28 will determine if the address of the memory mapped instruction corresponds to a function of accelerator 26. That is, component 28 (at least in part using decoder 36) looks at the address and determines if it corresponds to a function. If so, the corresponding function is ultimately outputted to core 26); and
based on determining that the first memory location is mapped to the function of the hardware accelerator, write the operand to a second memory location accessible by the hardware accelerator (see FIG.3 and column 6, lines 10-16 and 39-43. When the address is determined to correspond to a function, the operand of the memory-mapped instruction is written to latch memory location 54 for access by the accelerator to perform the function. From the example above, if the address corresponds to a cosine, the accelerator will perform a cosine on the operand to generate a result).
Maher has not explicitly taught wherein the second memory location is different from the first memory location which the processing unit initially intends to write the operand to. However, Treichler, in the same memory-mapped I/O field of endeavor, has taught that a writable address (location) in memory/RAM would become inaccessible/unusable as part of a memory hole when that location need to be mapped to an I/O device (see the “Background of Invention” section through the explanation of FIG.1A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Maher such that the first memory location corresponds to an actual location in physical RAM space. This is useful because for systems with fewer-memory mapped devices, more RAM would be available for storage. Given this modification, Maher’s WRITE instruction would specify a first memory location; thus, it intends to write an operand to this location in physical RAM space. However, because this location has been mapped to an I/O device (e.g. latch 54), instead of writing to the now inaccessible first memory location, component causes the write to occur to the second memory location 54. Note that intent is a matter of perspective. From the processor’s perspective, since a WRITE to a first memory location is present, its intention is to write to that first memory location. However, that location has been mapped to a second location and therefore an external component 28 re-routes the operand to the second location 54.
Maher has further taught second circuitry (FIG.3, at least circuit 54 and buses connected
thereto) configured to:
obtain a result of the function performed on the operand by the hardware accelerator (from FIG.3 and column 11, lines 5-10 and 15-21, result data is obtained on the bus between accelerator 26 and register 54); and
provide the result of the function to a memory location accessible by the processing unit (see column 11, lines 15-21. A temporary register is such a memory location that is accessed to obtain the accelerator output/result).
Claim 32 is rejected for similar reasoning as claim 10.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Maher in view of Treichler and the examiner’s taking of Official Notice.
Referring to claim 2, Maher, as modified, has taught the system of claim 1, but has not taught wherein the processing unit comprises a core of a multi-core central processing unit (CPU). However, a multi-core processor and coupling thereof to a coprocessor was well known in the art before applicant’s invention. A multi-core processor includes separate cores to each perform its own respective processing, thereby increasing parallelism and throughput. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Maher such that the processing unit comprises a core of a multi-core central processing unit (CPU).
Claim 12 is rejected for similar reasoning as claim 2.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Maher in view of the examiner’s taking of Official Notice.
Referring to claim 12, Maher has taught the system of claim 1 (when the writing step is not interpreted to occur). Maher has not taught wherein the processing unit comprises a core of a multi-core central processing unit (CPU). However, a multi-core processor and coupling thereof to a coprocessor was well known in the art before applicant’s invention. A multi-core processor includes separate cores to each perform its own respective processing, thereby increasing parallelism and throughput. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Maher such that the processing unit comprises a core of a multi-core central processing unit (CPU).
Response to Arguments
On page 9 of applicant’s response, applicant argues that Maher has not taught that the processing unit initially intends to write the operand to the first memory location.
The examiner has included Treichler as part of a new 103 rejection. The combination of Maher and Treichler are now asserted to teach the same intent as claimed. That is, it is obvious for the first memory location in Maher to actually belong to a RAM. Thus, a processor encountering a WRITE instruction specifying the first memory location has intent to write to that location in RAM. However, that location in RAM has been deemed inaccessible since it has been mapped to Maher’s accelerator. As such, instead of writing the operand to the first memory location in RAM as intended, it is written to the second location (latch 54).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights