DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 01/23/2026 has been entered. Claims 1, and 4-20 remain pending in the application. Claims 11-13 have been withdrawn as belonging to a non-elected species, in the applicant response to the restriction requirement, filed on 08/27/2025. Claims 2 and 3 have been cancelled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the claim is dependent on a canceled claim. For the purpose of examination, claim 4 will be interpreted as: The semiconductor device of claim 1 , wherein the first power supply is ground source.
Claims 5-10 are also rejected as being dependent on claim 4.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do et al., (United States Patent Application Publication Number, US 2022/0208757 A1), hereinafter referenced as Do.
Regarding claim 1, Do teaches a semiconductor device comprising: a plurality of circuits (Fig.11, circuits #PGT1, #RX2, #PGT2) a first power supply disposed on a first side of a first circuit of the plurality of circuits, wherein the first side comprises a backside a power distribution network of the semiconductor device (Fig.12, first power supply is element #PWL1, which is disposed on the backside of the first circuit, composed of elements #PGT1 and #RX2 on the top half, and corresponding to VDD, as shown in Fig.4); a second power supply disposed on the first side of the first circuit of the plurality of circuits (Fig.12, second power supply is element #PWL1, which is disposed on the backside of the first circuit, and corresponding VVDD rail located at the top of the figure, as shown in Fig.27A); and a third power supply disposed on a second side of the second circuit of the plurality of circuits, wherein the second side of the second circuit of the plurality of circuits comprises the frontside of the power distribution network of the semiconductor device (Fig.12, element #M1L, which is disposed on the frontside of the second circuit composed of elements #PGT2 and #RX2 on the bottom half, and corresponding to element #VVDD, as shown in Fig.4) and wherein the first circuit and the second circuit are each directly connected at a common point, wherein the common point is the first power supply (Fig.12, #PGT1 and #PGT2 are connected at the common point #V2B, which is part of the first power supply, VDD), and wherein the second circuit connects the third power supply and the first power supply (Fig.12, circuit #PGT2 connects bottom VVDD with VDD) wherein the frontside side of the power distribution network is opposite to the backside of the power distribution network (the two power networks are at opposite sides).
Regarding claim 14, Do teaches a semiconductor device comprising: a plurality of circuits (Fig.21, circuits #PGT1, #RX2, #PGT2, #RX1, #ST1, #ST2, #WT and #WTC) coupled to a frontside power distribution network and a backside power distribution network (Fig.12, elements #M1L connected to VDD, VVDD and VSS form frontside power distribution network, , and elements #PWL1 connected to VDD, VVDD and VSS form the backside power distribution network, see also Fig.27A and 4); and one or more connecting vias disposed between the frontside power distribution network and the backside power distribution network that couple the frontside power distribution network with the backside power distribution network (element #TVI in Fig.4 and element #TV_S and TV_W in Fig.27A); wherein the backside power distribution network includes a first power supply (Fig.21, first power supply is element #PWL1, corresponding to VDD, as shown in Fig.4), a second power supply (Fig.21, second power supply is element #PWL1, corresponding to VSS, as shown in Fig.27A), and a first portion of a third power supply (Fig.21, third power supply is element #PWL1, corresponding to VVDD, as shown in Fig.27A); the frontside power distribution network includes a second portion of the third power supply coupled to the first portion of the third power supply by at least one of the one or more connecting vias (Fig.27A, vias TV_S couples the first/backside portion of VVDD, with the second/frontside portion of VVDD); and the plurality of circuits receive power from the first power supply, the second power supply, and the first portion of the third power supply within the same circuit row (Fig.21 the row is determined by top and bottom VVDD power lines, and the circuits are power by the power supplies) wherein the first circuit and the second circuit are coupled to one another at a common point, wherein the common point is a connecting via directly connected to the first power supply (Fig.12, #circuits #PGT1 and #PGT2 are connected at the common point #TVI, which is part of the first power supply, VDD), and wherein the second circuit connects the first portion of the third power supply and the first power supply (Fig.12, circuit #PGT2 connects the bottom VVDD rail with VDD).
Allowable Subject Matter
Claim 4 is allowed if written in such a way to overcome the 112b rejection, and if written in independent form. Claims 5 through 10 will be allowed as being dependent on claim 4.
Claim 15 is allowed if written in independent form. Claims 16 and 17 will be allowed as being dependent on claim 15.
Claim 18 is allowed. Claims 19 and 20 are allowed as being dependent on claim 18.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 4, the cited prior art does not teach or fairly suggests, along with other
claimed features: “wherein the first power supply is ground source”.
Regarding claim 15, the cited prior art does not teach or fairly suggests, along with other claimed features: “the second portion of the second power supply is coupled to the third power supply via a power gate.”.
Regarding claim 18, the cited prior art does not teach or fairly suggests, along with other claimed features: “the second portion of the second power supply provides power to the third power supply”.
Response to Arguments
Applicant’s arguments filed on 01/23/2026 have been fully considered but they
are not persuasive.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to claim 14 have been considered but are not persuasive. The new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (the power supplies were mapped differently as compared to previous rejection).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899