DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species VI, corresponding to Figures 5A-5D and
claims 1-7 and 10-20, in the reply filed on 10/24/2025, is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 15 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second
paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
5. Claim 15 recites the limitation “wherein an area of the RDL is larger”. The RDL can refer to the first RDL or the second RDL and therefore the claim is indefinite. For the purpose of examination claim 15 will be interpreted as: An optical package, comprising: a fan-out-wafer-level-packaging (FOWLP) sub-package including a first redistribution layer (RDL) on a first molded component; a molded interconnect substrate (MIS) sub-package over the FOWLP sub-package, the MIS sub-package including a second RDL on a second molded component; an optical chip over the FOWLP sub-package, the optical chip being electrically connected to the first RDL, wherein an area of the first RDL is larger than an area of the optical chip; and a package housing over the optical chip, wherein light to be received or transmitted by the optical chip is to pass through the package housing.
6. Claims 16, 17 and 18 are also being rejected as being depended on claim 15.
7. Claim 17 recites the limitation “electrically connected to the RDL”. The RDL can refer to
the first RDL or the second RDL and therefore the claim is indefinite. For the purpose of examination claim 17 will be interpreted as: The optical package of claim 15, wherein the optical chip is a vertical- cavity surface-emitting laser (VCSEL) chip, and an emitter of the VCSEL chip is electrically connected to the first RDL by one of: a pair of plated thick gold (Au) bumps with an Au-Au diffusion bond, a copper (Cu) pillar with a solder bond, an Au stud bump with an Au-Au diffusion bond, an Au bump with a silver epoxy bond, or an Au bump with a solder bond.
Claim Rejections - 35 USC § 102
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1, 4, 6 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shi et al., (United States Patent Number US 12010416 B1), hereinafter referenced as Shi.
10. Regarding claim 1, Shi teaches an optical package, comprising: a fan-out-wafer-level
packaging (FOWLP) sub-package (Fig.6E) including a redistribution layer (RDL) (Fig.6E, RDL, element #600) on a molded component including an electrical chip (Fig.6E, several chips are molded with molding element #620); an optical chip over the FOWLP sub-package the optical chip being electrically connected to the RDL (Fig.6E, element #652), wherein an area of a surface of the RDL is larger than an area of a surface of the optical chip (Fig.6E, top surface area of the RDL, element #600, is larger than the bottom surface area of element #652); and a package housing over the optical chip, wherein light to be received or transmitted by the optical chip is to pass through the package housing (Fig.6E shows a housing over element #652, with a lens assembly).
11. Regarding claim 4, Shi teaches the optical package of claim 1 as set forth in the
anticipation rejection. Shi further teaches the optical package of claim 1, wherein the package housing is attached to the FOWLP sub-package (Fig.6E).
12. Regarding claim 6, Shi teaches the optical package of claim 1 as set forth in the
anticipation rejection. Shi further teaches the optical package of claim 1, further comprising one or more components mounted on the FOWLP sub-package (Fig.6E, several components are mounted on the subpackage).
13. Regarding claim 14, Shi teaches the optical package of claim 1 as set forth in the
anticipation rejection. Shi further teaches the optical package of claim 1, wherein the optical chip comprises a vertical-cavity surface-emitting laser (VCSEL) chip or a sensor chip (Fig.63, element #652 is an image sensor, column 10, row 36).
Claim Rejections - 35 USC § 103
14. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
15. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Shi in view of Steinmann (United States Patent Application Publication Number, US 2022/0236381 A1) hereinafter referenced as Steinmann.
16. Regarding claim 5, Shi teaches the optical package of claim 1 as set forth in the anticipation rejection. Shi does not teach the optical package of claim 1, wherein the package housing is attached to a molded interconnect substrate sub-package that is over the FOWLP sub-package. Steinmann teaches the package housing (Fig.2, formed by elements #232 and #226) is attached to a molded interconnect substrate sub-package (Fig.2, element #216, paragraph [0082], rows 1-5) that is over a substrate. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Steinmann and disclose wherein the package housing is attached to a molded interconnect substrate sub-package that is over the FOWLP sub-package. This reduces the lateral footprint of the optical package.
17. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shi in view of Camacho, (United States Patent Application Publication Number, US 2009/0166785 A1) hereinafter referenced as Camacho.
18. Regarding claim 10, Shi teaches the optical package of claim 1 as set forth in the anticipation rejection. Shi does not teach the optical package of claim 1, wherein the optical chip is included in a second FOWLP sub-package, the second FOWLP sub-package comprising a second RDL and second molded component, wherein the optical chip is embedded in the second molded component. Camacho teaches the optical chip is included in a second FOWLP sub-package (Fig.9, optical chip, element #54, in including in the FOWLP package) the second FOWLP sub-package comprising a second RDL (Fig.9, element #94) and second molded component wherein the optical chip is embedded in the second molded component (Fig .5b, paragraph [0036], rows 5-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Camacho and disclose the optical chip is included in a second FOWLP sub-package, the second FOWLP sub-package comprising a second RDL and second molded component, wherein the optical chip is embedded in the second molded component. As disclosed by Camacho, including the optical chip in a second FOWLP results in a package suitable for faster and reliable high density integration applications at lower cost. Embedding the chips in molded components is a standard technique well known in the art, which as disclosed by Camacho allows the formation and later separation of the sub-packages.
19. Claims 1, 2, 7, 11, 13, 15-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Renjan et al. (United States Patent Application Publication Number, US 2021/0090908 A1) hereinafter referenced as Renjan, in view of Pagaila, (United States Patent Number, US 8,080,445 A1) hereinafter referenced as Pagaila.
20. Regarding claim 1, Renjan teaches an optical package, comprising: a sub-package including a redistribution layer (RDL) (Fig.8, element #180 includes RDL element #102) on a molded component including an electrical chip (Fig.8, element #120, encapsulated in molding compound element #411, paragraph [0065], rows 11-13). Renjan does not teach the sub-package is a fan-out-wafer-level-packaging (FOWLP). Pagaila teaches a very similar sub-package that is a fan-out-wafer-level-packaging (FOWLP) sub-package (Fig.3h, electrical chip, element #124, is encapsulated in molding compound, element #140 and comprises bottom side connectors). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Pagaila and disclose the sub-package is a fan-out-wafer-level-packaging (FOWLP) sub-package. Using wafer level packaging to manufacture the sub-package allows the simultaneous processing of multiple chips on a wafer which reduced production cycles and cost.
21. Renjan further teaches an optical chip over the FOWLP sub-package, the optical chip being electrically connected to the RDL (Fig.8, element #140 on the right side of the figure is connected to element #102 through elements #413, #419 and #497), wherein an area of a surface of the RDL is larger than an area of a surface of the optical chip (Fig.8, the top surface area of element #102 is larger than the bottom surface area of each element #140). In a different embodiment, Renjan teaches a package housing over the optical chip, wherein light to be received or transmitted by the optical chip is to pass through the package housing (paragraph [0080], rows 1-3 and 11-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to combine the teachings of Renjan and disclose a package housing over the optical chip, wherein light to be received or transmitted by the optical chip is to pass through the package housing. As disclosed by Renjan, the metal housing can provide EMI shielding (paragraph [0031], rows 22-26)
22. Regarding claim 2, the combination of Renjan and Pagaila teaches the optical package of claim 1 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 1, further comprising a molded interconnect substrate (MIS) sub-package (Fig.8, element #480 has interconnects, element #493 and #497) over the FOWLP sub-package (Fig.8, element #480 is on element #180) , the MIS sub-package including a second RDL (Fig.8, element #460) and a second molded component (Fig.8, element #130).
23. Regarding claim 7, the combination of Renjan and Pagaila teaches the optical package of claim 1 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 1, wherein the optical chip is electrically connected to the RDL by one of: a pair of plated gold (Au) bumps with an Au-Au diffusion bond, a copper (Cu) pillar with a solder bond, an Au stud bump with an Au-Au diffusion bond, an Au bump with a silver epoxy bond, or an Au bump with a solder bond (Fig.8, optical chip, element #140, is connected to RDL through copper pillars, element #413 and #493, with a solder bond, paragraph [0056], rows 17-20).
24. Regarding claim 11, the combination of Renjan and Pagaila teaches the optical package of claim 1 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 1, wherein the optical package is a multi- chip module including multiple optical chips (Fig.8, the package includes two emitters, element #140, and a photodiode, element #130, paragraph [0036], rows 3-6).
25. Regarding claim 13, the combination of Renjan and Pagaila teaches the optical package of claim 1 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 1, wherein the electrical chip comprises at least one of an integrated circuit (IC) driver chip, a capacitor array, a discrete circuit component, a heat spreader, or a logic chip (paragraph [0031], rows 4-12).
26. Regarding claim 15, Renjan teaches an optical package, comprising: a sub-package including a first redistribution layer (RDL) (Fig.8, element #180 includes RDL element #102) on a first molded component(Fig.8, element #120, encapsulated in molding compound element #411, paragraph [0065], rows 11-13). Renjan does not teach the sub-package is a fan-out-wafer-level-packaging (FOWLP) sub-package. Pagaila teaches a very similar sub-package that is a fan-out-wafer-level-packaging (FOWLP) sub-package (Fig.3h, electrical chip, element #124, is encapsulated in molding compound, element #140 and comprises bottom side connectors). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Pagaila and disclose the sub-package is a fan-out-wafer-level-packaging (FOWLP) sub-package. Using wafer level packaging to manufacture the sub-package allows the simultaneous processing of multiple chips on a wafer which reduced production cycles and cost.
27. Renjan further teaches a molded interconnect substrate (MIS) sub-package (Fig.8, element #480 has interconnects, element #493 and #497) over the FOWLP sub-package (Fig.8, element #480 is on element #180) the MIS sub-package including a second RDL (Fig.8, element #460) on a second molded component (Fig.8, element #130); an optical chip over the FOWLP sub-package, the optical chip being electrically connected to the first RDL (Fig.8, element #140 on the right side of the figure is connected to element #102 through elements #413, #419 and #497), wherein an area of the first RDL is larger than an area of the optical chip (Fig.8, the top surface area of element #102 is larger than the bottom surface area of each element #140). In a different embodiment, Renjan teaches a package housing over the optical chip, wherein light to be received or transmitted by the optical chip is to pass through the package housing (paragraph [0080], rows 1-3 and 11-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Renjan and disclose a package housing over the optical chip, wherein light to be received or transmitted by the optical chip is to pass through the package housing. As disclosed by Renjan, the metal housing can provide EMI shielding (paragraph [0031], rows 22-26).
28. Regarding claim 16, the combination of Renjan and Pagaila teaches the optical package of claim 15 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 15, wherein the package housing is attached to the FOWLP sub-package or to the MIS sub-package (housing replaces the bonding compound, element #605 which is attached to the FOWLP sub-package, paragraph [0080], rows 1-3 and 11-12).
29. Regarding claim 17, the combination of Renjan and Pagaila teaches the optical package of claim 15 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 15, wherein the optical chip is a vertical- cavity surface-emitting laser (VCSEL) chip (paragraph [0034], rows 5-7), and an emitter of the VCSEL chip is electrically connected to the first RDL by one of: a pair of plated thick gold (Au) bumps with an Au-Au diffusion bond, a copper (Cu) pillar with a solder bond, an Au stud bump with an Au-Au diffusion bond, an Au bump with a silver epoxy bond, or an Au bump with a solder bond (Fig.8, optical chip, element #140, is connected to RDL through copper pillars, element #413 and #493, with a solder bond, paragraph [0056], rows 17-20).
30. Regarding claim 19, Renjan teaches an optical package, comprising: a fan-out-wafer-level-packaging (FOWLP) sub-package including a redistribution layer (RDL) (Fig.8, element #180 includes RDL element #102) on a molded component, wherein the molded component includes at least one electrical chip(Fig.8, element #120, encapsulated in molding compound element #411, paragraph [0065], rows 11-13). Pagaila teaches a very similar sub-package that is a fan-out-wafer-level-packaging (FOWLP) sub-package (Fig.3h, electrical chip, element #124, is encapsulated in molding compound, element #140 and comprises bottom side connectors). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Pagaila and disclose the sub-package is a fan-out-wafer-level-packaging (FOWLP) sub-package. Using wafer level packaging to manufacture the sub-package allows the simultaneous processing of multiple chips on a wafer which reduced production cycles and cost.
31. Renjan further teaches a vertical-cavity surface-emitting laser (VCSEL) chip over the FOWLP sub-package, the VCSEL chip Fig.8, element #140 on the right side of the figure is a VCSEL, paragraph [0034], rows 5-7), being electrically connected to the at least one electrical chip through the RDL (Fig.8, element #140 on the right side of the figure is connected to element #102 through elements #413, #419 and #497), wherein a size of the RDL is larger than a corresponding size of the VCSEL chip (Fig.8, horizontal length of the RDL is larger than the horizontal length of the chip). In a different embodiment, Renjan teaches a package housing over the VCSEL chip, wherein light to be received or transmitted by the VCSEL chip is to pass through the package housing (paragraph [0080], rows 1-3 and 11-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to combine the teachings of Renjan and disclose a package housing over the VCSEL chip, wherein light to be received or transmitted by the VCSEL chip is to pass through the package housing. As disclosed by Renjan, the metal housing can provide EMI shielding (paragraph [0031], rows 22-26).
32. Regarding claim 20, the combination of Renjan and Pagaila teaches the optical package of claim 19 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 19, further comprising a molded interconnect substrate (MIS) sub-package (Fig.8, element #480 has interconnects, elements #493 and #497) over the FOWLP sub-package (Fig.8, element #480 is on element #180), the MIS sub-package including a second RDL (Fig.8, element #460) and a second molded component (Fig.8, element #130).
33. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Renjan, in view of Pagaila, and in view of Chen (United States Patent Application Publication Number, US 2017/0353004 A1) hereinafter referenced as Chen.
34. Regarding claim 3, the combination of Renjan and Pagaila teaches the optical package of claim 1 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 1, wherein the package housing supports a set of optical filters (Fig.18, element #601). Renjan further teaches the emitter mat be a VCSEL (paragraph [0034], rows 5-7). Although Renjan does not explicitly teaches, the optical filters also act as protective windows. The combination of Renjan and Pagaila does not teach wherein the package housing supports a set of optical components arranged over the optical chip, the set of optical components including at least one of a diffractive optical element, a collimating lens, a microlens array (MLA), a rotational offset MLA, a glass, a protective coating, or a protective window. Chen teaches the package housing supports a set of optical components arranged over the optical chip, the set of optical components including at least a microlens array (MLA) (Fig.5B, element #520 is a microlens array, paragraph [0052], rows 6-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chen and disclose the package housing supports a set of optical components arranged over the optical chip, the set of optical components including at least one a microlens array (MLA). The microlens array provides increase optical efficiency of the VCSEL by reducing the emitted beam divergence.
35. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Renjan, in view of Pagaila, and in view of Young Don O (United States Patent Application Publication Number, US 2021/0099618 A1) hereinafter referenced as Don_O.
36. Regarding claim 12, the combination of Renjan and Pagaila teaches the optical package of claim 1 as set forth in the obviousness rejection. Renjan further teaches the optical package of claim 1, wherein the optical package is a proximity module including the optical chip (paragraph [0031], rows 1-4). The combination of Renjan and Pagaila does not teach the optical package of claim 1, wherein the optical package is a three-dimensional sensing module including the optical chip. Don_O teaches the optical package of claim 1, wherein the optical package is a three-dimensional sensing module including the optical chip (paragraph [0033], rows 1-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Don_O and disclose the optical package is a three-dimensional sensing module including the optical chip. As compared to proximity modules, the three-dimensional sensing modules can provide information not only related to the presence of objects but also the distance between these objects and the module.
37. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Renjan, in view of Pagaila, and in view of Camacho.
38. Regarding claim 18, the combination of Renjan and Pagaila teaches the optical package of claim 15 as set forth in the obviousness rejection. The combination of Renjan and Pagaila does not teach the optical package of claim 15, wherein the optical chip is included in a second FOWLP sub-package, the second FOWLP sub-package comprising a second RDL and second molded component, wherein the optical chip is embedded in the second molded component. Camacho teaches the optical chip is included in a second FOWLP sub-package (Fig.9, optical chip, element #54, in including in the FOWLP package) the second FOWLP sub-package comprising a second RDL (Fig.9, element #94) and second molded component wherein the optical chip is embedded in the second molded component (Fig .5b, paragraph [0036], rows 5-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Camacho and disclose the optical chip is included in a second FOWLP sub-package, the second FOWLP sub-package comprising a second RDL and second molded component, wherein the optical chip is embedded in the second molded component. As disclosed by Camacho, including the optical chip in a second FOWLP results in a package suitable for faster and reliable high density integration applications at lower cost. Embedding the chips in molded components is a standard technique well known in the art, which as disclosed by Camacho allows the formation and later separation of the sub-packages.
Conclusion
39. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 7:30 -5:00.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899