The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, without traverse, of claims 11-25 in the “Response to Restriction Requirement” filed on 07/23/2025 is acknowledged and entered by the Examiner.
This office action consider claims 1-25 pending for prosecution, wherein claims 1-10 are withdrawn from further consideration, and claims 11-25 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 11, 15-18, and 22-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Byun et al. (US 20020104874 A1; hereinafter Byun).
Regarding claim 11, Byun teaches an electrical package (see the entire document, specifically Fig. 4+; [0012+], and as cited below), comprising:
a substrate (120; Fig. 4 in view of Figs. 5-6; [0026]) having a first side (top side of 120), a second side (bottom side of 120) opposite the first side (top side of 120), and at least one corner (corner of 120);
one or more electrical components (110; Fig. 4 in view of Figs. 5-6; [0026]) mounted to the substrate (120; Fig. 4 in view of Figs. 5-6; [0026]); and
a plurality of electrically conductive interconnect members ({160, 162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) coupled to the second side (bottom side of 120) of the substrate (120; Fig. 4 in view of Figs. 5-6; [0026]), including at least one ({162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) of the interconnect members ({160, 162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that is closest to the corner (corner of 120) and has a larger size than inner interconnect members ({160}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that are positioned further inward away from the corner (corner of 120).
Regarding claim 15, Byun teaches all of the features of claim 11.
Byun further teaches wherein at least some of the inner interconnect members ({160, 162}; [0029-0031]) have a generally circular shape.
. Regarding claim 16, Byun teaches all of the features of claim 11.
Byun further teaches wherein the at least one interconnect member ({162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that is closest to the corner has a generally capsular shape.
Regarding claim 17, Byun teaches all of the features of claim 11.
Byun further teaches wherein the interconnect members ({160, 162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) are arranged as a grid (Fig. 4 in view of Fig. 5, [0026, 0031]) with at least some of the inner interconnect members ({160}; Fig. 4 in view of Figs. 5-6; [0029-0031]) occupying a single grid cell, and the interconnect member ({162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that is closest to the corner occupying at least two grid cells.
Regarding claim 18, Byun teaches an electrical package (see the entire document, specifically Fig. 4+; [0012+], and as cited below), comprising:
a substrate (120; Fig. 4 in view of Figs. 5-6; [0026]) having a first side (top side of 120) and a second side (bottom side of 120) opposite the first side (top side of 120);
one or more electrical components (110; Fig. 4 in view of Figs. 5-6; [0026]) mounted to the substrate (120; Fig. 4 in view of Figs. 5-6; [0026]); and
a plurality of electrically conductive interconnect members ({160, 162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) coupled to the second side (bottom side of 120) of the substrate (120; Fig. 4 in view of Figs. 5-6; [0026]), including at least one ({162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) of the interconnect members ({160, 162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that is furthest from a center (see Fig. 4 in view of Figs. 5-6) of the substrate (120; Fig. 4 in view of Figs. 5-6; [0026])and has a larger size than others ({160}; Fig. 4 in view of Figs. 5-6; [0029-0031]) of the interconnect members ({160, 162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that are positioned closer to the center (see Fig. 4 in view of Figs. 5-6).
Regarding claim 22, Byun teaches all of the features of claim 18.
Byun further teaches wherein at least some of the others ({160}; [0029-0031]) of the inner interconnect members ({160, 162}; [0029-0031]) have a generally circular shape.
. Regarding claim 23, Byun teaches all of the features of claim 18.
Byun further teaches wherein the at least one interconnect member ({162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that is furthest from the center has a generally capsular shape.
Regarding claim 24, Byun teaches all of the features of claim 18.
Byun further teaches wherein the at least one interconnect member ({162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that is furthest from the center is positioned at or proximate to a corner of the package (Fig. 4 in view of Figs. 5-6).
Regarding claim 25, Byun teaches all of the features of claim 18.
Byun further teaches wherein the interconnect members ({160, 162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) are arranged as a grid (Fig. 4 in view of Fig. 5, [0026, 0031]) with at least some of the inner interconnect members ({160}; Fig. 4 in view of Figs. 5-6; [0029-0031]) occupying a single grid cell, and the interconnect member ({162}; Fig. 4 in view of Figs. 5-6; [0029-0031]) that is furthest from the center occupying at least two grid cells (Fig. 4 in view of Figs. 5-6).
3. Claims 11-15, 18-22, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Byun et al. (US 20180063966 A1; hereinafter Chiu).
Regarding claim 11, Chiu teaches an electrical package (see the entire document, specifically Fig. 2A+; [0007+], and as cited below), comprising:
a substrate (20; Fig. 3; [0033-0036]) having a first side (top side of 20), a second side (bottom side of 20) opposite the first side (top side of 20), and at least one corner (corner of 20);
one or more electrical components (22; Fig. 3; [0033]) mounted to the substrate (20; Fig. 3; [0033-0036]); and
a plurality of electrically conductive interconnect members ({210, 23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) coupled to the second side (bottom side of 20) of the substrate (20; Fig. 3; [0033-0036]), including at least one ({23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) of the interconnect members ({210, 23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) that is closest to the corner (corner of 20) and has a larger size than inner interconnect members ({210, 23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) that are positioned further inward away from the corner (corner of 20).
Regarding claim 12, Chiu teaches all of the features of claim 11.
Chiu further teaches wherein the one or more electrical components (22; Fig. 3; [0033]) are mounted to the first side (top side of 20) of the substrate (20), and having one or more additional electrical components (21; Fig. 3; [0033]) mounted to the second side (bottom side of 20) of the substrate (20).
Regarding claim 13, Chiu teaches all of the features of claim 12.
Chiu further comprising a mold structure (26; Fig. 3; [0046-0047]) extending over at least part of the second side (bottom side of 20) of the substrate (20) and at least partially surrounding the one or more additional electrical components (21; Fig. 2C; [0033]).
Regarding claim 14, Chiu teaches all of the features of claim 13.
Chiu further comprising a mold structure (24; Fig. 3; [0038]) extending over at least part of the first side (top side of 20) of the substrate (20) and at least partially surrounding the one or more electrical components (22).
Regarding claim 15, Chiu teaches all of the features of claim 11.
Chiu further teaches wherein at least some of the inner interconnect members ({210, 23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) have a generally circular shape.
Regarding claim 18, Chiu teaches an electrical package (see the entire document, specifically Fig. 2A+; [0007+], and as cited below), comprising:
a substrate (20; Fig. 3; [0033-0036]) having a first side (top side of 20) and a second side (bottom side of 20) opposite the first side (top side of 20);
one or more electrical components (22; Fig. 3; [0033]) mounted to the substrate (20; Fig. 3; [0033-0036]); and
a plurality of electrically conductive interconnect members ({210, 23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) coupled to the second side (bottom side of 20) of the substrate (20), including at least one ({23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) of the interconnect members ({210, 23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) that is furthest from a center (see Fig. 3) of the substrate (20) and has a larger size than others ({210}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) of the interconnect members ({210, 23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) that are positioned closer to the center (see Fig. 3).
Regarding claim 19, Chiu teaches all of the features of claim 18.
Chiu further teaches wherein the one or more electrical components (22; Fig. 3; [0033]) are mounted to the first side (top side of 20) of the substrate (20), and having one or more additional electrical components (21; Fig. 3; [0033]) mounted to the second side (bottom side of 20) of the substrate (20).
Regarding claim 20, Chiu teaches all of the features of claim 19.
Chiu further comprising a mold structure (26; Fig. 3; [0046-0047]) extending over at least part of the second side (bottom side of 20) of the substrate (20) and at least partially surrounding the one or more additional electrical components (21; Fig. 2C; [0033]).
Regarding claim 21, Chiu teaches all of the features of claim 20.
Chiu further comprising a mold structure (24; Fig. 3; [0038]) extending over at least part of the first side (top side of 20) of the substrate (20) and at least partially surrounding the one or more electrical components (22).
Regarding claim 22, Chiu teaches all of the features of claim 18.
Chiu further teaches wherein at least some of the others ({210}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) of the inner interconnect members ({210, 23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) have a generally circular shape.
Regarding claim 24, Chiu teaches all of the features of claim 18.
Chiu further teaches wherein the at least one interconnect member ({23}; Fig. 3 in view of Fig. 2A; [0033, 0035, 0037]) that is furthest from the center is positioned at or proximate to a corner of the package (Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 12-14 and 19-21 are rejected under 35 U.S.C.103 as being unpatentable over Byun et al. (US 20020104874 A1; hereinafter Byun), in view of Chiu et al. (US 20180063966 A1; hereinafter Chiu).
Regarding claim 12, Byun teaches all of the features of claim 11.
Byun further teaches wherein the one or more electrical components (110; Fig. 4 in view of Figs. 5-6; [0026]) are mounted to the first side (top side of 120) of the substrate (120; Fig. 4 in view of Figs. 5-6; [0026]), and having (see below for “one or more additional electrical components mounted to”) the second side (bottom side of 120) of the substrate (120; Fig. 4 in view of Figs. 5-6; [0026]).
As noted above, Byun does not expressly disclose “implanting ions to form a Punch-Though-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions”.
However, in the analogous art, Chiu teaches semiconductor structures ([0001]), wherein (Fig. 2C; [0021+]) a carrier (20; Fig. 2C; [0033]) has a second electronic component (22; Fig. 2C; [0033]) on its top surface and the first electronic component (21; Fig. 2C; [0033]) on its bottom surface, where the electronic component (21; Fig. 2C; [0033]) is encapsulated by a second encapsulant (26; Fig. 2C; [0046]-0047)
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chiu’s first elecntronic component on the bottom side of the carrier into Byun’s device, and thereby, modified device Byun’s (by Chiu) device will have wherein the one or more electrical components (Byun 110; Fig. 4 in view of Figs. 5-6; [0026]) are mounted to the first side (Byun top side of 120) of the substrate (Byun 120; Fig. 4 in view of Figs. 5-6; [0026]), and having one or more additional electrical components (in view of Chiu 21; Fig. 2C; [0033]) mounted to the second side (Byun bottom side of 120) of the substrate (Byun 120; Fig. 4 in view of Figs. 5-6; [0026])
The ordinary artisan would have been motivated to modify Byun in the manner set forth above, at least, because this inclusion provides an additional electronic component to be connected to the bottom side of the substrate (Chiu [0033]), which helps add increased functionality to the device for faster processing.
Regarding claim 13, modified Byun (by Chiu) teaches all of the features of claim 12.
Modified Byun (by Chiu) further comprising a mold structure (in view of Chiu 26; Fig. 2C; [0046-0047]) extending over at least part of the second side (Byun bottom side of 120) of the substrate (Byun 120; Fig. 4 in view of Figs. 5-6; [0026]) and at least partially surrounding the one or more additional electrical components (in view of Chiu 21; Fig. 2C; [0033]).
Regarding claim 14, modified Byun (by Chiu) teaches all of the features of claim 13.
Modified Byun (by Chiu) further comprising a mold structure (Byun 140; Fig. 4 in view of Figs. 5-6; [0027]) extending over at least part of the first side (Byun top side of 120) of the substrate (Byun 120; Fig. 4 in view of Figs. 5-6; [0026]) and at least partially surrounding the one or more electrical components (110; Fig. 4 in view of Figs. 5-6; [0026]).
Regarding claim 19, Byun teaches all of the features of claim 18.
Byun further teaches wherein the one or more electrical components (110; Fig. 4 in view of Figs. 5-6; [0026]) are mounted to the first side (top side of 120) of the substrate (120; Fig. 4 in view of Figs. 5-6; [0026]), and having (see below for “one or more additional electrical components mounted to”) the second side (bottom side of 120) of the substrate (120; Fig. 4 in view of Figs. 5-6; [0026]).
As noted above, Byun does not expressly disclose “implanting ions to form a Punch-Though-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions”.
However, in the analogous art, Chiu teaches semiconductor structures ([0001]), wherein (Fig. 2C; [0021+]) a carrier (20; Fig. 2C; [0033]) has a second electronic component (22; Fig. 2C; [0033]) on its top surface and the first electronic component (21; Fig. 2C; [0033]) on its bottom surface, where the electronic component (21; Fig. 2C; [0033]) is encapsulated by a second encapsulant (26; Fig. 2C; [0046]-0047)
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chiu’s first elecntronic component on the bottom side of the carrier into Byun’s device, and thereby, modified device Byun’s (by Chiu) device will have wherein the one or more electrical components (Byun 110; Fig. 4 in view of Figs. 5-6; [0026]) are mounted to the first side (Byun top side of 120) of the substrate (Byun 120; Fig. 4 in view of Figs. 5-6; [0026]), and having one or more additional electrical components (in view of Chiu 21; Fig. 2C; [0033]) mounted to the second side (Byun bottom side of 120) of the substrate (Byun 120; Fig. 4 in view of Figs. 5-6; [0026])
The ordinary artisan would have been motivated to modify Byun in the manner set forth above, at least, because this inclusion provides an additional electronic component to be connected to the bottom side of the substrate (Chiu [0033]), which helps add increased functionality to the device for faster processing.
Regarding claim 20, modified Byun (by Chiu) teaches all of the features of claim 19.
Modified Byun (by Chiu) further comprising a mold structure (in view of Chiu 26; Fig. 2C; [0046-0047]) extending over at least part of the second side (Byun bottom side of 120) of the substrate (Byun 120; Fig. 4 in view of Figs. 5-6; [0026]) and at least partially surrounding the one or more additional electrical components (in view of Chiu 21; Fig. 2C; [0033]).
Regarding claim 21, modified Byun (by Chiu) teaches all of the features of claim 20.
Modified Byun (by Chiu) further comprising a mold structure (Byun 140; Fig. 4 in view of Figs. 5-6; [0027]) extending over at least part of the first side (Byun top side of 120) of the substrate (Byun 120; Fig. 4 in view of Figs. 5-6; [0026]) and at least partially surrounding the one or more electrical components (110; Fig. 4 in view of Figs. 5-6; [0026]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898