DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/20/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 9-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2022/0181441 to Liebmann et al (hereinafter Liebmann).
Regarding Claim 1, Liebmann discloses a semiconductor device, comprising:
a stacked field effect transistor (FET) structure comprising:
a bottom FET device (700_3; Fig. 23);
a top FET device (700_4) overlying the bottom FET device;
dielectric material (650) interposed between the bottom FET device and the top FET device; and
a gate tie-down assembly (646) of the top FET device extending through the bottom FET device.
Regarding Claim 2, Liebmann discloses the semiconductor device according to Claim 1, further comprising a backside power rail (unlabeled, seen extending through STI 612 to electrode 628) to which the gate tie-down assembly is connected.
Regarding Claim 3, Liebmann discloses the semiconductor device according to Claim 2, wherein:
the backside power rail comprises multiple types of contact leads, and the gate tie-down assembly is connectable with each of the multiple types of contact leads (Fig. 23).
Regarding Claim 4, Liebmann discloses the semiconductor device according to Claim 2, further comprising a backside contact (610, Fig. 23) by which the bottom FET device is connected to the backside power rail (606).
Regarding Claim 5, Liebmann discloses the semiconductor device according to Claim 1, wherein the top FET device comprises semiconductor channels and gate metal surrounding the semiconductor channels (Fig. 23).
Regarding Claim 6, Liebmann discloses the semiconductor device according to Claim 5, wherein the gate tie-down assembly comprises:
conductive material (646) in contact with the gate metal of the top FET device; and
dielectric spacers (642) isolating the conductive material from the bottom FET device.
Regarding Claim 7, Liebmann discloses the semiconductor device according to Claim 5, wherein the gate tie-down assembly comprises:
conductive material (646) in contact with the gate metal of the top FET device; and
inner spacers (642) isolating the conductive material from the semiconductor channels.
Regarding Claim 9, Liebmann discloses a semiconductor device, comprising:
a backside power rail (unlabeled, seen extending through STI 612 to electrode 628)); and
a stacked field effect transistor (FET) structure comprising:
a bottom FET device (700_3; Fig. 23);
a top FET device (700_4) overlying the bottom FET device;
dielectric material (650) interposed between the bottom FET device and the top FET device; and
a gate tie-down assembly (646) of the top FET device extending through the bottom FET device to connect to the backside power rail.
Regarding Claim 10, Liebmann discloses the semiconductor device according to Claim 9, wherein:
the backside power rail comprises multiple types of contact leads (Fig. 23), and the gate tie-down assembly is connectable with each of the multiple types of contact leads (Fig, 23).
Regarding Claim 11, Liebmann discloses the semiconductor device according to Claim 9, further comprising a backside contact (610, Fig. 23) by which the bottom FET device is connected to the backside power rail.
Regarding Claim 12, Liebmann discloses the semiconductor device according to Claim 9, wherein the top FET device comprises semiconductor channels and gate metal surrounding the semiconductor channels (Fig. 23).
Regarding Claim 13, Liebmann discloses the semiconductor device according to Cclaim 12, wherein the gate tie-down assembly comprises:
conductive material (646) in contact with the gate metal of the top FET device; and
dielectric spacers (642) isolating the conductive material from the bottom FET device.
Regarding Claim 14, Liebmann discloses the semiconductor device according to Claim 12, wherein the gate tie-down assembly comprises:
conductive material (646) in contact with the gate metal of the top FET device; and
inner spacers (642) isolating the conductive material from the semiconductor channels.
Allowable Subject Matter
Claims 16-20 are allowed.
Claims 8 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 16 recites a semiconductor device fabrication method, comprising:
forming a stack comprising a bottom field effect transistor (FET) device, a top FET device overlying the bottom FET device and dielectric material interposed between the bottom FET device and the top FET device;
creating an opening through the stack;
filling the opening with an outer core dielectric and an inner core dielectric;
removing the inner core dielectric and a portion of the outer core dielectric to expose gate metal and portions of channels of the top FET device;
forming inner spacers to isolate remainders of the channels; and
forming a backside power rail contact by metallizing space previously occupied by the inner core dielectric and the portion of the outer core dielectric.
Liebmann does not disclose the structure or method for inner spacers to isolate remainders of the channels from the gate tie-down structure. US PG Pub 2023/0067311 (“Lai”), US PG Pub 2023/0377985 (“Smith”) and US Patent No. 12,080,608 (“Lin”) are cited as being examples of other relevant references in the art for comparison to Applicant’s invention. However, these references do not cure the deficiencies of Liebmann and do not disclose the invention themselves. A search of other, relevant references does not show Applicant’s invention to be obvious or anticipated. Claims 17-20 depend on Claim 16 and are allowable for at least the reason above. Claims 8 and 15 recite similar structures for inner spacers.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893