Prosecution Insights
Last updated: July 17, 2026
Application No. 18/069,229

POWER MODULE PACKAGE

Non-Final OA §103§112
Filed
Dec 21, 2022
Priority
May 10, 2022 — TW 111117390
Examiner
BULLARD-CONNOR, GENEVIEVE GRACE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Niko Semiconductor Co. Ltd.
OA Round
3 (Non-Final)
50%
Grant Probability
Moderate
3-4
OA Rounds
1m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 50% of resolved cases
50%
Career Allowance Rate
7 granted / 14 resolved
-18.0% vs TC avg
Strong +47% interview lift
Without
With
+46.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
38 currently pending
Career history
72
Total Applications
across all art units

Statute-Specific Performance

§103
85.2%
+45.2% vs TC avg
§102
11.4%
-28.6% vs TC avg
§112
3.4%
-36.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 28 2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 requires the limitation “wherein each of the first non-contact section and the second non-contact section has a bending portion extending in an opposite direction.” It is unclear as to what the direction the bent portions of the terminals is opposite to. For examination purposes, the Examiner will interpret the claim to require that the terminals are bent opposite to each other’s bending direction. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 7, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kawanami et al. (“Kawanami” US 2011/0057713) and Hable et al. (“Hable” US 2018/0122720). Regarding claim 1, Kawanami discloses a power module package (Figure 1), comprising: an electronic assembly including at least one substrate (202, 203, 204): a first terminal assembly (211, on upper side of substrate 203) including at least one first power device terminal (211 is a gate signal terminal for the power devices); and a second terminal assembly (211, on lower side of substrate 203) including at least one second power device terminal (211 is a gate terminal for the power devices); a package layer (resin member 216) for enclosing the electronic assembly (encloses the assembly, see Figure 1), wherein each of the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower) has a portion protruding from a side surface of the package layer (216) and being exposed outside the package layer (216, see Figure 1, terminals 211 protrude from the left side surface of the package layer 216); and an electrical isolation portion located on the side surface of the package layer (216, electrical isolation portion is the portion of the left side of the package layer 216 that extends between the upper and lower terminals 211, this provides a creepage/insulation distance and electrical insulation between the terminals and thus is considered an electrical isolation portion) and between the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower, see Figure 1). wherein the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower) respectively extend from different surfaces of the substrate (203, extend from the upper and lower surfaces of the substrate 203, respectively), and a height difference is formed between the at least one first power device terminal and the at least one second power device terminal (see Figure 1, there is a height difference between the upper and lower terminals 211); wherein the at least one first power device terminal (211, upper) includes a first contact section (section with the lower surface directly physically contacting joining material 210) and a first non-contact section (section of 211, upper with lower surface not directly contacting 210), the first contact section is directly connected to the substrate (203, first contact section is directly connected to the substrate through joining material 210), and the first non-contact section is not in contact with the substrate (203, see Figure 1), and the substrate (203) protrudes from the first contact section and extends to a position under the first non-contact section (see Figure 1, see also annotated Figure 1 below); wherein the at least one second power device terminal (211, lower) includes a second contact section (section with the upper surface directly physically contacting joining material 210) and a second non-contact section (section with upper surface not directly contacting 210), the second contact section (section of 211, lower contacting the joining material 210) is directly connected to the substrate (directly connected to the substrate 203 through the joining material 210, see Figure 1), and the second non-contact section (portion of 211, lower not directly contacting the joining material 210) is not in contact with the substrate (203, see Figure 1), and the substrate (203) protrudes from the second contact section (portion of 211, lower that directly contacts the joining material 210) and extends to a position above the second non-contact section (portion of 211, lower not in direct contact with the joining material 210, see Figure 1); wherein the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower) are symmetric with respective to the electrical isolation portion (left side portion of package layer 216 between the terminals 211, see Figure 1); and wherein a side edge of the substrate (203) is laterally aligned with the electrical isolation portion of the package layer (216, see Figure 1, which shows the substrate 203 provided on the same horizontal extending region as the portion of the package layer between the terminals 211, thus is considered laterally aligned with the electrical isolation portion of the package layer 216). Kawanami does not disclose that the electrical isolation portion is recessed within the side surface of the package layer, or that the non-contact sections of the terminals have a bending portion in an opposite direction. However, Hable discloses two terminals (118/119, see Figure 1), an electrical isolation portion (dielectric film 170) between the terminals (118/119, see Figure 1) that is also recessed within a side surface of the package layer (108, see Figure 1 which shows the dielectric film 170 protrudes into a recessed side surface of the package layer 108), and that portions of the terminals (118/119) have a bending portion in an opposite direction (para. [0030] discloses that the electrically conductive contact structures (i.e., terminals 118/119) may be bent with the dielectric foil therebetween to reduce electric coupling, while not shown in Figure 1, Hable discloses this configuration of bent terminals to increase the distance therebetween, thus would be bent in opposite directions to each other). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Hable into the teachings of Kawanami to include the electrical isolation portion between the terminals recessed within a side surface of the package layer and to bend the terminals in opposite directions for the purpose of providing further electrical isolation therebetween which reduces parasitic electrical coupling (Hable, para. [0030], [0075]). The combination of the teachings of Kawanami and Hable would result in the following structure: PNG media_image1.png 220 547 media_image1.png Greyscale Regarding claim 7, Kawanami discloses wherein the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower) are aligned with each other in a thickness direction of the substrate (203, cross-section of Figure 1 shows the upper and lower terminals 211 are aligned vertically). Regarding claim 13, Kawanami discloses wherein the substrate (203) further includes: an insulating plate (203) having a first surface and a second surface opposite to each other (upper and lower surfaces of the insulating plate 203), wherein the insulating plate has a side edge extending along a direction (left side edge extending in a vertical direction, see Figure 1); a first circuit pattern layer (upper “wiring layer” disposed between insulating plate 203 and joining material 210, see Figure 1 and para. [0038]-[0039]) disposed on the first surface of the insulating plate (203, upper surface), wherein the first terminal assembly (211, upper) is connected to the first circuit pattern layer (upper wiring layer is connected to the upper terminal 211 through joining material, see Figure 1); and a second circuit pattern layer (lower “wiring layer” disposed between insulating plate 203 and lower joining material 210, see Figure 1) disposed on the second surface of the insulating plate (203, lower surface), wherein the second terminal assembly (211, lower) is connected to the second circuit pattern layer (lower wiring layer, see Figure 1). PNG media_image2.png 614 1065 media_image2.png Greyscale Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kawanami and Hable as applied to claim 1 above, and further in view of Gong et al. (“Gong” US 2023/0326907). Regarding claim 14, Kawanami does not disclose a temperature sensor. Gong discloses that the electronic assembly (Figure 5) further includes a temperature sensor (13) disposed on the substrate (1, para. [0048], Figure 5), and the first terminal assembly (14, 15, 16) further includes a temperature sensing pin group (16, para. [0048]) electrically connected to the temperature sensor (13, see Figure 5 and para. [0048]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Gong into the teachings of Kawanami to include a temperature sensor as described above for the purpose of improving service life of the device (Gong, para. [0048]). Response to Arguments Applicant’s amendment to claim 1 with respect to the 112(b) rejection of claim 1 have been fully considered and overcome the 112(b) rejection. The 112(b) rejection of claim 1 has been withdrawn. Applicant’s arguments with respect to the prior art rejection have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Show 2 earlier events
Jan 16, 2026
Response Filed
Jan 29, 2026
Final Rejection mailed — §103, §112
Apr 13, 2026
Interview Requested
Apr 21, 2026
Applicant Interview (Telephonic)
Apr 21, 2026
Examiner Interview Summary
Apr 28, 2026
Request for Continued Examination
May 04, 2026
Response after Non-Final Action
May 29, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685163
SEMICONDUCTOR DEVICE
3y 8m to grant Granted Jul 14, 2026
Patent 12667010
SEMICONDUCTOR DEVICE
3y 6m to grant Granted Jun 23, 2026
Patent 12525517
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Jan 13, 2026
Study what changed to get past this examiner. Based on 3 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
50%
Grant Probability
97%
With Interview (+46.7%)
3y 8m (~1m remaining)
Median Time to Grant
High
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allowance rate.

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