DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “wherein the electrical isolation portion is independent of the package layer and is recessed within the side surface of the package layer”. This limitation seems to require that the electrical isolation portion layer is considered to be the recessed side surface of the package layer, as shown in Figure 10 of the instant application (electrical isolation portion is labeled GA, which is a recessed side surface of the package layer 5), and is also considered as independent of the package layer. However, it is unclear how the electrical isolation portion is independent of the package layer and simultaneously considered as a specific, integral feature of the package layer.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kawanami et al. (“Kawanami” US 2011/0057713) and Nolten et al. (“Nolten” US 2023/0187291).
Regarding claim 1, Kawanami discloses:
A power module package (Figure 1), comprising:
an electronic assembly including at least one substrate (202, 203, 204):
a first terminal assembly (211, on upper side of substrate 203) including at least one first power device terminal (211 is a gate signal terminal for the power devices); and
a second terminal assembly (211, on lower side of substrate 203) including at least one second power device terminal (211 is a gate terminal for the power devices);
a package layer (resin member 216) for enclosing the electronic assembly (encloses the assembly, see Figure 1), wherein each of the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower) has a portion protruding from a side surface of the package layer (216) and being exposed outside the package layer (216, see Figure 1, terminals 211 protrude from the left side surface of the package layer 216); and
an electrical isolation portion is located on the side surface of the package layer (216, electrical isolation portion is the segment of the left side surface of the package layer that extends between the upper and lower terminals 211, this provides a creepage distance and thus is considered an electrical isolation portion) and between the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower, see Figure 1).
wherein the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower) respectively extend from different surfaces of the substrate (203, extend from the upper and lower surfaces of the substrate 203, respectively), and a height difference is formed between the at least one first power device terminal and the at least one second power device terminal (see Figure 1, there is a height difference between the upper and lower terminals 211);
wherein the at least one first power device terminal (211, upper) includes a first contact section (section with the lower surface directly physically contacting joining material 210) and a first non-contact section (section with lower surface not directly contacting 210), the first contact section is directly connected to the substrate (203, first contact section is directly connected to the substrate through joining material 210), and the first non-contact section is not in contact with the substrate (203, see Figure 1), and the substrate (203) protrudes from the first contact section and extends to a position under the first non-contact section (see Figure 1, see also annotated Figure 1 below).
Kawanami does not disclose that the electrical isolation portion is independent of the package layer and is recessed within the side surface of the package layer.
However, Nolten discloses in Figures 1 and 4 a package layer (7) with an electrical isolation portion (creepage distance 80) recessed within the side surface of the package layer (7, see recess 732 in package layer 7 in Figure 4) that is between respective terminals (41) extending outside of the package layer (7).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Nolten into the teachings of Kawanami to include the recessed electrical isolation portion as taught by Nolten for the purpose of increasing creepage distance between two terminals of a device (Nolten, para. [0003]-[0004]), thereby preventing electrical arcing.
Regarding claim 7, Kawanami discloses:
The power module package according to claim 1, wherein the at least one first power device terminal (211, upper) and the at least one second power device terminal (211, lower) are aligned with each other in a thickness direction of the substrate (203, cross-section of Figure 1 shows the upper and lower terminals 211 are aligned vertically).
Regarding claim 13, Kawanami discloses:
The power module package according to claim 1, wherein the substrate (203) further includes:
an insulating plate (203) having a first surface and a second surface opposite to each other (upper and lower surfaces of the insulating plate 203),
wherein the insulating plate has a side edge extending along a direction (left side edge extending in a vertical direction, see Figure 1);
a first circuit pattern layer (upper “wiring layer” disposed between insulating plate 203 and joining material 210, see Figure 1 and para. [0038]-[0039]) disposed on the first surface of the insulating plate (203, upper surface), wherein the first terminal assembly (211, upper) is connected to the first circuit pattern layer (upper wiring layer is connected to the upper terminal 211 through joining material, see Figure 1); and
a second circuit pattern layer (lower “wiring layer” disposed between insulating plate 203 and lower joining material 210, see Figure 1) disposed on the second surface of the insulating plate (203, lower surface),
wherein the second terminal assembly (211, lower) is connected to the second circuit pattern layer (lower wiring layer, see Figure 1).
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Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kawanami as applied to claim 1 above, and further in view of Gong et al. (“Gong” US 2023/0326907).
Regarding claim 14, Kawanami does not disclose a temperature sensor.
Gong discloses that the electronic assembly (Figure 5) further includes a temperature sensor (13) disposed on the substrate (1, para. [0048], Figure 5), and the first terminal assembly (14, 15, 16) further includes a temperature sensing pin group (16, para. [0048]) electrically connected to the temperature sensor (13, see Figure 5 and para. [0048]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Gong into the teachings of Kawanami to include a temperature sensor as described above for the purpose of improving service life of the device (Gong, para. [0048]).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899