DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 12/7/25.
Applicant’s amendment to claims 1 and 5-8 is acknowledged.
Applicant’s cancellation of claims 4 is acknowledged.
Claims 1-3 and 5-20 are pending and claim 13 is withdrawn.
Claims 1-3, 5-12 and 14-20 are subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Relevant Art
The following relevant art was previously cited on Form PTO-892 on 9/11/25. It is cited in this office as a reference table for the Young Modulus and Thermal Expansion values of elements.
Young Modulus of Elements (2025) (retrieved from https://periodictable.com/Properties/A/YoungModulus.v.wt.html)
Thermal Expansion of the Elements (2025) (retrieved from https://periodictable.com/Properties/A/ThermalExpansion.v.wt.html)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-10 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US Publication No. 2019/0221520 A1.
Regarding claims 1-3:
Kim does not expressly disclose the formula recited in claim 1.
0.7×(0.0069E2−1.1498E+59.661)≤CTE≤1.3×(0.0069E2−1.1498E+59.661),
However, it would have been obvious to one of ordinary skill in the art to form the first conductive pad to have a first coefficient of thermal expansion (CTE) and a first Young's modulus (E) that conforms to the formula because Kim discloses materials that satisfy the equation.
For example, Kim discloses materials such as gold (Au) or aluminum (Al) that have a coefficient of thermal expansion (CTE) and Young's modulus (E) that satisfy the equation in claim 1. See a table of coefficient of thermal expansion (CTE) and Young's modulus (E) values for materials provided in the Relevant Art section above.
In particular, Kim discloses materials such a s gold (Au) or aluminum (Al) that have a coefficient of thermal expansion (CTE) and Young's modulus (E) that falls within the ranges of claims 2-3.
Thus, Kim teaches:
1. An electronic device, comprising (see figs. 8-9):
a redistribution structure (200/240);
an electronic unit (e.g. bottom 100/116);
a first conductive pad (118P; e.g. gold (Au) at para. [0035]) disposed between the redistribution structure and the electronic unit, and the electronic unit (e.g. bottom 100/116) is electrically connected to the redistribution structure (200/240) through the first conductive pad, and
a second conductive pad (230; corresponds to pad 115 in fig. 4; e.g. aluminum (Al) at para. [0026]) disposed between the first conductive pad (118P) and the electronic unit (e.g. bottom 100/116), wherein in a direction perpendicular to a normal direction of the electronic device, there is a distance between a centerline (BCL2, BCL3) of the first conductive pad (118P) and a centerline of the second conductive pad (230),
wherein the first conductive pad (118P; e.g. gold (Au) at para. [0035]) has a first coefficient of thermal expansion and a first Young's modulus, and the first coefficient of thermal expansion and the first Young's modulus conform to the following formula:
0.7×(0.0069E2−1.1498E+59.661)≤CTE≤1.3×(0.0069E2−1.1498E+59.661),
wherein CTE is the first coefficient of thermal expansion, and E is the first Young's modulus in the formula. See Kim at para. [0001] – [0102], figs. 1-9.
2. The electronic device as claimed in claim 1, wherein the first coefficient of thermal expansion of the first conductive pad (118P) is greater than or equal to 10 ppm/° C. and less than or equal to 43.6 ppm/° C (See a table of coefficient of thermal expansion (CTE) values for materials provided in the Relevant Art section above. The units ppm/° K is equivalent to ppm/° C for conversion purposes. The material gold (Au) has a CTE of 14.2 ppm/° K. )
3. The electronic device as claimed in claim 1, wherein the first Young's modulus of the first conductive pad (118P) is greater than or equal to 17 GPa and less than or equal to 89 GPa (See a table of Young's modulus (E) values for materials provided in the Relevant Art section above. The material silver (Au) has a E of 78 GPa.)
5. The electronic device as claimed in claim 1, wherein the second conductive pad (230) has a second coefficient of thermal expansion (e.g. Al has a CTE of 23.1 ppm/° K), and the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion (e.g. first conductive pad 118p is gold (Au) that has a CTE of 14.2 ppm/° K. )
6. The electronic device as claimed in claim 1, further comprising: a first insulating layer (150) disposed adjacent to the first conductive pad (118p) and the second conductive pad (230), wherein the first conductive pad (118p) is in contact with the first insulating layer (150) and the second conductive pad (230), fig. 8.
7. The electronic device as claimed in claim 1, wherein the second coefficient of thermal expansion is greater than or equal to 15 ppm/° C. and less than or equal to 30 ppm/° C (e.g. Al has a CTE of 23.1 ppm/° K)
8. The electronic device as claimed in claim 1, wherein the second conductive pad has a first width, and the first conductive pad has a second width, and the first width is greater than the second width (e.g. See fig. 5 and para. [0063] disclosing dimension b’ > b.)
Regarding claim 9:
Kim teaches in fig. 5 that the dimension a is a result effective variable at para. [0064] – [0065].
It would have been obvious to one having ordinary skill in the art to “wherein a distance between a centerline of the first conductive pad and a centerline of the second conductive pad does not exceed ⅙ of the first width”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Kim further teaches:
10. The electronic device as claimed in claim 1, further comprising: a packaging structure (e.g. upper chips 100) electrically connected to the redistribution structure (200/240).
19. The electronic device as claimed in claim 1, wherein the redistribution structure (200/240) comprises: at least one conductive layer and at least one insulating layer, and the at least one conductive layer and the at least one insulating layer are stacked alternately, para. [0089].
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claim 1 above, in view of Chen et al., US Publication No. 2020/0365571 A1 (of record).
Regarding claim 11:
Kim teaches all the limitations of claim 1 above and further teaches:
wherein the packaging structure comprises:
a chip (e.g. upper chips 100); and
a protective layer (e.g. layer around the stack of four chips 100) surrounding the chip, …the first coefficient of thermal expansion (e.g. gold (Au) has a CTE of 14.2 ppm/° K. )
Kim does not expressly teach:
the protective layer has a third coefficient of thermal expansion, and the third coefficient of thermal expansion is smaller than the first coefficient of thermal expansion.
In an analogous art, Chen teaches:
(see fig.1E) a chip (200, 204); and
a protective layer (110) surrounding the chip, wherein the protective layer has a third coefficient of thermal expansion (e.g. 8 ppm/° C. to 15 ppm/° C), para. [0040]. Also see para. [0023] – [0043].
One of ordinary skill in the art modifying Kim with Chen would form:
the third coefficient of thermal expansion (e.g. 8 ppm/° C. to 15 ppm/° C, as taught by Chen) is smaller than the first coefficient of thermal expansion (e.g. gold (Au) has a CTE of 14.2 ppm/° K, as taught by Kim)
Chen further teaches:
12. The electronic device as claimed in claim 11, wherein the third coefficient of thermal expansion is greater than or equal to 6 ppm/° C. and less than or equal to 24 ppm/° C (e.g. 8 ppm/° C. to 15 ppm/° C), para. [0040].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Chen to “…prevent the warpage or stress by reducing the CTE mismatch”. See Chen at para. [0040].
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claim 1 above, in view of Yin et al., US Publication No. 2005/0028361 A1 (of record).
Regarding claim 14:
Kim teaches all the limitations of claim 1 above, and further teaches:
further comprising: a first insulating layer (150) disposed adjacent to the first conductive pad (118P), wherein the first insulating layer has a fourth coefficient of thermal expansion, fig. 8.
Kim is silent regarding a numerical value for the fourth coefficient of thermal expansion .
In Kim’s fig. 8, the first insulating layer (150) forms an underfill of the chip stack(100).
In an analogous art, Yin teaches:
(see fig. 4e) a first insulating layer (412) disposed adjacent to the first conductive pad (400, 415), wherein the first insulating layer has a fourth coefficient of thermal expansion (e.g. 3 ppm/° C. to 30 ppm/° C), para. [0040]. Also see para. [0034] – [0041].
One of ordinary skill in the art modifying Kim with Yin would form:
and the fourth coefficient of thermal expansion (e.g. 3 ppm/° C, as taught by Yin) is smaller than the first coefficient of thermal expansion (e.g. gold (Au) has a CTE of 14.2 ppm/° K, as taught by Kim)
Yin further teaches:
15. The electronic device as claimed in claim 14, wherein the fourth coefficient of thermal expansion is greater than or equal to 5 ppm/° C. and less than or equal to 12 ppm/° C expansion (e.g. 3 ppm/° C. to 30 ppm/° C at para. [0040])
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Yin because “The use of filled underfill allows for optimizing the coefficient of thermal expansion as needed which can result in improved reliability of the assembled device following mating of the chip or die 410 to a substrate.” See Yin at para. [0039].
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claim 1 above, in view of Sugimoto et al, JP 2005056958 A (of record, see attached English machine translation).
Regarding claim 16:
Kim teaches all the limitations of claim 1 above, and further teaches wherein the redistribution structure (240 of 200/240) comprises: a second insulating layer (240), wherein the first conductive pad (118P) is disposed on the second insulating layer, fig. 8.
Kim is silent regarding the second insulating layer has a fifth coefficient of thermal expansion smaller than the first coefficient of thermal expansion.
In an analogous art, Sugimoto teaches:
16. The electronic device as claimed in claim 1, (see figs. 1-2) wherein the redistribution structure (10) comprises: a second insulating layer (11), wherein the first conductive pad (GPA1-GPA12) is disposed on the second insulating layer, the second insulating layer has a fifth coefficient of thermal expansion (e.g. 3 to 8 ppm/° C). See Sugimoto at English machine translation page 7.
One of ordinary skill in the art modifying Kim with Sugimoto would form:
and the fifth coefficient of thermal expansion (e.g. 3 to 8 ppm/° C, as taught by Sugimoto) is smaller than the first coefficient of thermal expansion (e.g. gold (Au) has a CTE of 14.2 ppm/° K, as taught by Kim). Note the units ppm/° K is equivalent to ppm/° C for conversion purposes.
Regarding claim 17:
Sugimoto further teaches:
17. The electronic device as claimed in claim 16, wherein the fifth coefficient of thermal expansion is greater than or equal to 5 ppm/° C. and less than or equal to 25 ppm/° C (e.g. 3 to 8 ppm/° C at English machine translation page 7).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Sugimoto “…to alleviate thermal expansion strain”. See Sugimoto at English machine translation page 7.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claim 1 above, in view of Cobb et al., US Publication No. 2022/0130738 A1 (of record).
Regarding claim 18:
Kim teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the redistribution structure comprises: a thin-film transistor unit electrically connected to the first conductive pad.
In an analogous art, Cobb teaches:
(see figs. 5 and 7) wherein the redistribution structure (110) comprises: a thin-film transistor unit (e.g. active components 104, and see TFT at para. [0091]) electrically connected to a first conductive pad (108). See Cobb at para. [0058] – [0061], [0086].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Cobb because incorporating “…active 104 and passive 106 components into the fabric (i.e. the substrate or member 102) of the interposer 100 allowing for further system volume and assembly cost reductions. For example, discrete passive/active components may be replaced with integrated equivalents, therefore, eliminating one or more assembly steps, as well as, reducing the cost of materials and allowing for optimal component positioning (e.g. immediately adjacent to an IC terminal).” See Cobb at para. [0061].
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claim 1 above, in view of Low et al., US Publication No. 2022/0208646 A1 (of record).
Regarding claim 19:
Kim teaches all the limitations of claim 1 above, and in an alternative interpretation of claim 19 the reference Low is being introduced.
In an analogous art, Low teaches:
19. The electronic device as claimed in claim 1, (see fig. 6B) wherein the redistribution structure (600) comprises: at least one conductive layer (611, 695-1, 695-2, 697) and at least one insulating layer (692-1, 692-2), and the at least one conductive layer and the at least one insulating layer are stacked alternately. See Low at para. [0084] – [0087].
Regarding claim 20:
Low further teaches:
20. The electronic device as claimed in claim 19, wherein one of the conductive layers (611, 695-1, 695-2, 697) is a dummy pattern (e.g. dummy pads may be left electrical floating, para. [0087])
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Low because dummy pattern enables the redistribution structure to be customized for signal, ground, voltage or electrically floating functions. See Low at para. [0087].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
23 February 2026