DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 8/25/2025 "Reply" elects without traverse and identifies claims 1-9 and 18-20 as being drawn to Group I. Accordingly, Examiner has withdrawn claims 10-17 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
The 6/25/2025 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US Pub. No. 2019/0096879).
Regarding claim 1, in FIG. 6, Chen discloses a compound semiconductor heterostructure transistor device comprising: a substrate (100, paragraph [0021]); a dopant layer (paragraphs [0027]-[0028]) implanted in the substrate, wherein the dopant layer includes a p-type material forming a first region (100a/100b) and an n-type material forming a second region (100b/100a), and wherein the first region is adjacent the second region; and a first semiconductor material layer (106, paragraph [0025]) formed over a second semiconductor material layer (104, paragraph [0024]) to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel (105, paragraph [0024]), wherein the 2DEG channel is more electrically conductive than either the first semiconductor material layer or the second semiconductor material layer.
Regarding claim 2, in FIG. 6, Chen discloses that the substrate includes silicon carbide (paragraph [0021]).
Regarding claim 3, in FIG. 6, Chen discloses a gate electrode (130) electrically coupled (capacitively) with the first semiconductor material layer; a source electrode (S/110) electrically coupled with the first region (100a) of the dopant layer and to the 2DEG channel; and a drain electrode (D/120) electrically coupled with the second region (100b) of the dopant layer and to the 2DEG channel.
Regarding claim 9, in FIG. 6, Chen discloses that the first region and the second region form a p-n junction diode (paragraph [0037]).
Regarding claim 18, in FIG. 6, Chen discloses a compound semiconductor heterostructure transistor device comprising: a substrate (100); a dopant layer (paragraphs [0027]-[0028]) implanted in the substrate, wherein the dopant layer includes a p-type material (100a/100b) forming a first region and an n-type material (100b/100a) forming a second region, wherein the first region is adjacent the second region, and wherein the first region and the second region form a p-n junction diode; a nucleation layer (102, paragraph [0023]) formed over the dopant layer; and a first semiconductor material layer (106, paragraph [0025]) formed over a second semiconductor material layer (104, paragraph [0024]) to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel (105, paragraph [0024]), wherein the 2DEG channel is more electrically conductive than either the first semiconductor material layer or the second semiconductor material layer, and wherein the second semiconductor material layer is formed over the nucleation layer.
Regarding claim 20, in FIG. 6, Chen discloses that the substrate includes silicon carbide (paragraph [0021]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US Pub. No. 2019/0096879) in view of Kanamura (US Pub. No. 2007/0228415).
Regarding claims 4-7, Chen appears not to explicitly disclose that the source/drain electrode includes a first material and a second material, wherein the first material is different from the second material.
The art however well recognized source/drain electrodes comprising a stack of Ta/Al/Ni to be suitable for use as source/drain electrodes in a HEMT device. See, for example, Kanamura, paragraph [0044].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the source/drain electrodes from a stack of Ta/Al/Ni for its recognized suitability as source/drain electrodes in a HEMT device. In doing so, the source/drain electrode includes a first material and a second material, wherein the first material is different from the second material, wherein the first material includes nickel, and wherein the second material includes aluminum.
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US Pub. No. 2019/0096879) in view of Gao (US Patent No. 10,128,228).
Regarding claims 8 and 19, Chen appears not to explicitly disclose a field plate formed over the first semiconductor material layer.
However, in FIG. 1 and col. 5, line 63 to col. 6, line 55, Gao discloses a similar transistor device comprising a field plate (124) formed over a first semiconductor material layer (110) to deplete a two-dimensional charge carrier gas (112) during an OFF state of the transistor device or during a transition to an OFF state of the transistor device.
To deplete the two-dimensional charge carrier gas during an OFF state of the transistor device or during a transition to an OFF state of the transistor device it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a field plate formed over the first semiconductor material layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891