CTFR 18/069,804 CTFR 100025 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment The Amendment filed on 03/03/2026 has been entered. Claims 1-19 remain pending in the application. Claims 3, 6, 7, 10, 12, 14, 15 and 19 have been withdrawn in the Response to Election/Restriction filed on 11/10/2025. Applicant’s amendments have overcome the 112(b) rejection of claim 17 previously set forth in the Non-Final Office Action mailed on 12/03/2025 . Information Disclosure Statement The prior art documents submitted by applicant in the Information Disclosure Statement filed on 12/11/2025 has been considered and made of record. Claim Rejections - 35 USC § 112(b) 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the new limitation “the second joining material extending between two adjacent support wires of the plurality of support wires and having a constant height between the two adjacent support wires”. The limitation can be interpreted as: the second joining material having a constant height in an entire region between the two adjacent support wires, or having a constant height in a part of a region between the two adjacent support wires. As shown in Fig.2 (same arguments apply to other figures showing similar cross-sections), each support wire, element #11, forms a loop , where the distal end portions, element #11b, are in contact with the semiconductor element #1, and the vertex portion, element #11a, is in contact with the electrode plate, element #7. In the region between the vertex of the left wire and the right distal end portion of the left wire (or the region between the vertex of the right wire and the left distal end portion of the right wire), as shown in Fig.2, the height of the region between the two wires varies according to the shape of the wire and, as a result, the height of the second joining material also varies in the same way. Therefore, the second joining material, element #12, does not have a constant height in an entire region between the two wires. For the purpose of examination, claim 1 will be interpreted as: A semiconductor device, comprising: an insulating substrate; a semiconductor element joined onto the insulating substrate with a first joining material interposed therebetween; an electrode plate provided above the semiconductor element; a plurality of support wires that are provided between the semiconductor element and the electrode plate in contact with the semiconductor element and the electrode plate; and an electrically conductive second joining material that is provided on the semiconductor element and joins the semiconductor element and the electrode plate, the second joining material extending between two adjacent support wires of the plurality of support wires and having a constant height in a part of a region between the two adjacent support wires of the plurality of support wires without extending beyond the two adjacent support wires, the second joining material positioned directly between the semiconductor element and the electrode plate. Claims 2, 11, 13, 16, 17, 18 are also rejected as being depended on claim 1. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated Kumbhat et al., (United States Patent Number, US 10,163,808 B2), hereinafter referenced as Kumbhat. Regarding claim 8, Kumbhat teaches a semiconductor device, comprising: a circuit pattern (Fig.1, element #127a and #127b); an insulating member provided below the circuit pattern (Fig.1, element #110 is made of glass, column 4, rows 1-3); a semiconductor element (Fig.1, element #122) joined onto the circuit pattern with a first joining material interposed therebetween (Fig.1, element #127b); an electrode plate provided above the insulating member and the semiconductor element (Fig.1, element #145), a plurality of support wires that are provided between the insulating member and the electrode plate (Fig.1, element #142c, see also Fig.2 for the plurality of wires) in contact with the insulating member and the electrode plate (column 4, rows 3-9); and a second joining material that is provided on the semiconductor element and joins the semiconductor element and the electrode plate (Fig.1, element #130). Regarding claim 9, Kumbhat teaches the semiconductor device of claim 8 as set forth in the anticipation rejection. Kumbhat further teaches the semiconductor device according to claim 8, wherein each of the support wires has a distal end portion at both ends thereof and a vertex portion that includes a vertex of the support wire and is provided between the distal end portions of the support wire, the distal end portions are in contact with the insulating member, and the vertex portion is in contact with the electrode plate (Fig.2D, top wires of elements #241, #243 and #244). Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 2, 11, 13, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hohlfeld et al., (United States Patent Number, US 10096584 B2) hereinafter referenced as Hohlfeld, in view of disclosed prior art, Junji et al., (Japanese Patent Publication Number, JP 2021019139 A, hereinafter referenced as Junji, and in view of disclosed prior art, Fukuoka et al., (WIPO Publication Number, WO2021065736 A1; the text of United States application of the same invention, US 2022/0223544 A1, will be used for the rejection below) hereinafter referenced as Fukuoka . Regarding claim 1, Hohlfeld teaches a semiconductor device, comprising: an insulating substrate (Fig.9, element #2); a semiconductor element joined onto the insulating substrate with a first joining material interposed therebetween (Fig.9, element #10 on the left side of the figure, column 2, rows 49-57); an electrode plate provided above the semiconductor element (Fig.9, formed by element #5, #6 and #7 located above element #10 on the left side of the figure); a support wire provided between the semiconductor element and the electrode plate in contact with the semiconductor element and the electrode plate (Fig.9, elements #3 above element #10 t on the left side of the figure). Hohlfeld does not teach a plurality of support wires that are provided between the semiconductor element and the electrode plate in contact with the semiconductor element and the electrode plate. Junji teaches a plurality of support wires that are provided between the semiconductor element and the electrode plate in contact with the semiconductor element and the electrode plate (Fig.1, elements #11 are provided between semiconductor element #4 and electrode plate, element #8, paragraph [0041], rows 6-8 and 11-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Junji and disclose a plurality of support wires that are provided between the semiconductor element and the electrode plate in contact with the semiconductor element and the electrode plate. As disclosed by Junji, this increases the stability and support for the electrode plate. Hohlfeld does not teach an electrically conductive second joining material that is provided on the semiconductor element and joins the semiconductor element and the electrode plate, the second joining material extending between two adjacent support wires of the plurality of support wires and having a constant height in a part of a region between the two adjacent support wires of the plurality of support wires without extending beyond the two adjacent support wires, the second joining material positioned directly between the semiconductor element and the electrode plate. Junji teaches an electrically conductive second joining material that is provided on the semiconductor element and joins the semiconductor element and the electrode plate (Fig.1, element #6). The combination of Hohlfeld and Junji does not teach an electrically conductive second joining material that is provided on the semiconductor element and joins the semiconductor element and the electrode plate, the second joining material extending between two adjacent support wires of the plurality of support wires and having a constant height in a part of a region between the two adjacent support wires of the plurality of support wires without extending beyond the two adjacent support wires, the second joining material positioned directly between the semiconductor element and the electrode plate. Fukuoka teaches an electrically conductive second joining material (Fig.39, element #81 is solder) that is provided on the semiconductor element (Fig.39, element #30) and joins the semiconductor element and the electrode plate (Fig.39, element #81 joins element #30 with the electrode plate, element #55), the second joining material extending between two adjacent support wires of the plurality of support wires and having a constant height in a part of a region between the two adjacent support wires of the plurality of support wires (Fig.1, the height of element #81, in the region between the furthest right point of left wire, element #90, and the leftmost point of the right wire is constant; note that the wires can have the shape as shown in Fig.28) without extending beyond the two adjacent support wires (Fig.39, element #81 does not extend beyond the two wires in the vertical direction), the second joining material positioned directly between the semiconductor element and the electrode plate (Fig.81 is directly between elements #30 and #55). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fukuoka and disclose an electrically conductive second joining material that is provided on the semiconductor element and joins the semiconductor element and the electrode plate, the second joining material extending between two adjacent support wires of the plurality of support wires and having a constant height in a part of a region between the two adjacent support wires of the plurality of support wires without extending beyond the two adjacent support wires, the second joining material positioned directly between the semiconductor element and the electrode plate. The second conductive joining material increases the electrically conductive contact area between the semiconductor electrode and the electrode plate, thus reducing the contact resistance and increasing the contact reliability. Regarding claim 2, the combination of Hohlfeld, Junji and Fukuoka teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Hohlfeld further teaches the semiconductor device according to claim 1, wherein each of the support wires has a distal end portion at both ends thereof and a vertex portion that includes a vertex of the support wire and is provided between the distal end portions of the support wire, the distal end portions are in contact with the semiconductor element, and the vertex portion is in contact with the electrode plate (Fig.1, elements #3). Regarding claim 11, the combination of Hohlfeld, Junji and Fukuoka teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Fukuoka further teaches the semiconductor device according to claim 1, wherein three or more support wires are provided on the semiconductor element (Fig.20 elements #90). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fukuoka and disclose wherein three or more support wires are provided on the semiconductor element. Using three or more wires, disposed in corners of the semiconductor die and electrode plate, as shown by Fukuoka in Fig.15 and 16, spreads the contact pressure force over the semiconductor area. Regarding claim 13, the combination of Hohlfeld, Junji and Fukuoka teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Hohlfeld further teaches t he semiconductor device according to claim 1, wherein each of the support wires has a single vertex portion (Fig.1, elements #3). Regarding claim 16, the combination of Hohlfeld, Junji and Fukuoka teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Junji further teaches the semiconductor device of claim 1, wherein each of the support wires is at least partially embedded in the second joining material (Fig.1, the wires are embedded in the second joining material, element #6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Junji and disclose wherein each of the support wires is at least partially embedded in the second joining material. When embedding the contact points of the wire, the second conductive joining material increases the contact area between the wire and semiconductor electrodes and the electrode plate, thus reducing the contact resistance and increasing the contact reliability. Regarding claim 18, the combination of Hohlfeld, Junji and Fukuoka teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Hohlfeld does not teach a power conversion apparatus, comprising: a main conversion circuit that includes the semiconductor device according to claim 1 and converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit. Junji further teaches a power conversion apparatus (Fig.11, paragraph [0094]), comprising: a main conversion circuit (Fig.11, element #501, paragraph [0098], row 1) that includes the semiconductor device according to claim 1 (paragraph [0097], rows 9-11) and converts input power and outputs the converted power (Fig.11, paragraph [0095], rows 3-6); a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device (paragraph [0098], rows 1-6); and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit (paragraph [0098], rows 7-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Junji and disclose a power conversion apparatus, comprising: a main conversion circuit that includes the semiconductor device according to claim 1 and converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit. As disclosed by Junji, the power conversion apparatus can be applied to applications involving a DC/DC converter or an AC/DC converter (paragraph [0101]) . 07-21-aia AIA Claim s 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Hohlfeld, in view Satoshi, (Japanese Patent Publication Number, JP 3632960 B2) hereinafter referenced as Satoshi . Regarding claim 4, Hohlfeld teaches a semiconductor device, comprising: a circuit pattern (Fig.9, element #21); an insulating member provided below the circuit pattern (Fig.9, element #20); a semiconductor element joined onto the circuit pattern with a first joining material interposed therebetween (Fig.9, element #10 on the left side of the figure, column 2, rows 49-57) , the semiconductor element comprising a switching element or a diode (column 2, rows 44-47); an electrode plate provided above the circuit pattern and the semiconductor element (Fig.9, formed by element #5, #6 and #7 located above element #10 on the left side of the figure) ; a plurality of wires that are provided between the circuit pattern and the electrode plate in contact with the circuit pattern (column 7, rows 1-3 and rows 36-38) and a second joining material that is provided on the semiconductor element and joins the semiconductor element and the electrode plate (Fig.9, element #4). Hohlfeld teaches the bonding wires can be formed as bond loops (column 7, rows 8-9) Hohlfeld does not teach the wires that are in contact with the electrode plate. Satoshi teaches a plurality of support wires that are provided between the circuit pattern and the electrode plate in contact with the circuit pattern and the electrode plate (Fig.2 elements #5, paragraph [0019], rows 3-4, and paragraph [0021], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Satoshi and disclose a plurality of support wires that are provided between the circuit pattern and the electrode plate in contact with the circuit pattern and the electrode plate. As disclosed by Satoshi, these wires act as support wires for the electrode plate (paragraph [0018], rows 6-8) and allow using the circuit pattern to bias the electrode plate. Regarding claim 5, the combination of Hohlfeld and Satoshi teaches the semiconductor device of claim 4 as set forth in the obviousness rejection. Satoshi further teaches the semiconductor device according to claim 4, wherein each of the support wires has a distal end portion at both ends thereof and a vertex portion that includes a vertex of the support wire and is provided between the distal end portions of the support wire, the distal end portions are in contact with the circuit pattern, and the vertex portion is in contact with the electrode plate (Fig.2, element #5, paragraph [0021], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Satoshi and disclose wherein each of the support wires has a distal end portion at both ends thereof and a vertex portion that includes a vertex of the support wire and is provided between the distal end portions of the support wire, the distal end portions are in contact with the circuit pattern, and the vertex portion is in contact with the electrode plate. As disclosed by Satoshi, this allows connecting tow electrode pads of the circuit pattern together using the same wire, which can be used to grounding together the different parts of the circuit patter and the electrode, with a reduce number of wires . 07-21-aia AIA Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over disclosed prior art, Hohlfeld in view of Junji, Fukuoka and in view of Bayerer et al., (United States Patent Number, US 8319335 B2) hereinafter referenced as Bayerer . Regarding claim 18, the combination of Hohlfeld, Junji and Fukuoka teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Hohlfeld further teaches the semiconductor device according to claim 1, including a circuit pattern and an insulating member positioned below the circuit pattern (Fig.9 circuit pattern, element #21 and insulating member, element #20). The combination of Hohlfeld, Junji and Fukuoka does not teach the semiconductor device according to claim 1,wherein the insulating substrate or the insulating member has a heat radiation member on a lower surface thereof. Bayerer teaches wherein the insulating substrate or the insulating member has a heat radiation member on a lower surface thereof (Fig.4, insulating member, element #20, is a ceramic, has a heat radiation member, element #200, on the lower surface, column 1, rows 36 and 41). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bayerer and disclose wherein the insulating substrate or the insulating member has a heat radiation member on a lower surface thereof. As disclosed by Bayerer, the heat sink helps cool the semiconductor elements connected to it (column 1, rows 20-24). Response to Arguments Applicant’s arguments filed on 03/03/2026 have been fully considered but they are not persuasive. Applicant’s arguments with respect to claims have been considered but are moot because the new grounds of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00AM -5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/069,804 Page 2 Art Unit: 2899 Application/Control Number: 18/069,804 Page 4 Art Unit: 2899 Application/Control Number: 18/069,804 Page 5 Art Unit: 2899 Application/Control Number: 18/069,804 Page 6 Art Unit: 2899 Application/Control Number: 18/069,804 Page 7 Art Unit: 2899 Application/Control Number: 18/069,804 Page 8 Art Unit: 2899 Application/Control Number: 18/069,804 Page 9 Art Unit: 2899 Application/Control Number: 18/069,804 Page 10 Art Unit: 2899 Application/Control Number: 18/069,804 Page 11 Art Unit: 2899 Application/Control Number: 18/069,804 Page 12 Art Unit: 2899 Application/Control Number: 18/069,804 Page 13 Art Unit: 2899 Application/Control Number: 18/069,804 Page 14 Art Unit: 2899 Application/Control Number: 18/069,804 Page 15 Art Unit: 2899
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