DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 7 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching Tee et al. (US 2013/0320485 A1; hereinafter “Ching”).
Regarding claim 7, Ching teaches a semiconductor device, comprising: a substrate (604) including a recessed area (a recessed region of 604 where 614 is formed therein) within the substrate; an insulating material (614) formed in the recessed area with a surface of the insulating material co-planar with a surface of the substrate (a top surface of 614 is co-planar with a top surface of 604); and a semiconductor layer (a semiconductor layer including 606, 613, 620, and 624) formed over the substrate and the insulating material, wherein the semiconductor layer includes a first type of semiconductor material (an n-drift 620) and a second type of semiconductor material (a p-well 624) opposite the first type of semiconductor material (Figs. 6-7 and paragraphs 65-71).
Claims 1-2, 5-8, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ning (US 2018/0012966 A1).
Regarding claim 1, Ning teaches a power transistor including a plurality of cells (20A and 20B), each cell comprising: a substrate (2 and 3A) including a notch (32) formed in the substrate (paragraphs 34-37); an insulating material (24 including 24A and 24B) formed within the notch with a surface of the insulating material co-planar with a surface of the substrate (a top surface of 24B of 24 is co-planar with a top surface of 3A) (paragraphs 38-39); and a semiconductor layer (34A and 34B) formed over the substrate and the insulating material, wherein the semiconductor layer includes a first type of semiconductor material (an n-type source/drain 6/9) and a second type of semiconductor material (a p-type body contact 5) opposite the first type of semiconductor material to form the power transistor (Figs. 5-11 and paragraphs 3 and 34-49).
Ning teaches each and every limitation of the power transistor including the insulating material within the notch identically as claimed as discussed above. As such, the claimed property/function of the power transistor including the insulating material within the notch (i.e., “the power transistor with a reduced output capacitance by nature of the insulating material within the notch”) is presumed to be inherent: Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Regarding claim 2, Ning teaches wherein a width of the insulating material (a width of 24) within the notch is less than a width of the semiconductor layer (a width of 34A and 34B combined) so that a portion of the substrate extends to the semiconductor layer (Fig. 11).
Regarding claim 5, Ning teaches wherein the insulating material includes a first thickness (a thickness of 24A) and a second thickness (a combined thickness of 24A and 24B) greater than the first thickness within the notch (Fig. 8).
Regarding claim 6, Ning teaches wherein the insulating material includes an oxide (paragraphs 38-39).
Regarding claim 7, Ning teaches a semiconductor device, comprising: a substrate (2 and 3A) including a recessed area (32) within the substrate (paragraphs 34-37); an insulating material (24 including 24A and 24B) formed in the recessed area with a surface of the insulating material co-planar with a surface of the substrate (a top surface of 24B of 24 being co-planar with a top surface of 3A) (paragraphs 38-38); and a semiconductor layer (34A and 34B) formed over the substrate and the insulating material, wherein the semiconductor layer includes a first type of semiconductor material (an n-type source/drain 6/9) and a second type of semiconductor material (a p-type body contact 5) opposite the first type of semiconductor material (Figs. 5-11 and paragraphs 3 and 34-49).
Regarding claim 8, Ning teaches wherein a width of the insulating material (a width of 24) within the recessed area is less than a width of the semiconductor layer (a width of 34A and 34B combined) so that a portion of the substrate extends to the semiconductor layer (Fig. 11).
Regarding claim 11, Ning teaches wherein the insulating material includes a first thickness (a thickness of 24A) and a second thickness (a combined thickness of 24A and 24B) greater than the first thickness within the recessed area (Fig. 8).
Regarding claim 12, Ning teaches wherein the insulating material includes an oxide (paragraphs 38-39).
Claims 14 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Terashima (US 2012/0049240 A1).
Regarding claim 14, Terashima teaches a method of making a semiconductor device, comprising: providing a substrate (1); forming in a recessed area (a recessed region of 1 where 3 is formed therein) within the substrate; and forming an insulating material (3) in the recessed area within the substrate to completely fill the recessed area with a surface of the insulating material co-planar with a surface of the substrate (a top surface of a lower center portion of 3 is co-planar with a top surface of 1); and forming a semiconductor layer (a semiconductor layer including 2 and 4) over the substrate and insulating material, wherein the semiconductor layer includes a first type of semiconductor material (an n-type semiconductor layer 2) and a second type of semiconductor material (a p-type impurity region 4) opposite the first type of semiconductor material (Fig. 3 and paragraph 93).
Regarding claim 17, Terashima teaches wherein the recessed area includes a step (a stepped structure of 3) (Fig. 3).
Regarding claim 18, Terashima teaches wherein the insulating material includes a first thickness (a thickness of 3a) and a second thickness (a thickness of 3b) greater than the first thickness within the recessed area (Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-8, and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0245041 A1; hereinafter “Chen”) in view of Lin et al. (US 2012/0286359 A1; hereinafter “Lin”).
Regarding claim 1, Chen teaches a power transistor including a plurality of cells (104 including two transistors), each cell comprising: a substrate (102a) including a notch formed in the substrate (a recessed region of 102a where 106 and 108 are formed therein); an embedded material (106 and 108) formed within the notch with a surface of the insulating material co-planar with a surface of the substrate (a top surface of 102a within the recessed region is co-planar with a bottom surface of 108 due to a direct interface therebetween); and a semiconductor layer (102b) formed over the substrate and the embedded material, wherein the semiconductor layer includes a first type of semiconductor material (124 having an n-type conductivity) and a second type of semiconductor material (128 having a p-type conductivity) opposite the first type of semiconductor material to form the power transistor (Fig. 1 and paragraphs 3 and 34-49).
Chen does not explicitly teach that the embedded material is an insulating material. Lin teaches a semiconductor device, comprising: an embedded layer 320 in a substrate 210 formed of an insulating layer such as an oxide layer as one of available material choices for forming the embedded layer for avoiding circuit leakage (Fig. 3 and paragraphs 4-5, 19-24, and 26). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Chen with Lin in order to utilize one of available material choices for the embedded layer in the substrate for avoiding circuit leakage.
Furthermore, Chen in view of Lin teaches each and every limitation of the power transistor including the insulating material within the notch identically as claimed as discussed above. As such, the claimed property/function of the power transistor including the insulating material within the notch (i.e., “the power transistor with a reduced output capacitance by nature of the insulating material within the notch”) is presumed to be at least obvious: Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Regarding claim 2, Chen in view of Lin teaches wherein a width of the insulating material (a width of 106/108) within the notch is less than a width of the semiconductor layer (a width of 102b) so that a portion of the substrate extends to the semiconductor layer (Chen, Fig. 1 and Lin, Fig. 3, 320).
Regarding claim 4, Chen teaches wherein the notch includes a step (Fig. 1 and paragraph 44).
Regarding claim 5, Chen in view of Lin teaches wherein the insulating material includes a first thickness (a thickness of 108) and a second thickness (a thickness of 106 and 108) greater than the first thickness within the notch (Chen, Fig. 1 and Lin, Fig. 3, 320).
Regarding claim 6, Lin teaches wherein the insulating material includes an oxide (paragraph 24).
Regarding claim 7, Chen teaches a semiconductor device, comprising: a substrate (102a) including a recessed area within the substrate (a recessed region of 102a where 106 and 108 are formed therein); an embedded material (106 and 108) formed in the recessed area with a surface of the insulating material co-planar with a surface of the substrate (a top surface of 102a within the recessed region is co-planar with a bottom surface 108 due to a direct interface therebetween); and a semiconductor layer (102b) formed over the substrate and the embedded material, wherein the semiconductor layer includes a first type of semiconductor material (124 having an n-type conductivity) and a second type of semiconductor material (128 having a p-type conductivity) opposite the first type of semiconductor material (Fig. 1 and paragraphs 3 and 34-49).
Chen does not explicitly teach that the embedded material is an insulating material. Lin teaches a semiconductor device, comprising: an embedded layer 320 in a substrate 210 formed of an insulating layer such as an oxide layer as one of available material choices for forming the embedded layer for avoiding circuit leakage (Fig. 3 and paragraphs 4-5, 19-24, and 26). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Chen with Lin in order to utilize one of available material choices for the embedded layer in the substrate for avoiding circuit leakage.
Regarding claim 8, Chen in view of Lin teaches wherein a width of the insulating material (a width of 106/108) within the recessed area is less than a width of the semiconductor layer (a width of 102b) so that a portion of the substrate extends to the semiconductor layer (Chen, Fig. 1 and Lin, Fig. 3, 320).
Regarding claim 10, Chen teaches wherein the recessed area includes a step (Fig. 1 and paragraph 44).
Regarding claim 11, Chen in view of Lin teaches wherein the insulating material includes a first thickness (a thickness of 108) and a second thickness (a thickness of 106 and 108) greater than the first thickness within the recessed area (Chen, Fig. 1 and Lin, Fig. 3, 320).
Regarding claim 12, Lin teaches wherein the insulating material includes an oxide (paragraph 24).
Regarding claim 13, Chen teaches wherein the semiconductor layer includes a cell of a power transistor (a LDMOS transistor) (Fig. 1 and paragraph 37). Furthermore, for the limitation “the power transistor with a reduced output capacitance by nature of the insulating material within the recessed area”, see the rejection of claim 1 regarding the claimed property/function.
Claims 1, 7, 14-15, and 20-24 are rejected under 35 U.S.C. 103 as being unpatentable over Kao (US 2013/0207183 A1) in view of Lin.
Regarding claim 1, Kao teaches a power transistor including a plurality of cells (a LDMOS device each having a transistor with a gate), each cell comprising: a substrate (22) including a notch formed in the substrate (a recessed region of 22 where 24 is formed therein); an embedded material (24) formed within the notch with a surface of the insulating material co-planar with a surface of the substrate (a top surface of 24 is co-planar with a top surface of 22); and a semiconductor layer (52) formed over the substrate and the embedded material, wherein the semiconductor layer includes a first type of semiconductor material (26 having a first conductivity type) and a second type of semiconductor material (30 having a second conductivity type) opposite the first type of semiconductor material to form the power transistor (Fig. 10 and paragraphs 16-28).
Kao does not explicitly teach that the embedded material is an insulating material. Lin teaches a semiconductor device, comprising: an embedded layer 320 in a substrate 210 formed of an insulating layer such as an oxide layer as one of available material choices for forming the embedded layer for avoiding circuit leakage (Fig. 3 and paragraphs 4-5, 19-24, and 26). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kao with Lin in order to utilize one of available material choices for the embedded layer in the substrate for avoiding circuit leakage.
Furthermore, Kao in view of Lin teaches each and every limitation of the power transistor including the insulating material within the notch identically as claimed as discussed above. As such, the claimed property/function of the power transistor including the insulating material within the notch (i.e., “the power transistor with a reduced output capacitance by nature of the insulating material within the notch”) is presumed to be at least obvious: Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Regarding claim 7, Chen teaches a semiconductor device, comprising: a substrate (22) including a recessed area within the substrate (a recessed region of 22 where 24 is formed therein); an embedded material (24) formed in the recessed area with a surface of the insulating material co-planar with a surface of the substrate (a top surface of 24 is co-planar with a top surface of 22); and a semiconductor layer (52) formed over the substrate and the embedded material, wherein the semiconductor layer includes a first type of semiconductor material (26 having a first conductivity type) and a second type of semiconductor material (30 having a second conductivity type) opposite the first type of semiconductor material (Fig. 10 and paragraphs 16-28).
Kao does not explicitly teach that the embedded material is an insulating material. Lin teaches a semiconductor device, comprising: an embedded layer 320 in a substrate 210 formed of an insulating layer such as an oxide layer as one of available material choices for forming the embedded layer for avoiding circuit leakage (Fig. 3 and paragraphs 4-5, 19-24, and 26). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kao with Lin in order to utilize one of available material choices for the embedded layer in the substrate for avoiding circuit leakage.
Regarding claim 14, Kao teaches a method of making a semiconductor device, comprising: providing a substrate (22) (Fig. 3 and paragraph 20); forming in a recessed area (a recessed region of 22 where 24 is formed therein) within the substrate (Fig. 2 and paragraph 20); and forming an embedded material (24) in the recessed area within the substrate to completely fill the recessed area with a surface of the embedded material co-planar with a surface of the substrate (a top surface of 24 is co-planar with a top surface of 22) (Fig. 2 and paragraph 20); and forming a semiconductor layer (52) over the substrate and embedded material, wherein the semiconductor layer includes a first type of semiconductor material (26 having a first conductivity type) and a second type of semiconductor material (30 having a second conductivity type) opposite the first type of semiconductor material (Figs. 4-9 and paragraphs 20-27).
Kao does not explicitly teach that the embedded material is an insulating material. Lin teaches a semiconductor device, comprising: an embedded layer 320 in a substrate 210 formed of an insulating layer such as an oxide layer as one of available material choices for forming the embedded layer for avoiding circuit leakage (Fig. 3 and paragraphs 4-5, 19-24, and 26). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kao with Lin in order to utilize one of available material choices for the embedded layer in the substrate for avoiding circuit leakage.
Regarding claim 19, Lin teaches wherein the insulating material includes an oxide (paragraph 24).
Regarding claim 20, Kao teaches wherein the semiconductor layer includes a cell of a power transistor (paragraph 7).
Regarding claim 21, Kao in view of Lin teaches each and every limitation of the method of making the semiconductor device with the power transistor having the insulating material within the recessed area identically as claimed as discussed above. As such, the claimed property/function of the power transistor (i.e., “the power transistor has a reduced output capacitance by nature of the insulating material within the recessed area”) is presumed to be at least obvious: Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Regarding claims 22-24, while Kao in view of Lin does not explicitly teach that the insulating material has a thickness in the range of 1.0-2.0 µm, it would have been obvious to one of ordinary skill in the art to adjust the thickness of the insulating material by a routine experimentation in order to obtain the optimal and/or workable insulating material thickness range, including the claimed range of 1.0-2.0 µm while maintaining the function of the insulating material (i.e., avoiding the leakage): It has held that discovering an optimum or workable ranges involves only routine skill in the art. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation. In re Aller, 105 USPQ 233.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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