DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for the examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Balle (US 20200409877) in view of Singh(US 20090307442 A1) and further in view of WOO(US 20160259739 A1).
As to claim 1, Balle teaches processor(executed by one or more processors, para[0024], ln 6-8), one or more circuits to perform an application programming interface (API) to transfer information between memory of one or more first accelerators and memory of one or more second accelerators ( in block 2216, the accelerator device 1620 may receive a request from the kernel 1660 to write data at a local memory address to a memory address of a remote accelerator device. The request may be received through an application programming interface exposed to a high level software language in which the kernel 1660 of the accelerator device 1620 is implemented in block 2218. Such a request may be embodied as a command to the communication abstraction logic unit 1640 that includes a write instruction as well as one or more remote memory addresses and/or one or more local memory addresses, para[0103], ln 1-15/ Fig. 16/ Example 11 includes the subject matter of any of Examples 8-10, and wherein the circuitry is further to receive, from the kernel and through the application programming interface, a request to write data at a memory address of the accelerator device to a second memory address of the remote accelerator device; and transmit, to the remote accelerator device and through the logical communication path established between the accelerator device and the remote accelerator device, the write request and the data at the memory address of the accelerator device, para[0117]),
the API call including address information of data stored in memory of one or more first accelerators( The request may be received through an application programming interface exposed to a high level software language in which the kernel 1660 of the accelerator device 1620 is implemented in block 2204. Such a request may be embodied as a command to the communication abstraction logic unit 1640 that includes a read instruction as well as one or more remote memory addresses and/or one or more local memory addresses. In block 2206, the accelerator device 1620 may transmit the read request for the data at the memory address through a logical communication path to the remote accelerator device. After the remote accelerator processes the request (e.g., by the communication abstraction logic unit 1644 or 1648), the accelerator device 1620 receives the data that was at the memory address of the remote accelerator device, para[0101], ln 15-27 to para[0102], ln 1-12/ In block 2216, the accelerator device 1620 may receive a request from the kernel 1660 to write data at a local memory address to a memory address of a remote accelerator device. The request may be received through an application programming interface exposed to a high level software language in which the kernel 1660 of the accelerator device 1620 is implemented in block 2218. Such a request may be embodied as a command to the communication abstraction logic unit 1640 that includes a write instruction as well as one or more remote memory addresses and/or one or more local memory addresses, para[0103]/ Fig. 22).
Singh teaches in response to receipt of the API call, generate, from the address information, a data structure including information usable to cause the data access ( receiving one or more requests to control memory access. The requests are in the form of a call to a register_as(base address, offset address, locking policy) function. The call to the register_as( ) function is performed shortly after the concurrent computer program is executed. More specifically, the concurrent computer program makes the register_as( ) function call by invoking an initialization software module that contains the register_as( ) function call. The register_as( ) has three parameters: base address; offset address; and locking policy. The base address parameter identifies the base address of a region of memory, while the offset address parameter identifies the upper limit of the region of memory. The locking policy parameter identifies the locking policy (or memory access control technique) that is to be used to control access to the region of memory defined by the base address and offset address parameters, para[0016], ln 3-12 to para[0017], ln 1-10/ Following on from the previous step 202 of receiving the first request (the register_as( ) function), the memory access control means 108 performs the step 204 of creating an instance of a data structure 300, which is represented in FIG. 3, that is based on the first request, or more specifically, the three parameters accompanying the register_as( ) function. With reference to FIG. 3, the instance of the data structure 300 includes six fields 302 to 312 that are used to contain information about the called register_as( ) function. The first field 302 specifies the base address of a region of protected memory, while the second field 304 specifies the upper limit of the region of protected memory. The third field 306 contains a pointer to a queue of tasks waiting to access the region of protected memory defined by the first and second fields 302 and 304. The fourth field 308 identifies the type of policy being used to protect the region of memory defined by the first and second fields 302 and 304. The fifth field 310 is used to indicate whether the region of memory defined by the first and second fields 302 and 304 is accessible. Finally, the sixth field 312 is used to contain a pointer to another related data structure 300, para[0020])).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Balle with Singh to incorporate the above feature because this keeps track of which memory access control techniques are being used and which region of memory each control technique protects.
Woo teaches the API call, generate, from the address information, a data structure include information cause the data to be from the memory of the one or more first accelerators to memory of one or more second accelerators( FIG. 12 depicts a process 1200 for allocating two portions (e.g., blocks) of memory that reside on the same memory channel, associating the two portions of memory, and initiating a data transfer between the two portions of memory. For example, each of the two portions of memory reside on respective memory modules on the same channel, para[0090], ln 6-12/ t block 1202, source code is compiled into a program. The source code can include one or more calls to create direct copy structures and perform direct copy operations, as described below.At block 1204, the program is launched or executed, para[0091] to para[0092]/ block 1206, a function call to create a direct copy structure is executed. In some embodiments, a programming mechanism is available to create and identify “direct transfer” data structures. For example, programming language constructs substantially similar to pragma and/or library calls like malloc can be used. In some embodiments, direct transfer data structures can be dynamically allocated where the data structures are allocated to the same physical memory channel, para[0093]/ the call to “dc_malloc(a, b, size)” allocates “size” bytes over which a direct transfer can occur. The function call “dc_malloc(a, b, size)” sets the pointer “a” to an address at the start of the allocated memory space in one DIMM on a memory channel. The function call “dc_malloc(a, b, size)” sets the pointer “b” to another address on the same memory channel. The pointers “a” and “b” can have the same address alignment to ensure that as the corresponding addresses are traversed, the addresses in “a” and “b” are such that bank/row/column crossings happen for “a” and “b” at the same time. In some embodiments, the direct copy structures are created so that the addresses of each respective structure have matching bank row and column crossings on the memory modules. This avoids situations where accessing data to copy would cross a column boundary and could necessitate two reads for one write operation. The addresses for “a” and “b” can be configured so that there is a 1:1 mapping of physical addresses between two different DIMMs on the memory channel. The direct transfer memory portions can thus be thought of as “bound” together, para[0096]/ block 1208, whether the direct copy structures were created on the same channel is determined. If the direct copy structures were created on the same channel, block 1212 is performed. If copy structures were not created on the same channel or were not able to be created, block 1210 is performed., para[0098]/ At block 1212, a direct copy operation function call is executed. At block 1214, whether the data structures provided are on the same channel is determined. If the data structures are on the same channel, block 1216 is performed, para[0100], The process 1200 thus allows a programmer create a data structure that will be used to copy data from one location to another location. The program requests the creation of the structures by the operating system on the same memory channel. .…. The runtime determines where memory will be allocated from and allocates memory for the direct copy structures. The runtime further receives (or intercepts) the direct copy function call and determines whether the data structures of the direct copy function call are on the same memory channel. If the data structures are not on the same channel, the copy will be performed as a conventional copy, para[0104]/ Fig. 12/ Memory as a Service, page migration and caching and Application Offloading/Acceleration and Integration, using various types of storage, such as Non-Volatile Memory Express, Flash, Multi-Tenancy, Internet Small Computer System Interface (iSCSI), Object Storage, Scale Out storage, and using various types of networking, such as 10/40/100 GbE, Software-Defined Networking, Silicon Photonics, Rack TOR Networks, and Low-Latency networking, para[0127], ln 21-31).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Balle and Singh with Woo to incorporate the above feature because this allows the direct transfer of data between the first and second memory modules reduces power consumption and increases performance.
As to claims 8, 15, they are rejected for the same reason as to claim 1 above.
Claims 2, 9, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Balle (US 20200409877) in view of Singh(US 20090307442 A1) in view of WOO(US 20160259739 A1) and further in view of Rossbach( US 20130232495 A1).
As to claim 2, Balle teaches the information is to indicate one or more memory regions comprising data to be transferred from memory of the one or more first accelerators to memory of the one or more second accelerators( para[0122]/ para[0046], ln 6-18]/ para[0101] ln 12-20), Woo teaches data structure( para[0104]/ Fig. 12) for the same reason as to claim 1 above .
Rossbach teaches the information is to indicate one or more memory regions(the datablocks A and B may be pushed by the application interface 140 into input channels represented by the edges from the datablocks A and B to the node 701, causing the application task associated with the node 701 to be executed by an accelerator 120a-c, para[0074], ln 8-14/ each datablock of the datablocks 340 may include one or more pointers to one or memory locations that are associated with the datablock. The memory locations may include buffers. A datablock may be implemented as a logical buffer with a corresponding physical buffer at one or more of the memories of the computing device 110 and the accelerators 120a-c., para[0033], ln 1-10/ each datablock 340 may also include an indicator of which memory location includes the most current version of the data. Each datablock 340 may further indicate which memory locations are writable, readable, or contain valid data, para[0033], ln 12-16/ The graph includes a node for each of the accelerator tasks, and edges between pairs of nodes corresponding to accelerator task pairs where a data output of a first accelerator task in the pair is a data input of a second accelerator task in the pair, para[0005, ln 3-7/ The graph 900 may similarly be used to eliminate unnecessary copying of data between accelerators 120a-c, para[0065], ln 1-2/ For example, FIG. 2 is an illustration of an example graph 200. The graph includes nodes 207, 209, and 211 that each represent an accelerator task. The graph 200 further includes datablocks 201, 203, 205, and 213 that represent data sources and data sinks used by the accelerator tasks associated with the nodes 207, 209, and 211 of the graph 200, para[0024]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Balle, Singh and Woo with Rossbach to incorporate the above feature because this schedules the execution of accelerator tasks to minimize the amount of data that is copied to and from the accelerators.
As to claims 9, 16, they are rejected for the same reasons as to claim 2 above.
Claims 3, 4, 7, 10, 11, 12, 14,18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Balle (US 20200409877) in view of Singh(US 20090307442 A1) in view of WOO(US 20160259739 A1) and further in view of Lee( US 20220283851 A1).
As to claim 3, Lee teaches the one or more first accelerators are one or more accelerators within a heterogeneous processor( FIG. 3 illustrates an example of an interconnect switch. More specifically, FIG. 3 illustrates an example of an operation of an interconnect switch configured to manage direct communication between accelerators is illustrated. In the example of FIG. 3, accelerators A and B may be devices of heterogeneous hardware types. A first case 310 may indicate passing numerous hardware stacks and software stacks for direct communication between the accelerators A and B. In a case in which an electronic device is configured using heterogeneous accelerators, the performance of the electronic device may be limited due to frequent data synchronizations between the accelerators. A synchronization used herein may refer to a process of transferring input and output of a function to be performed by each of the accelerators A and B, para[0059] to para[0060], ln 1-11).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Balle, Singh and Woo with Lee to incorporate above feature because this manages direct communication between the accelerators without interference by the host processor and a software stack.
As to claim 4, Lee teaches herein the address information of the data comprises pointer to data( para[0059]/ para[0023]/ para[0033], ln 1-5) for the same reason as to claim 2 above.
As to claim 7, Lee teaches the one or more second accelerators are graphics processing units (GPUs)( para[0057], ln 1-5) for the same reason as to claim2 above.
As to claim 10, 12, 14, 19, they are rejected for the same reasons as to claims 2, 3, 4, 7 above.
As to claim 11, Lee teaches the one or more processors comprise the one or more second accelerators( para[0043],l n 1-5) for the same reason as to claim 2 above.
As to claim 18, Lee teaches the one or more first accelerators are accelerators within a heterogeneous processor and the one or more second accelerators are graphics processing units (GPUs)( para[0012], ln 1-8/ para[0017], ln 1-5) for the same reason as to claim 3 above.
Claims 5, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Balle (US 20200409877) in view of Singh(US 20090307442 A1) in view of WOO(US 20160259739 A1) and further in view of Rossbach1( US 20150007182 A1).
As to claim 5, Rossbach1 teaches the information is to be transferred from memory of the one or more first accelerators to memory of the one or more second accelerators( at least one datablock of the plurality of datablocks with a control code to control a flow of the data between memories of accelerators, right col 14, ln 10).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Balle, Singh and Woo Rossbach1 to incorporate above feature because this provides techniques and constructs to improve execution speed of distributed iterative computation using heterogeneous specialized resources including, for example, processors and accelerators.
As to claim 17, is it rejected for the same reason as to claim 5 above.
Claims 6, 13, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Balle (US 20200409877) in view of Singh(US 20090307442 A1) in view of WOO(US 20160259739 A1) in view of Lee( US 20220283851 A1) in view of Yang( US 20190005606 A1).
As to claim 6, Lee teaches GPU accelerator(The accelerators may include any combination of any two or more of an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a graphics processing unit (GPU), para[0017, ln 1-5) for the same reason as to claim 3 above.
Yang teaches the API is to receive, as input, indicating one or more locations in memory of the one or more second accelerators to store the information( computing system that has operating system calls and device driver functions to enable direct memory access transfer of data between peripheral devices and the CPU memory, data structures are established to enable mapping of bus addresses to physical GPU memory, allowing peripheral devices connected to the bus to be able to transfer data directly from or to the GPU memory without copying the data to or from the CPU memory. For example, for a system that uses the Linux operating system, the “struct page” data structure is used to represent a physical page of memory. A user application executing in the user space of the CPU memory can, via a proper system call, send a struct page data object or data structure that represents a page of the CPU physical memory mapped to the user space, to the device driver of a storage device connected to a PCIe bus to enable the storage device to directly transfer data from or to the CPU memory through the PCIe bus without being processed by the CPU. Struct page data objects or data structures can also be established for pages of the GPU physical memory. When the user application intends to transfer data between the GPU memory and the storage device, the user application, via a proper system call, sends the struct page data object(s) representing the page(s) of the GPU physical memory mapped to the user space, to the storage device driver to enable the storage device to directly transfer data from or to the GPU memory page(s) through the PCIe bus without having the data being processed by the CPU and without having the data copied to the CPU memory, para[0019]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Balle, Singh and Woo with Yang to incorporate above feature because this enables direct memory access for both central processing unit memory and graphics processing unit memory.
As to claims 13, 20, they are rejected for the same reason as to claim 6 above.
.
Response to the argument:
A. Applicant amendment filed on 04/07/2026 has been considered but they are not persuasive:
Applicant argued in substance that :
(1) “ Balle does not disclose circuitry that, in response to the API call, generates a data structure including information usable to cause data stored in memory of one or more first accelerators to be transferred from the memory of the one or more first accelerators to memory of one or more second accelerators, as recited by claim 1, as amended.
B. Examiner respectfully disagreed with Applicant's remarks:
As to the point (1), Balle teaches processor(executed by one or more processors, para[0024], ln 6-8), one or more circuits to perform an application programming interface (API) to transfer information between memory of one or more first accelerators and memory of one or more second accelerators ( in block 2216, the accelerator device 1620 may receive a request from the kernel 1660 to write data at a local memory address to a memory address of a remote accelerator device. The request may be received through an application programming interface exposed to a high level software language in which the kernel 1660 of the accelerator device 1620 is implemented in block 2218. Such a request may be embodied as a command to the communication abstraction logic unit 1640 that includes a write instruction as well as one or more remote memory addresses and/or one or more local memory addresses, para[0103], ln 1-15/ Fig. 16/ Example 11 includes the subject matter of any of Examples 8-10, and wherein the circuitry is further to receive, from the kernel and through the application programming interface, a request to write data at a memory address of the accelerator device to a second memory address of the remote accelerator device; and transmit, to the remote accelerator device and through the logical communication path established between the accelerator device and the remote accelerator device, the write request and the data at the memory address of the accelerator device, para[0117]),
the API call including address information of data stored in memory of one or more first accelerators( The request may be received through an application programming interface exposed to a high level software language in which the kernel 1660 of the accelerator device 1620 is implemented in block 2204. Such a request may be embodied as a command to the communication abstraction logic unit 1640 that includes a read instruction as well as one or more remote memory addresses and/or one or more local memory addresses. In block 2206, the accelerator device 1620 may transmit the read request for the data at the memory address through a logical communication path to the remote accelerator device. After the remote accelerator processes the request (e.g., by the communication abstraction logic unit 1644 or 1648), the accelerator device 1620 receives the data that was at the memory address of the remote accelerator device, para[0101], ln 15-27 to para[0102], ln 1-12/ In block 2216, the accelerator device 1620 may receive a request from the kernel 1660 to write data at a local memory address to a memory address of a remote accelerator device. The request may be received through an application programming interface exposed to a high level software language in which the kernel 1660 of the accelerator device 1620 is implemented in block 2218. Such a request may be embodied as a command to the communication abstraction logic unit 1640 that includes a write instruction as well as one or more remote memory addresses and/or one or more local memory addresses, para[0103]/ Fig. 22).
Singh teaches in response to receipt of the API call, generate, from the address information, a data structure including information usable to cause the data access ( receiving one or more requests to control memory access. The requests are in the form of a call to a register_as(base address, offset address, locking policy) function. The call to the register_as( ) function is performed shortly after the concurrent computer program is executed. More specifically, the concurrent computer program makes the register_as( ) function call by invoking an initialization software module that contains the register_as( ) function call. The register_as( ) has three parameters: base address; offset address; and locking policy. The base address parameter identifies the base address of a region of memory, while the offset address parameter identifies the upper limit of the region of memory. The locking policy parameter identifies the locking policy (or memory access control technique) that is to be used to control access to the region of memory defined by the base address and offset address parameters, para[0016], ln 3-12 to para[0017], ln 1-10/ Following on from the previous step 202 of receiving the first request (the register_as( ) function), the memory access control means 108 performs the step 204 of creating an instance of a data structure 300, which is represented in FIG. 3, that is based on the first request, or more specifically, the three parameters accompanying the register_as( ) function. With reference to FIG. 3, the instance of the data structure 300 includes six fields 302 to 312 that are used to contain information about the called register_as( ) function. The first field 302 specifies the base address of a region of protected memory, while the second field 304 specifies the upper limit of the region of protected memory. The third field 306 contains a pointer to a queue of tasks waiting to access the region of protected memory defined by the first and second fields 302 and 304. The fourth field 308 identifies the type of policy being used to protect the region of memory defined by the first and second fields 302 and 304. The fifth field 310 is used to indicate whether the region of memory defined by the first and second fields 302 and 304 is accessible. Finally, the sixth field 312 is used to contain a pointer to another related data structure 300, para[0020])).
Woo teaches the API call, generate, from the address information, a data structure include information cause the data to be from the memory of the one or more first accelerators to memory of one or more second accelerators( FIG. 12 depicts a process 1200 for allocating two portions (e.g., blocks) of memory that reside on the same memory channel, associating the two portions of memory, and initiating a data transfer between the two portions of memory. For example, each of the two portions of memory reside on respective memory modules on the same channel, para[0090], ln 6-12/ t block 1202, source code is compiled into a program. The source code can include one or more calls to create direct copy structures and perform direct copy operations, as described below.At block 1204, the program is launched or executed, para[0091] to para[0092]/ block 1206, a function call to create a direct copy structure is executed. In some embodiments, a programming mechanism is available to create and identify “direct transfer” data structures. For example, programming language constructs substantially similar to pragma and/or library calls like malloc can be used. In some embodiments, direct transfer data structures can be dynamically allocated where the data structures are allocated to the same physical memory channel, para[0093]/ the call to “dc_malloc(a, b, size)” allocates “size” bytes over which a direct transfer can occur. The function call “dc_malloc(a, b, size)” sets the pointer “a” to an address at the start of the allocated memory space in one DIMM on a memory channel. The function call “dc_malloc(a, b, size)” sets the pointer “b” to another address on the same memory channel. The pointers “a” and “b” can have the same address alignment to ensure that as the corresponding addresses are traversed, the addresses in “a” and “b” are such that bank/row/column crossings happen for “a” and “b” at the same time. In some embodiments, the direct copy structures are created so that the addresses of each respective structure have matching bank row and column crossings on the memory modules. This avoids situations where accessing data to copy would cross a column boundary and could necessitate two reads for one write operation. The addresses for “a” and “b” can be configured so that there is a 1:1 mapping of physical addresses between two different DIMMs on the memory channel. The direct transfer memory portions can thus be thought of as “bound” together, para[0096]/ block 1208, whether the direct copy structures were created on the same channel is determined. If the direct copy structures were created on the same channel, block 1212 is performed. If copy structures were not created on the same channel or were not able to be created, block 1210 is performed., para[0098]/ At block 1212, a direct copy operation function call is executed. At block 1214, whether the data structures provided are on the same channel is determined. If the data structures are on the same channel, block 1216 is performed, para[0100], The process 1200 thus allows a programmer create a data structure that will be used to copy data from one location to another location. The program requests the creation of the structures by the operating system on the same memory channel. .…. The runtime determines where memory will be allocated from and allocates memory for the direct copy structures. The runtime further receives (or intercepts) the direct copy function call and determines whether the data structures of the direct copy function call are on the same memory channel. If the data structures are not on the same channel, the copy will be performed as a conventional copy, para[0104]/ Fig. 12/ Memory as a Service, page migration and caching and Application Offloading/Acceleration and Integration, using various types of storage, such as Non-Volatile Memory Express, Flash, Multi-Tenancy, Internet Small Computer System Interface (iSCSI), Object Storage, Scale Out storage, and using various types of networking, such as 10/40/100 GbE, Software-Defined Networking, Silicon Photonics, Rack TOR Networks, and Low-Latency networking, para[0127], ln 21-31).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
US 20200409877 A1teaches memory locations on the FPGA 1622 or the GPU 1624). The request may be received through an application programming interface exposed to a high level software language in which the kernel 1660 of the accelerator device 1620 is implemented in block 2204. Such a request may be embodied as a command to the communication abstraction logic unit 1640 that includes a read instruction as well as one or more remote memory addresses and/or one or more local memory addresses.
US 20160259739 A1 teaches some embodiments, the call to “dc_malloc(a, b, size)” allocates “size” bytes over which a direct transfer can occur. The function call “dc_malloc(a, b, size)” sets the pointer “a” to an address at the start of the allocated memory space in one DIMM on a memory channel. The function call “dc_malloc(a, b, size)” sets the pointer “b” to another address on the same memory channel.
US 10802807 teaches B1FIG. 20B includes a global memory input/output (GMIO) class with special APIs for moving data between the DPE array and DDR memory in the SoC. For example, the init( ) API initializes a GMIO object by providing a set of memory addresses that exist in the DDR memory. The gm2me_nb( ) APIs can use the DMA registers in the shim to transfer data from the global memory to the DPE array.
US 20100161976 A1 teaches a system call having memory reference parameters, a memory area referred to by a parameter of the system call may be a structured object rather than raw data. For example, the ioctl( ) system call may have an object supporting a buffer interface. The structured object referred to by the parameter should be evaluated and converted element by element of the structured object.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LECHI TRUONG whose telephone number is (571)272-3767. The examiner can normally be reached 10-8 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Young Kevin can be reached on (571)270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LECHI TRUONG/ Primary Examiner, Art Unit 2194
.
Prosecution Insights