DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 2/18/2026 is acknowledged.
Applicant amended claims 1, 2, 9, 10, and 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, and 9-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al. (US 2023/0420429) (hereafter Chang).
Regarding claim 1, Chang discloses an integrated circuit package (device in Fig. 10A) comprising:
a first integrated circuit die (left 701 in Fig. 10A, paragraph 0052);
a first spacer die (left 710 and right 710 in Fig. 10A, paragraph 0052) coupled in the integrated circuit package (device in Fig. 10A) in a first location (region where left 710 and right 710 are formed in Fig. 10A) designed to house a second integrated circuit die (left 703 in Fig. 10A, paragraph 0052); and
an interconnection bridge 405 (Fig. 10A, paragraph 0035) embedded in a substrate 400 (Fig. 10A, paragraph 0079), wherein the first integrated circuit die (left 701 in Fig. 10A) and the first spacer die (left 710 and right 710 in Fig. 10A) are coupled (see Fig. 10A, wherein 701 and 710 are indirectly coupled to 405) to the interconnection bridge 405 (Fig. 10A).
Regarding claim 2, Chang further discloses the integrated circuit package of claim 1 further comprising: wherein the interconnection bridge 405 (Fig. 10A) comprises conductors (element number is not shown in Fig. 10A but see 480 in Fig. 3, paragraph 0034) that are coupled to the first integrated circuit die (left 701 in Fig. 10A) and to the first spacer die (left 710 and right 710 in Fig. 10A).
Regarding claim 3, Chang further discloses the integrated circuit package of claim 1 further comprising: a second spacer die (top 710 and bottom 710 in Fig. 10B, paragraph 0052) coupled in the integrated circuit package (device in Fig. 10A) in a second location (region where top 710 and bottom 710 are formed in Fig. 10B) designed to house a third integrated circuit die (top right 701 in Fig. 10B, paragraph 0052).
Regarding claim 5, Chang further discloses the integrated circuit package of claim 1, wherein the first integrated circuit die (left 701 in Fig. 10A, paragraph 0053, wherein “application processor die, a central processing unit die, or a graphic processing unit die”) comprises a processing integrated circuit.
Regarding claim 6, Chang further discloses the integrated circuit package of claim 1 further comprising: a third integrated circuit die (bottom left 701 in Fig. 10B) coupled to the first integrated circuit die (top left 701 in Fig. 10B).
Regarding claim 7, Chang further discloses the integrated circuit package of claim 6, wherein the third integrated circuit die (bottom left 701 in Fig. 10B) comprises a first transceiver integrated circuit (bottom left 701 in Fig. 10B; see Fig. 10A and paragraph 0099, wherein “the package-side redistribution wiring interconnects (580, 582) embodiments wafer-level communication for SoC dies 701 and data transmission to, and from, high bandwidth memory dies that are attached to the composite interposer (400, 500)”), and wherein the first spacer die (left vertical 710 and right vertical 710 in Fig. 10B) is coupled in the integrated circuit package (device in Fig. 10A) in the first location (region where left vertical 710 and right vertical 710 are formed in Fig. 10B) that is designed to house a second transceiver integrated circuit (bottom right 701 in Fig. 10B; see Fig. 10A and paragraph 0099, wherein “the package-side redistribution wiring interconnects (580, 582) embodiments wafer-level communication for SoC dies 701 and data transmission to, and from, high bandwidth memory dies that are attached to the composite interposer (400, 500)”).
Regarding claim 9, Chang discloses a method for forming an integrated circuit package (device in Fig. 10A), the method comprising:
coupling a first integrated circuit die (left 701 in Fig. 10A, paragraph 0052) in the integrated circuit package (device in Fig. 10A); and
coupling a first spacer die (left 710 and right 710 in Fig. 10A, paragraph 0052) in the integrated circuit package (device in Fig. 10A) in a first location (region where left 710 and right 710 are formed in Fig. 10A) designed to house a second integrated circuit die (left 703 in Fig. 10A, paragraph 0052); and
coupling an interconnection bridge 405 (Fig. 10A, paragraph 0035) embedded in a substrate 400 (Fig. 10A, paragraph 0079) to the first integrated circuit die (left 701 in Fig. 10A) and to the first spacer die (left 710 and right 710 in Fig. 10A).
Regarding claim 10, Chang further discloses the method of claim 9, wherein coupling the first integrated circuit die (left 701 in Fig. 10A) in the integrated circuit package (device in Fig. 10A) and coupling the first spacer die (left 710 and right 710 in Fig. 10A) in the integrated circuit package (device in Fig. 10A) further comprise coupling the first integrated circuit die (left 701 in Fig. 10A) and the first spacer die (left 710 and right 710 in Fig. 10A) to the interconnection bridge 405 (Fig. 10A) through conductive bumps (element number is not shown in Fig. 10A but see 435 in Fig. 3, paragraph 0034).
Regarding claim 11, Chang further discloses the method of claim 9 further comprising: coupling a second spacer die (top horizontal 710 and bottom horizontal 710 in Fig. 10B, paragraph 0052) in the integrated circuit package (device in Fig. 10A) in a second location (region where top horizontal 710 and bottom horizontal 710 are formed in Fig. 10B) designed to house a third integrated circuit die (top right 701 in Fig. 10B, paragraph 0052).
Regarding claim 12, Chang further discloses the method of claim 11, wherein each of the first (left vertical 710 and right vertical 710 in Fig. 10B) and the second spacer dies (top horizontal 710 and bottom horizontal 710 in Fig. 10B) is an open circuit die (see paragraph 0052, wherein “Each spacer die 710 is free from any transistor therein”) that lacks active circuits.
Regarding claim 13, Chang further discloses the method of claim 9 further comprising: coupling a third integrated circuit die (bottom left 701 in Fig. 10B) to the first integrated circuit die (top left 701 in Fig. 10B) in the integrated circuit package (device in Fig. 10A).
Regarding claim 14, Chang further discloses the method of claim 9, wherein the first integrated circuit die (top left 701 in Fig. 10B, paragraph 0053, wherein “application processor die, a central processing unit die, or a graphic processing unit die”) comprises a processing integrated circuit, and wherein the first spacer die (left vertical 710 and right vertical 710 in Fig. 10B) is coupled in the integrated circuit package (device in Fig. 10B) in the first location (region where left vertical 710 and right vertical 710 are formed in Fig. 10B) that is designed to house a transceiver integrated circuit (bottom left 701 in Fig. 10B; see Fig. 10A and paragraph 0099, wherein “the package-side redistribution wiring interconnects (580, 582) embodiments wafer-level communication for SoC dies 701 and data transmission to, and from, high bandwidth memory dies that are attached to the composite interposer (400, 500)”).
Regarding claim 15, Chang discloses a circuit system comprising:
a substrate 400 (Fig. 10A, paragraph 0039) comprising an interconnection bridge 405 (Fig. 10A, paragraph 0035) embedded in the substrate 400 (Fig. 10A);
a first integrated circuit die (left 701 in Fig. 10A, paragraph 0052) coupled to the substrate 400 (Fig. 10A); and
a first spacer die (left 710 and right 710 in Fig. 10A, paragraph 0052) coupled to the substrate 400 (Fig. 10A) at a first location (region where left 710 and right 710 are formed in Fig. 10A) designed to house a second integrated circuit die (left 703 in Fig. 10A, paragraph 0052), wherein the first integrated circuit die (left 701 in Fig. 10A) and the first spacer die (left 710 and right 710 in Fig. 10A) are coupled to the interconnection bridge 405 (Fig. 10A).
Regarding claim 16, Chang further discloses the circuit system of claim 15 further comprising: a second spacer die (top 710 and bottom 710 in Fig. 10B, paragraph 0052) coupled to the substrate 400 (Fig. 10B) at a second location (region where top 710 and bottom 710 are formed in Fig. 10B) designed to house a third integrated circuit die (top right 701 in Fig. 10B, paragraph 0052).
Regarding claim 17, Chang further discloses the circuit system of claim 15, wherein the substrate 400 (Fig. 10A, paragraph 0039) is a package substrate, and wherein the circuit system is an integrated circuit package (see paragraph 0053, wherein “system-on-chip (SoC) die”).
Regarding claim 18, Chang further discloses the circuit system of claim 15 further comprising: a third integrated circuit die (top right 701 in Fig. 10B, paragraph 0052) coupled to the substrate 400 (Fig. 10B).
Claims 1, 4, 8, 15, 19, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeong et al. (US 2005/0208701) (hereafter Jeong).
Regarding claim 1, Jeong discloses an integrated circuit package 64 (Fig. 12, paragraph 0041) comprising:
a first integrated circuit die 24B (Fig. 12, paragraph 0041);
a first spacer die 66 (Fig. 12, paragraph 0041) coupled in the integrated circuit package 64 (Fig. 12) in a first location (region where 66 is formed in Fig. 12) designed to house a second integrated circuit die 24A (Fig. 12, paragraph 0041); and
an interconnection bridge 54 (Fig. 12, paragraph 0039) embedded in a substrate 58 (Fig. 12, paragraph 0039), wherein the first integrated circuit die 24B (Fig. 12) and the first spacer die 66 (Fig. 12) are coupled (see Fig. 12, wherein 24B and 66 are indirectly coupled to 58) to the interconnection bridge 58 (Fig. 12).
Regarding claim 4, Jeong further discloses the integrated circuit package of claim 1, wherein the first spacer die 66 (Fig. 12, paragraph 0041, wherein “prevent electrical leakage”) is an open circuit die that blocks leakage current.
Regarding claim 8, Jeong further discloses the integrated circuit package of claim 1, wherein the first spacer die 66 (Fig. 12, paragraph 0048) has a same size (see paragraph 0048, wherein “spacer stacked over the first die can be the same size as the first die”) as the second integrated circuit die 24A (Fig. 12).
Regarding claim 15, Jeong discloses a circuit system comprising:
a substrate 46 (Figs. 9 and 12, paragraph 0039) comprising an interconnection bridge 54 (Figs. 9 and 12, paragraph 0039) embedded (see Fig. 9) in the substrate 58 (Figs. 9 and 12);
a first integrated circuit die 24B (Fig. 12, paragraph 0041) coupled to the substrate 46 (Fig. 12); and
a first spacer die 66 (Fig. 12, paragraph 0041) coupled to the substrate 46 (Fig. 12) at a first location (region where 66 is formed in Fig. 12) designed to house a second integrated circuit die 24A (Fig. 12, paragraph 0041), wherein the first integrated circuit die 24B (Fig. 12) and the first spacer die 66 (Fig. 12) are coupled to the interconnection bridge 54 (Fig. 12).
Regarding claim 19, Jeong further discloses the circuit system of claim 15, wherein the first spacer die 66 (Fig. 12, paragraph 0041, wherein “prevent electrical leakage”) is an open circuit die that blocks leakage current through the first spacer die 66 (Fig. 12).
Regarding claim 20, Jeong further discloses the circuit system of claim 15, wherein the first spacer die 66 (Fig. 12, paragraph 0048) has a same footprint (see paragraph 0048, wherein “spacer stacked over the first die can be the same size as the first die”) over the substrate 46 (Fig. 12) as the second integrated circuit die 24A (Fig. 12).
Response to Arguments
1. Applicant's arguments filed 2/18/2026 have been fully considered.
2. The applicant argues (REMARKS, second paragraph in page 7) that “Chang does not disclose or suggest that any of the spacer dies 710 are coupled to an interconnection bridge embedded in a substrate. For example, FIG. 10A of Chang does not show that either of the spacer dies 710 is coupled to an interconnection bridge that is also coupled to one of the semiconductor dies 703 or 701. FIG. 10A of Chang does not disclose or suggest that die 415 is coupled to either of the semiconductor dies 703 or 701. Chang does not disclose or suggest that the LSI bridges 405 are coupled to any of the spacer dies 710. See also FIG. 12 of Chang. Therefore, Chang does not disclose or suggest at least "an interconnection bridge embedded in a substrate, wherein the first integrated circuit die and the first spacer die are coupled to the interconnection bridge" as recited in amended claim 1 of the present application.” However, Chang et al. (US 2023/0420429) disclose an interconnection bridge 405 (Fig. 10A, paragraph 0035) embedded in a substrate 400 (Fig. 10A, paragraph 0079), wherein the first integrated circuit die (left 701 in Fig. 10A) and the first spacer die (left 710 and right 710 in Fig. 10A) are coupled (see Fig. 10A, wherein 701 and 710 are indirectly coupled to 405) to the interconnection bridge 405 (Fig. 10A). In addition, Jeong et al. (US 2005/0208701) disclose an interconnection bridge 54 (Fig. 12, paragraph 0039) embedded in a substrate 58 (Fig. 12, paragraph 0039), wherein the first integrated circuit die 24B (Fig. 12) and the first spacer die 66 (Fig. 12) are coupled (see Fig. 12, wherein 24B and 66 are indirectly coupled to 58) to the interconnection bridge 58 (Fig. 12).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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