DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species III in the reply filed on 01/27/2026 is acknowledged. The traversal is on the ground(s) that the applicant elects species III corresponding to Fig. 4 for examination. Applicant respectfully traverses the alleged correspondence between the claims and the figures. Applicant respectfully submits that claims 1-25 correspond to FIG. 4.
It is noted that the applicant merely stated claims 1-25 read on Fig. 4 but does not explained as to how each limitations in each claims 1-25 would be read on Fig. 4. Thus, this is not found persuasive for because the restriction is species restrictions and the applicant has not traverse on the ground that the species are not patently distinct. Applicant’s argument is provided only as an assertion, and is thus not persuasive.
The requirement is still deemed proper and is therefore made FINAL.
Claims 2-8 & 19-25 do not read on the elected Species III, Fig. 4, thus Claims 2-8 & 19-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, 11 & 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maida (US 7,285,992 B1).
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Regarding claim 1, Maida discloses in Fig. 5 a circuit comprising:
a front-end including an input section (forms by transistors XIP1, XIN1, XIN2, XIP2) having a voltage input (INP, INM) and a current output (collector terminals of transistors XIN2 and XINP2);
a current generating section (circuit 520, Transistors X52A-X52D and resistors R52A-R52C are configured to operate as a first current mirror circuit) operably coupled to the input section;
a signal node (annotated, node N1, N2) operably coupled to the input section; and
transconductance choke circuitry (it is noted that no specific transconductance choke circuitry defined by the applicant, thus broadly, diode XDN1 and transistor X54) coupled to the signal node and to the current generating section, the transconductance choke circuitry configured to control transconductance of the front-end.
Regarding claim 9, Maida discloses in Fig. 5 an amplifier comprising:
an input section (forms by transistors XIP1, XIN1, XIN2, XIP2) having a voltage input (INP, INM) having a voltage input (INP, INM) and a current output (collector terminals of transistors XIN2 and XINP2);
a current generating section (circuit 520, Transistors X52A-X52D and resistors R52A-R52C are configured to operate as a first current mirror circuit) operably coupled to the input section, the current generating section including impedance circuitry (transistors X52A, X52B and X52C in circuit 520);
a signal node (annotated, node N1, N2) operably coupled to the input section;
voltage follower circuitry (transistors X56, X57) coupled to the signal node; and
diode circuitry (diode transistor XDN1) coupled to the voltage follower circuitry and to the impedance circuitry.
Regarding claim 11, Maida discloses in Fig. 5 the amplifier of claim 9,
wherein the impedance circuitry includes a pair of transistors (e.g., transistors X52B and X52C form a current mirror to generate current) of the current generating circuitry.
Regarding claim 13, Maida discloses in Fig. 5 the amplifier of claim 9,
wherein the amplifier includes multiple stages including:
a first stage comprised of the input section (transistors XIP1, XIN1, XIN2, XIP2, the current generating section (circuit 520), the signal node (annotated, node N1, N2), the diode circuitry (diode transistor XDN1), and the impedance circuitry (transistors X52A, X52B and X52C in circuit 520), the signal node forming an output of the first stage, and the diode circuitry including first and second diode circuits (transistors XDN1 and XDP1);and
a second stage (form by transistors XFN and XFP) having first and second nodes (NN1 and NN2) that follow an output voltage at the signal node, the first node (N1) coupled to the first diode circuit (XDN1) and the second node (N2) coupled to the second diode circuit (XDP1).
Claim 18 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Srinivasa et al. (US 2009/0058527 A1).
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Regarding claim 18, Srinivasa et al. discloses in Fig. 5 an amplifier comprising:
an input section (510) configured to receive an input voltage (input voltage at terminals 501, 502);
an output section (540) configured to output an output voltage in response to the input voltage (INP, INM); and
transconductance choke circuitry (it is noted that no specific transconductance choke circuitry defined by the applicant, thus broadly, transistor 513 read as transconductance choke circuitry wherein the transistor 513 is controlled by comparator circuit 545, the comparator 545 comparing signal output from circuit 540 with reference signal a terminal 505)) configured to reduce transconductance of the input section in response to the output voltage exceeding or dropping below a threshold (e.g. reference signal at terminal 505).
Allowable Subject Matter
Claims 10, 12 & 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The most relevant prior art reference of Maida does not teach: in regards to claims 10 & 12, wherein the diode circuitry includes a plurality of Schottky diodes coupled in series; and wherein the pair of transistors includes a first n-type bipolar junction transistor (n-BJT) and a second n-BJT, each having a base, an emitter and a collector, the collector of the first n-BJT coupled to the base of the second n-BJT and the base of the first n-BJT coupled to the emitter of the second n-BJT. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious.
The most relevant prior art reference of Maida does not teach: in regards to claim 14, the diode circuitry includes first and second diode strings, and the impedance circuitry includes first and second impedance circuits, the first impedance circuit formed by a first transistor pair of the current generating section and the second impedance circuit formed by a second transistor pair of the current generating section. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious. By virtue of dependency from claims 15-17 has also been determined to be novel and non-obvious.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843