DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 8/12/26.
Applicant’s amendment to claim 1 is acknowledged.
Claims 1-25 are pending and claims 12-25 are withdrawn.
Claims 1-11 are subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al., US Publication No. 2014/0124929 A1.
Lin anticipates:
1. An interconnect, comprising (see fig.10 and 15; also see figs. 22 and 28):
a substrate (200);
a pad (208) over the substrate;
a hole (209) through the pad, wherein the hole exposes a portion of the substrate; and
a solder (215) over the pad, wherein the solder (215) bridges across the hole (209) through the pad (208), and wherein the solder (215) has a bottommost surface at a same level as a bottommost surface of the pad (208). See Lin at para. [0001] – [0131], figs. 1-46.
2. The interconnect of claim 1, wherein the solder (215) fully fills the hole (209), fig. 15.
3. The interconnect of claim 1, wherein the solder partially fills the hole (e.g. If the solder 215 fully fills the hole, then it also at least partially fills the hole.), fig. 15.
4. The interconnect of claim 1, wherein a width of the hole (209) is less than a thickness of the pad (208), fig. 15.
8. The interconnect of claim 1, wherein the solder comprises tin and the pad comprises copper, para. [0042] – [0045],
9. The interconnect of claim 1, wherein the substrate is a package substrate, para. [0004], [0024].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 1 above.
Regarding claims 5-7:
Lin teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the width of the hole is up to half the thickness of the pad;
wherein the width of the hole is up to approximately 15 μm;
wherein an outer width of the pad is up to approximately 80 μm.
However, Lin teaches the width of hole and outer width of the pad are a result affective variable (e.g. In fig. 5, the width of hole is dimension c-a. The outer width of the pad is dimension c) to achieve “desired mechanical strength”.
It would have been obvious to one having ordinary skill in the art to form “wherein the width of the hole is up to half the thickness of the pad; wherein the width of the hole is up to approximately 15 μm; wherein an outer width of the pad is up to approximately 80 μm.”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 1 above, and further in view of Alur et al. US Publication No. 10,163,798 (of record).
Regarding claim 10:
Lin teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the package substrate is coupled to a processor of a computing system.
In an analogous art, Alur taches:
wherein the package substrate (e.g. 101 in fig. 1A corresponding to 520 in fig. 5) is coupled to a processor (510) of a computing system, col 2, ln 10–20, col 6, ln 43–67, col 7, ln 1–67.
Regarding claim 11:
Lin further teaches:
11. The interconnect of claim 9, further comprising:
a die coupled to the package substrate, wherein the solder couples the die to the package substrate, para. [0024].
Lin does not expressly teach:
a board coupled to the package substrate;
Alur further teaches:
a board (394 in fig. 3) coupled to the package substrate, col 5, ln 60–67.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lin with the teachings of Alur because in order to enable computing in devices such as a laptop, PDA, cellular phone, etc. See Alur at col 6, ln 43–67.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michele Fan/
Primary Examiner, Art Unit 2818
29 September 2026
