DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-11, in the reply filed on 2/16/26 is acknowledged.
Claims 12-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/16/26.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8, 9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MacKay et al., US Publication No. 2010/0089983 A1.
MacKay anticipates:
1. An interconnect, comprising (see fig. 7G-7I):
a substrate (762);
a pad (764) over the substrate;
a hole (792) through the pad, wherein the hole exposes a portion of the substrate; and
a solder (790) over the pad, wherein the solder (790) bridges across the hole (792) through (e.g. by way of) the pad (764). See Mackay at para. [0244] – [0249], also see para. [0001] – [0402], figs. 1-14.
8. The interconnect of claim 1, wherein the solder comprises tin and the pad comprises copper, para. [0014], [0110], [0359].
9. The interconnect of claim 1, wherein the substrate is a package substrate (e.g. see package substrate at para. [0012], [0031])
11. The interconnect of claim 9, further comprising:
a board (e.g. circuit board at para. [0204]) coupled to the package substrate (e.g. para. [0012], [0031]); and
a die (e.g. flip chip at para. [0012] – [0013], [0017]) coupled to the package substrate, wherein the solder couples the die to the package substrate.
Claim(s) 1-3 and 9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhang et al., US Publication No. 2025/0098070 A1.
Zhang anticipates:
1. An interconnect, comprising (see figs. 7-8):
a substrate (1);
a pad (102a) over the substrate;
a hole (1021) through the pad, wherein the hole exposes a portion (e.g. left and right sidewall portions) of the substrate (1); and
a solder (3) over the pad, wherein the solder (3) bridges across the hole (1021) through the pad (102a). See Zhang para. [0082] – [0090], also see para. [0001] – [0111], figs. 1-21.
2. The interconnect of claim 1, wherein the solder (3) fully fills the hole, fig. 8
3. The interconnect of claim 1, wherein the solder (3) partially fills the hole (e.g. If the solder fully fills the hole, it also partially fills the hole.), fig. 8.
9. The interconnect of claim 1, wherein the substrate is a package substrate, para. [0088].
Claim(s) 1-3, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pendse et al., US Publication No. 2011/0074024 A1.
Pendse anticipates:
1. An interconnect, comprising (see fig. 21):
a substrate (308/314);
a pad (306; e.g. See para. [0126], “Alternatively, bump material 304 can be aligned with a conductive pad or other interconnect site formed on substrate 308.”) over the substrate;
a hole (312) through the pad, wherein the hole exposes a portion (e.g. left and right sidewall portions) of the substrate (308/314); and
a solder (304) over the pad, wherein the solder (304) bridges across the hole (312) through the pad (306). See Pendse at para. [0001] – [0159], figs. 1-27.
2. The interconnect of claim 1, wherein the solder (304) fully fills the hole, fig. 21.
3. The interconnect of claim 1, wherein the solder (304) partially fills the hole (e.g. If the solder fully fills the hole, it also partially fills the hole.), fig. 21.
8. The interconnect of claim 1, wherein the solder comprises tin and the pad comprises copper, para. [0063], [0144].
9. The interconnect of claim 1, wherein the substrate is a package substrate, para. [0099].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-7, 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pendse, as applied to claim 1 above.
Regarding claims 4-6:
Pendse teaches all the limitations of claim 1 above, but does not expressly teach:
wherein a width of the hole is less than a thickness of the pad;
wherein the width of the hole is up to half the thickness of the pad;
wherein the width of the hole is up to approximately 15 μm.
However, Pendse teaches at para. [0126]:
The mechanical interlock between the bump material and the top surface and side surfaces of conductive trace 306 and opening 312 of conductive via 310 provides a robust connection with greater contact area between the respective surfaces, without significantly increasing the bonding force. The mechanical interlock between the bump material and the top surface and side surfaces of conductive trace 306 and opening 312 of conductive via 310 also reduces lateral die shifting during subsequent manufacturing processes, such as encapsulation. (Emphasis added.)
The size of the hole affects the contact area and thus, the bonding force. The bonding force ultimately affects lateral die shifting.
The size of the hole comprises the width. The size/width of the hole is a result effect variable that one of ordinary skill in the art would find obvious to optimize
Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Also see MPEP § 2144.05:
In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)…Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions. (Emphasis added.)
Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent").
Regarding claim 7:
Pendse teaches an outer width of the pad is approximately 100 μm, para. [0095] – [0096].
Pendse does not expressly teach 80 μm.
However, it would have been obvious to one of ordinary skill in the art to form an outer width of the pad is up to approximately 80 μm, since such a modification would have involved a mere change in the size of a component. A change is size is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04, Legal Precedent as Source of Supporting Rationale, IV. Changes in Size, Shape, or Sequence of Adding Ingredients.
Regarding claims 9 and 11:
In the embodiment shown in fig. 21, Pendse does not show a board coupled to the package substrate.
However, it would have been obvious to one of ordinary skill in the art to form a board coupled to the package substrate because Pendse teaches this in the embodiment shown in fig. 5c.
(see fig. 5c) wherein the substrate is a package substrate (106)
a board (52) coupled to the package substrate; and
a die (58) coupled to the package substrate, wherein the solder (110) couples the die to the package substrate (106), para. [0065] – [0067].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacKay, as applied to claim 1 above, and further in view of Alur et al. US Publication No. 10,163,798.
Regarding claim 10:
MacKay teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the package substrate is coupled to a processor of a computing system.
In an analogous art, Alur taches:
wherein the package substrate (e.g. 101 in fig. 1A corresponding to 520 in fig. 5) is coupled to a processor (510) of a computing system, col 2, ln 10–20, col 6, ln 43–67, col 7, ln 1–67.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of MacKay with the teachings of Alur because in order to enable computing in devices such as a laptop, PDA, cellular phone, etc. See Alur at col 6, ln 43–67.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, as applied to claim 1 above, and further in view of Alur et al. US Publication No. 10,163,798.
Regarding claim 10:
Zhang teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the package substrate is coupled to a processor of a computing system.
In an analogous art, Alur taches:
wherein the package substrate (e.g. 101 in fig. 1A corresponding to 520 in fig. 5) is coupled to a processor (510) of a computing system, col 2, ln 10–20, col 6, ln 43–67, col 7, ln 1–67.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Zhang with the teachings of Alur because in order to enable computing in devices such as a laptop, PDA, cellular phone, etc. See Alur at col 6, ln 43–67.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pendse, as applied to claim 1 above, and further in view of Alur et al. US Publication No. 10,163,798.
Regarding claim 10:
Pendse teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the package substrate is coupled to a processor of a computing system.
In an analogous art, Alur taches:
wherein the package substrate (e.g. 101 in fig. 1A corresponding to 520 in fig. 5) is coupled to a processor (510) of a computing system, col 2, ln 10–20, col 6, ln 43–67, col 7, ln 1–67.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Pendse with the teachings of Alur because in order to enable computing in devices such as a laptop, PDA, cellular phone, etc. See Alur at col 6, ln 43–67.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
5 May 2026
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