CTFR 18/071,257 CTFR 85098 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment Claims 1, 14 and 23 have been amended; and claims 1-25 are currently pending. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 2, 3, 4, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2016/0128186 A1, hereinafter “Cho”) in view of Park (KR 20090107682 A, hereinafter “Park”) . In regards to claim 1, Cho discloses (See, for example, annotated Fig. 6F attached below) a package substrate ( 1000), comprising: a core (10); buildup layers (800) over the core; and a polymer over the core (11) . Cho is silent about having the shape memory polymer over the core. However, Park while disclosing a PCB substrate teaches (See, for example, Fig. 4) the shape memory polymer (130) over the core (120). In regards to a conductive structure extending at least partially through the SMP. Cho teaches a via 150 formed of a conductive metal (e.g., copper) penetrating through the core part 100 and connecting the first wiring layer 210 disposed on opposing surfaces thereof (See, Figs. 1A, 6A/6B). Though Cho is does not expressly teach that the resin layer over the core comprises a shape memory polymer, Park teaches a printed circuit board in which a shape memory polymer 130 is impregnated into the core material in place of the conventional polymer resin, at approximately the same 40% ratio (See, for example, Fig. 4 and Tech Solution), the SMP being a synthetic resin that returns a memorized flat shape upon heating above the shape recovery temperature, and the board being pressed flat at the pre-shipment bake temperature so that the flat shape and temperature condition are memorized (See, for example, Fig. 5), such that the warpage introduced during PCB processing is substantially removed at the final bake step (See, for example, Fig. 6). Furthermore, Park teaches a copper clad laminate in which copper foils 110 are laminated onto both the upper and lower faces of a core material comprising glass fiber 120 impregnated with shape memory polymer 130 (See, Figs. 4 and 5), the copper foils being provided as the conductive layers from which the circuit patterns of the PCB are subsequently formed, and Park further teaches that the PCB so formed is assembled with an integrated circuit chip through a die attach operation and solder balls 21 (See, Fig. 2). A person of ordinary skill in the art would have recognized that copper foils disposed on opposite faces of a dielectric core serve no signal-routing purpose in isolation. The two conductive layers must be electrically interconnected through the intervening dielectric for the board to provide the electrical connection paths that Park expressly identifies as the function of the conductive copper circuit. It is therefore necessary to provide a conductive structure extending through the SMP impregnated core material to connect the copper foil 110 on one face to the copper foil 110 on the opposing face, this being the conventional plated through hole arrangement of double-sided and multilayer PCBs that Park identifies as the field of the invention. Cho confirms that such an arrangement was well known and clearly teaches the resulting structure, disclosing a via 150 formed of a conductive metal penetrating through the core part 100 so as to connect the first wiring layers 210 disposed on opposing surfaces of the core part (See, Figs. 1A, 6A, and 6B). Hence the combination of Cho and Park yields a conductive structure extending at least partially through the SMP. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Cho by incorporating shape memory polymer of Park because this provides the advantages of increased mechanical strength, reduced warpage, improved reliability, and enablement of thinner, more compact electronic devices. In regards to claim 2, Cho as modified above discloses (See, annotated Fig. 4 attached below, Park) the SMP (SMP4) is directly on a topmost buildup layer (Buildup2). In regards to claim 3, Cho as modified above discloses (See, for example, annotated Fig. 4 attcahed below, Park) the SMP (SMP3) is directly contacting the core (Core). In regards to claim 4, Cho as modified above discloses the SMP. However, Cho as modified above is silent about the SMP being embedded in the buildup layers. It is well known in the art to embed Shape memory polymer in the build up layers to help prevent microcracking in the vias or internal traces. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to embed shape memory polymer in the buildup layers because it is well known in the art to embed Shape memory polymer in the buildup layers to help prevent microcracking in the vias or internal traces. In regards to claim 11, Cho as modified by Park discloses (See, for example, Fig. 5/6, Park) the SMP is actuated with a heating process. In regards to claim 13, Cho as modified above discloses (See, for example, Fig. 1, Park) the package substrate (1000) is coupled to a processor (500) of a computing system . 07-21-aia AIA Claim s 5-6, 9, 12, 14-16, 19 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Park and Weiss et al. (USPN 9447253 B2, hereinafter “Weiss”) . In regards to claims 5 and 6, Cho as modified above discloses all limitations of claim 1 but the SMP comprises poly (ether ether ketone) (PEEK); and the PEEK is sulfonated. Weiss while disclosing a high temperature Shape Memory polymer teaches SMP comprises poly (ether ether ketone) (PEEK) (See, for example, Col. 9 lines 46-59) ; and the PEEK is sulfonated (See, for example, Col. 9 lines 60-65). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Cho by Weiss because this would help provide high performance polymer that is solvent-soluble for liquid-phase buildup processing while providing a tunable, high-temperature transition necessary to survive electronic assembly ambient. In regards to claim 9, Cho as modified above discloses all limtations of claim 1 except that the SMP is provided in a keep out zone (KOZ) of the package substrate. Weiss teaches a high-temperature SMP (sulfonated PEEK) designed for "actuation" and "deployable structures" (See, for example, Col. 1, lines 60 thru Col. 2 lines 33). Weiss explicitly teaches that the SMP is used for "changing the SMP from the permanent shape into a temporary shape" (See, for example, Col. 9 lines 46-59)) and that the switching temperature must be precisely controlled to avoid "degradation of the part" (Col. 9 lines 50-51, Also Col. 17 lines 32-44) ). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the SMP of Weiss into a defined Keep-Out Zone (KOZ) at the perimeter of the substrate above in Cho as modified by Park because Weiss teaches that the SMP is used for "reverting from the temporary shape into the permanent shape", a person of ordinary skill in the art would recognize that placing the SMP at the perimeter (the edge) of the substrate provides the maximum mechanical leverage for spraeding. However, Weiss teaches that the SMP must be heated to a "switching temperature" to revert shapes. A person of ordinary skill in the art would be motivated to define a Keep-Out Zone around this perimeter SMP to ensure it is "isolated from non-shape memory material" and heat-generating components, thereby preventing "accidental triggering" or "physical interference" during the shape-change transition. In conclusion, defining a KOZ at a perimeter to house an active SMP is a predictable application of standard PCB design rules (Keep-Out Zones) to the functional requirements of the shape memory polymer taught by Weiss. In regards to claim 12, Cho as modified above discloses (See, for example, Fig. 4, Park) the SMP (130) has a first end and a second end. However, Cho as modified above is silent about the first end of the SMP can be actuated without actuating the second end. Weiss teaches that the SMP transition is triggered by reaching a specific “switching temperature” (See, for example, Col. 1 lines 14-23). Weiss further teaches that the material is used for high temperature actuation (See, for example, Col. 2 lines 18-28). It is also well-known inherent property of the SMP material to exhibit “selective activation” or “localized actuation” because SMPs do not react wholly, they react only where the stimulus (heat or magnetic induction) is applied. Specifically, by applying heat to only one area (localized heating via laser, targeted induction…) allows one portion of the SMP (first end) to reach its glass temperature while the other portion (second end) remains rigid (below the threshold). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use localized actuation because this would help control the movement of the substrate and avoid unnecessary tangling or touching with other internal components during large scale actuation (deformation). In regards to claim 14, Cho discloses (See, for example, Figs. 1 and 6F annotated and included below) a package substrate (1000), comprising: a core (700); buildup layers (800) over the core (700); a polymer (11) on the core (700). Cho is silent about teaching the package substrate comprises a keep out zone (KOZ) around a perimeter of the package substrate; and a shape memory polymer (SMP) positioned in the KOZ of the package substrate. Park teaches (See, for example, Fig. 4) the shape memory polymer (130) over the core (120). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Cho by incorporating shape memory polymer of Park because this provides the advantages of increased mechanical strength, reduced warpage, improved reliability, and enablement of thinner, more compact electronic devices. In regards to a conductive structure extending at least partially through the SMP. Cho teaches a via 150 formed of a conductive metal (e.g., copper) penetrating through the core part 100 and connecting the first wiring layer 210 disposed on opposing surfaces thereof (See, Figs. 1A, 6A/6B). Though Cho is does not expressly teach that the resin layer over the core comprises a shape memory polymer, Park teaches a printed circuit board in which a shape memory polymer 130 is impregnated into the core material in place of the conventional polymer resin, at approximately the same 40% ratio (See, for example, Fig. 4 and Tech Solution), the SMP being a synthetic resin that returns a memorized flat shape upon heating above the shape recovery temperature, and the board being pressed flat at the pre-shipment bake temperature so that the flat shape and temperature condition are memorized (See, for example, Fig. 5), such that the warpage introduced during PCB processing is substantially removed at the final bake step (See, for example, Fig. 6). Furthermore, Park teaches a copper clad laminate in which copper foils 110 are laminated onto both the upper and lower faces of a core material comprising glass fiber 120 impregnated with shape memory polymer 130 (See, Figs. 4 and 5), the copper foils being provided as the conductive layers from which the circuit patterns of the PCB are subsequently formed, and Park further teaches that the PCB so formed is assembled with an integrated circuit chip through a die attach operation and solder balls 21 (See, Fig. 2). A person of ordinary skill in the art would have recognized that copper foils disposed on opposite faces of a dielectric core serve no signal-routing purpose in isolation. The two conductive layers must be electrically interconnected through the intervening dielectric for the board to provide the electrical connection paths that Park expressly identifies as the function of the conductive copper circuit. It is therefore necessary to provide a conductive structure extending through the SMP impregnated core material to connect the copper foil 110 on one face to the copper foil 110 on the opposing face, this being the conventional plated through hole arrangement of double-sided and multilayer PCBs that Park identifies as the field of the invention. Cho confirms that such an arrangement was well known and clearly teaches the resulting structure, disclosing a via 150 formed of a conductive metal penetrating through the core part 100 so as to connect the first wiring layers 210 disposed on opposing surfaces of the core part (See, Figs. 1A, 6A, and 6B). Hence the combination of Cho , Park, and Weiss yields a conductive structure extending at least partially through the SMP. However, Cho as modified by Park further fails to explicitly teach that Cho is silent about teaching the package substrate comprises a keep out zone (KOZ) around a perimeter of the package substrate; and a shape memory polymer (SMP) positioned in the KOZ of the package substrate. Weiss teaches a high-temperature SMP (sulfonated PEEK) designed for "actuation" and "deployable structures" (See, for example, Col. 1, lines 60 thru Col. 2 lines 33). Weiss explicitly teaches that the SMP is used for "changing the SMP from the permanent shape into a temporary shape" (See, for example, Col. 9 lines 46-59)) and that the switching temperature must be precisely controlled to avoid "degradation of the part" (Col. 9 lines 50-51, Also Col. 17 lines 32-44) ). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the SMP of Weiss into a defined Keep-Out Zone (KOZ) at the perimeter of the substrate above in Cho as modified by Park because Weiss teaches that the SMP is used for "reverting from the temporary shape into the permanent shape", a person of ordinary skill in the art would recognize that placing the SMP at the perimeter (the edge) of the substrate provides the maximum mechanical leverage for spreading. However, Weiss teaches that the SMP must be heated to a "switching temperature" to revert shapes. A person of ordinary skill in the art would be motivated to define a Keep-Out Zone around this perimeter SMP to ensure it is "isolated from non-shape memory material" and heat-generating components, thereby preventing "accidental triggering" or "physical interference" during the shape-change transition. In conclusion, defining a KOZ at a perimeter to house an active SMP is a predictable application of standard PCB design rules (Keep-Out Zones) to the functional requirements of the shape memory polymer taught by Weiss. In regards to claims, 15 and 16, Cho as modified above discloses the SMP comprises poly (ether ether ketone) (PEEK) (See, for example, Col. 9 lines 46-59, Weiss) ; and the PEEK is sulfonated (See, for example, Col. 9 lines 60-65, Weiss). In regards to claim 19, Cho as modified above discloses a plurality of SMP regions are provided around a perimeter of the KOZ. In regards to claim 21, Cho as modified by Park discloses (See, for example, Fig. 5/6, Park) the SMP is actuated with a heating process. In regards to claim 22, Cho as modified above discloses (See, for example, Fig. 4, Park) the SMP (130) has a first end and a second end. However, Cho as modified above is silent about the first end and the second end can be independently articulated. Weiss teaches that the SMP transition is triggered by reaching a specific “switching temperature” (See, for example, Col. 1 lines 14-23). Weiss further teaches that the material is used for high temperature actuation (See, for example, Col. 2 lines 18-28). It is also well-known inherent property of the SMP material to exhibit “selective activation” or “localized actuation” because SMPs do not react wholly, they react only where the stimulus (heat or magnetic induction) is applied. Specifically, by applying heat to only one area (localized heating via laser, targeted induction…) allows one portion of the SMP (first end) to reach its glass temperature while the other portion (second end) remains rigid (below the threshold). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use localized actuation because this would help control the movement of the substrate and avoid unnecessary tangling or touching with other internal components during large scale actuation (deformation) . 07-22-aia AIA Claim s 7-8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Park as applied to claim 1 above, and further in view of Mohr et al. (NPL, “2006”, “Initiation of shape-memory effect by inductive heating of magnetic nanoparticles in thermoplastic polymers”, Vol 103, no. 10, 3540-3545, hereinafter “Mohr”) . In regards to claim 7, 8, 10 and 11, Cho as modified above teaches all limitations of claim 1 except that the SMP comprises: magnetic particles, the magnetic particles comprise one or more of iron and oxygen, or neodymium, iron, and boron, or nickel, iron, and boron; and the SMP is actuated with a magnetic induction process. Mohr teaches that SMPs can be infused with ferromagnetic or ferromagnetic nanoparticles (e.g. Fe 2 O 3 ) and this composite material is designed to generate internal heat via hysteresis loss when subjected to an alternating magnetic field. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use magnetic particles infused SMPs because this would help only heat the magnetic particles while other part of the substrate (with sensitive electronics) remains relatively cool . 07-22-aia AIA Claim s 17-18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Park and Weiss as applied to claim 14 above, and further in view of Mohr . In regards to claim 17, 18, 20 and 21, Cho as modified above teaches all limitations of claim 1 except that the SMP comprises: magnetic particles, the magnetic particles comprise one or more of iron and oxygen, or neodymium, iron, and boron, or nickel, iron, and boron; the SMP is configured to articulate with application of a magnetic field; and SMP is configured to articulate with the addition of thermal energy. Mohr teaches that SMPs can be infused with ferromagnetic or ferromagnetic nanoparticles (e.g. Fe 2 O 3 ) and this composite material is designed to generate internal heat via hysteresis loss when subjected to an alternating magnetic field. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use magnetic particles infused SMPs because this would help only heat the magnetic particles while other part of the substrate (with sensitive electronics) remains relatively cool . 07-21-aia AIA Claim s 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Dory et al. (US 2004/0118594 A1, hereinafter “Dory”) in view of Cho and Park . In regards to claim 23, Dory discloses (See, for example, Fig. 1) a computing system (5), comprising: a board (24); a package substrate (20) coupled to the board (24). a die (10) coupled to the package substrate (20). Dory is silent about a shape memory polymer (SMP) over the core. Cho discloses (See, for example, Figs. 1 and 6F annotate and attached below) wherein the package substrate (1000) comprises: a core (10); a buildup layer (800) over the core (10); and a polymer (11 over the core; and a die (500, Fig. 1) coupled to the package substrate (1000). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Dory by Cho because this would help prevent deformities such as warpage occurring during manufacturing. Dory as modified by Cho is silent about having the shape memory polymer over the core. However, Park while disclosing a PCB substrate teaches (See, for example, Fig. 4) the shape memory polymer (130) over the core (120). In regards to a conductive structure extending at least partially through the SMP. Cho teaches a via 150 formed of a conductive metal (e.g., copper) penetrating through the core part 100 and connecting the first wiring layer 210 disposed on opposing surfaces thereof (See, Figs. 1A, 6A/6B). Though Cho is does not expressly teach that the resin layer over the core comprises a shape memory polymer, Park teaches a printed circuit board in which a shape memory polymer 130 is impregnated into the core material in place of the conventional polymer resin, at approximately the same 40% ratio (See, for example, Fig. 4 and Tech Solution), the SMP being a synthetic resin that returns a memorized flat shape upon heating above the shape recovery temperature, and the board being pressed flat at the pre-shipment bake temperature so that the flat shape and temperature condition are memorized (See, for example, Fig. 5), such that the warpage introduced during PCB processing is substantially removed at the final bake step (See, for example, Fig. 6). Furthermore, Park teaches a copper clad laminate in which copper foils 110 are laminated onto both the upper and lower faces of a core material comprising glass fiber 120 impregnated with shape memory polymer 130 (See, Figs. 4 and 5), the copper foils being provided as the conductive layers from which the circuit patterns of the PCB are subsequently formed, and Park further teaches that the PCB so formed is assembled with an integrated circuit chip through a die attach operation and solder balls 21 (See, Fig. 2). A person of ordinary skill in the art would have recognized that copper foils disposed on opposite faces of a dielectric core serve no signal-routing purpose in isolation. The two conductive layers must be electrically interconnected through the intervening dielectric for the board to provide the electrical connection paths that Park expressly identifies as the function of the conductive copper circuit. It is therefore necessary to provide a conductive structure extending through the SMP impregnated core material to connect the copper foil 110 on one face to the copper foil 110 on the opposing face, this being the conventional plated through hole arrangement of double-sided and multilayer PCBs that Park identifies as the field of the invention. Cho confirms that such an arrangement was well known and clearly teaches the resulting structure, disclosing a via 150 formed of a conductive metal penetrating through the core part 100 so as to connect the first wiring layers 210 disposed on opposing surfaces of the core part (See, Figs. 1A, 6A, and 6B). Hence the combination of Cho and Park yields a conductive structure extending at least partially through the SMP. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Dory by Cho incorporating shape memory polymer of Park because this provides the advantages of increased mechanical strength, reduced warpage, improved reliability, and enablement of thinner, more compact electronic devices. In regards to claim 25, Dory as modified above discloses (See, for example, Fig. 1, Dory) the computing system (5) is part of a personal computer, a mobile device, a tablet, a server, or an automobile (See, for example, Par [0005]) . 07-22-aia AIA Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Dory in view of Cho and Park as applied to claim 23 above, and further in view of Weiss . In regards to claim 24, Dory as modified above discloses all limitations of claim 23 except that the SMP is in a keep out zone (KOZ) of the package substrate. Weiss teaches a high-temperature SMP (sulfonated PEEK) designed for "actuation" and "deployable structures" (See, for example, Col. 1, lines 60 thru Col. 2 lines 33). Weiss explicitly teaches that the SMP is used for "changing the SMP from the permanent shape into a temporary shape" (See, for example, Col. 9 lines 46-59)) and that the switching temperature must be precisely controlled to avoid "degradation of the part" (Col. 9 lines 50-51, Also Col. 17 lines 32-44) ). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the SMP of Weiss into a defined Keep-Out Zone (KOZ) at the perimeter of the substrate above in Cho as modified by Park because Weiss teaches that the SMP is used for "reverting from the temporary shape into the permanent shape", a person of ordinary skill in the art would recognize that placing the SMP at the perimeter (the edge) of the substrate provides the maximum mechanical leverage for spraeding. However, Weiss teaches that the SMP must be heated to a "switching temperature" to revert shapes. A person of ordinary skill in the art would be motivated to define a Keep-Out Zone around this perimeter SMP to ensure it is "isolated from non-shape memory material" and heat-generating components, thereby preventing "accidental triggering" or "physical interference" during the shape-change transition. In conclusion, defining a KOZ at a perimeter to house an active SMP is a predictable application of standard PCB design rules (Keep-Out Zones) to the functional requirements of the shape memory polymer taught by Weiss . PNG media_image1.png 396 656 media_image1.png Greyscale PNG media_image2.png 468 746 media_image2.png Greyscale Response to Arguments 07-37 AIA Applicant's arguments filed on 04/16/2026 have been fully considered but they are not persuasive. Applicant makes the following argument: 1. “As the Examiner points out, "Cho is silent about having the shape memory polymer over the core." Instead, the Examiner points to shape memory polymer 130 and core 120 of Park. (See Office Action, Page 3; see also Examiner's Annotated Figure 4 of Park, shown below.)However, Applicant does NOT understand Park as disclosing a conductive structure extending at least partially through one of the SMP layers. Thus, the combination of Cho in view of Park does not disclose a package substrate including a core, a shape memory polymer (SMP) over the core, and a conductive structure extending at least partially through the SMP, as is required by Applicant's claims. As such, with respect to amended independent claims 1, , 14 and 23, the combination of Cho in view of Park fails to disclose each and every feature of Applicant's claims.” (See Applicant’s remark PP 7-8). This is not persuasive because Cho teaches a via 150 formed of a conductive metal (e.g., copper) penetrating through the core part 100 and connecting the first wiring layer 210 disposed on opposing surfaces thereof (See, Figs. 1A, 6A/6B). Though Cho does not expressly teach that the resin layer over the core comprises a shape memory polymer, Park teaches a printed circuit board in which a shape memory polymer 130 is impregnated into the core material in place of the conventional polymer resin, at approximately the same 40% ratio (See, for example, Fig. 4 and Tech Solution), the SMP being a synthetic resin that returns a memorized flat shape upon heating above the shape recovery temperature, and the board being pressed flat at the pre-shipment bake temperature so that the flat shape and temperature condition are memorized (See, for example, Fig. 5), such that the warpage introduced during PCB processing is substantially removed at the final bake step (See, for example, Fig. 6). Furthermore, Park teaches a copper clad laminate in which copper foils 110 are laminated onto both the upper and lower faces of a core material comprising glass fiber 120 impregnated with shape memory polymer 130 (See, Figs. 4 and 5), the copper foils being provided as the conductive layers from which the circuit patterns of the PCB are subsequently formed, and Park further teaches that the PCB so formed is assembled with an integrated circuit chip through a die attach operation and solder balls 21 (See, Fig. 2). A person of ordinary skill in the art would have recognized that copper foils disposed on opposite faces of a dielectric core serve no signal-routing purpose in isolation. The two conductive layers must be electrically interconnected through the intervening dielectric for the board to provide the electrical connection paths that Park expressly identifies as the function of the conductive copper circuit. It is therefore necessary to provide a conductive structure extending through the SMP impregnated core material to connect the copper foil 110 on one face to the copper foil 110 on the opposing face, this being the conventional plated through hole arrangement of double-sided and multilayer PCBs that Park identifies as the field of the invention. Cho confirms that such an arrangement was well known and clearly teaches the resulting structure, disclosing a via 150 formed of a conductive metal penetrating through the core part 100 so as to connect the first wiring layers 210 disposed on opposing surfaces of the core part (See, Figs. 1A, 6A, and 6B). Hence the combination of Cho and Park yields a conductive structure extending at least partially through the SMP, and the prima-facie case of obviousness is deemed to be proper. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893 Application/Control Number: 18/071,257 Page 2 Art Unit: 2893 Application/Control Number: 18/071,257 Page 3 Art Unit: 2893 Application/Control Number: 18/071,257 Page 4 Art Unit: 2893 Application/Control Number: 18/071,257 Page 5 Art Unit: 2893 Application/Control Number: 18/071,257 Page 6 Art Unit: 2893 Application/Control Number: 18/071,257 Page 7 Art Unit: 2893 Application/Control Number: 18/071,257 Page 8 Art Unit: 2893 Application/Control Number: 18/071,257 Page 9 Art Unit: 2893 Application/Control Number: 18/071,257 Page 10 Art Unit: 2893 Application/Control Number: 18/071,257 Page 11 Art Unit: 2893 Application/Control Number: 18/071,257 Page 12 Art Unit: 2893 Application/Control Number: 18/071,257 Page 13 Art Unit: 2893 Application/Control Number: 18/071,257 Page 14 Art Unit: 2893 Application/Control Number: 18/071,257 Page 15 Art Unit: 2893 Application/Control Number: 18/071,257 Page 16 Art Unit: 2893 Application/Control Number: 18/071,257 Page 17 Art Unit: 2893 Application/Control Number: 18/071,257 Page 18 Art Unit: 2893
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