DETAILED ACTION
This office action addresses Applicant’s response filed on 29 May 2026. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract mental processes without significantly more. The claim(s) recite(s) detecting an issue in a register transfer level (RTL) circuit description, receiving and capturing a selection to waive the issue, detecting a second issue while generating a netlist, and based on the selection to waive the issue, bypassing invocation of a check for the issue while generating a netlist or gate level description of the electronic circuit design, wherein the issue is an unconnected signal in claims 1-7 and 15-20, and is a duplicate label in claims 8-14, which are abstract mental steps that could be performed by a designer in the mind or with pen and paper. A designer performs the claimed process by noting an issue in an RTL design, deciding (or being told) to waive the issue, remembering the waiver, and not checking the waived issue in subsequent design steps.
This judicial exception is not integrated into a practical application because the only claim limitations beyond the abstract idea itself are merely limitations for generic computer implementation of the abstract idea, such as a memory and processor, EDA operations/tools, and data structures. Generic computer implementation of an abstract idea does not qualify as integration of the abstract idea into a patentable practical application. Similarly, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because generic computer implementation of an abstract idea does not qualify as ‘significantly more’ than the abstract idea itself.
Claim 2 recites capturing a location of the issue, claim 4 recites an error message and label for an optimization, claim 5 recites noting the register optimization in an output, and claim 6 recites converting message syntax, mapping messages, and adding labels to messages, which could be performed by a designer with pen and paper, and outputting messages is merely insignificant post-solution activity. Claims 3 and 7 recite determining a register optimization comprising removal of a register, which could be performed by a designer in the mind or with pen and paper. All other claims are analogous to the claims discussed above and are rejected under the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganai (US 2016/0259879) in view of McBride (US 6,434,723) and Fisher (US 2003/0221173).
Regarding claim 1, Ganai discloses a method for verifying an electronic circuit design, the method comprising: detecting an issue in a register transfer level description of the electronic circuit design using a first electronic design automation (EDA) verification operation (¶8), receiving a selection to waive the issue, capturing the selection to waive the issue in a waiver data structure used by a downstream EDA operation (¶¶25-26), and based on the selection to waive the issue, controlling a downstream EDA synthesis or implementation operation to bypass invocation of a check for the issue while generating a netlist or gate level description of the electronic circuit design (¶¶25, 26, 53, 65, 66).
If Ganai is found to be unclear regarding bypassing invocation of a check for the issue, persons having ordinary skill in the art would recognize that instead of ignoring issues that have been waived, checks for waived issues could also be bypassed to save time, as evidenced by McBride (col. 7, lines 14-25; col. 8, lines 2-8). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai and McBride, because doing so would have involved merely the routine combination of known elements according to known techniques, or the substitution of one element for a known equivalent to produce merely the predictable results of skipping verification of waived issues to save time. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Ganai discloses waiving an issue identified during RTL verification, and then ignoring or skipping checking of the issue during netlist generation. McBride provides further explicit evidence that refraining from checking for an issue is a known alternative to ignoring the results of checking for the issue. The teachings of McBride are directly applicable to Ganai in the same way, so that Ganai would similarly refraing from checking for waived issues to save time.
Ganai does not appear to explicitly disclose that the issue is an unconnected signal; Fisher discloses these limitations (¶15). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai, McBride, and Fisher, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of waiving identified issues of signals being unconnected. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Ganai teaches waiving an identified issue and then ignoring/skipping subsequent checks of the issue. Fisher teaches that the identified issue is an unconnected signal. The teachings of Fisher are directly applicable to Ganai in the same way, so that Ganai would similarly skip subsequent checks of waived issues of unconnected signals.
Claim 15 is directed to a non-transitory computer readable medium storing instructions for performing the method of claim 1, and is rejected under the same reasoning. Ganai further discloses a non-transitory computer readable medium storing instructions for performing the claimed method (¶12).
Claim(s) 2 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganai in view of McBride, Fisher, and Fey (US 2014/0089899).
Regarding claims 2 and 16, Ganai discloses capturing, in the memory, a location of the issue in the register transfer level description (¶¶27-51); as discussed above with regard to claim 1, Ganai does not appear to explicitly disclose that the issue is an unconnected signal, but Fisher discloses these limitations (¶15). Motivation to combine remains consistent with claim 1.
If Ganai is found to be unclear regarding the location of the issue, Fey discloses the same (¶12). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai, McBride, Fisher, and Fey, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of indicating locations of identified issues. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Ganai teaches identifying issues and their locations. Fey provides additional explicit disclosure of determining issue locations. The teachings of Fey are directly applicable to Ganai in the same way, so that Ganai would similarly indicate locations of identified issues.
Claim(s) 3-5, 7, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganai in view of McBride, Fisher, and Pathak (US 8,166,427).
Regarding claims 3 and 17, Ganai does not appear to explicitly disclose determining a register optimization prior to generating the netlist or gate level description; and adding, to the memory, an indication of the register optimization. Pathak discloses these limitations (Fig. 1; col. 4, lines 19-20; col. 5, lines 41-43; col. 7, lines 20-21). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai, McBride, Fisher, and Pathak, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of optimizing a netlist while tracking the causes or reasons for optimizations. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Ganai discloses generating a netlist. Pathak teaches that the netlist should be optimized while tracking the causes for each optimization, thus providing useful information to users. The teachings of Pathak are directly applicable to Ganai in the same way, so that Ganai would similarly optimize the netlist while tracking causes.
Regarding claims 4 and 18, Ganai does not appear to explicitly disclose that the indication of the register optimization comprises an error message and a label indicating that the error message is for a determined optimization; Pathak discloses these limitations (Fig. 8). Motivation to combine remains consistent with claim 3.
Regarding claims 5 and 19, Ganai does not appear to explicitly disclose based on determining that the register optimization is indicated in the memory, noting the register optimization in an output; Pathak discloses these limitations (col. 7, lines 20-21; Fig. 8). Motivation to combine remains consistent with claim 3.
Regarding claim 7, Ganai does not appear to explicitly disclose that the register optimization comprises removal of a register; Pathak discloses these limitations (col. 7, lines 20-21; Fig. 8). Motivation to combine remains consistent with claim 3.
Claim(s) 6 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganai in view of McBride, Fisher, Pathak and Arcand (US 2004/0153822).
Regarding claims 6 and 20, Ganai does not appear to explicitly disclose that adding the indication of the register optimization to the memory comprises: converting a message indicating the register optimization to an extensible markup language (XML) message; mapping the XML message to an error message; and adding a label to the error message to produce the indication of the register optimization. Pathak discloses a message indicating the register optimization; mapping the message to an error message and adding a label to the error message to produce the indication of the register optimization (Fig. 8); motivation to combine remains consistent with claim 3.
XML is an industry-standard data format for messages like Pathak’s; Arcand discloses converting a message to an extensible markup language (XML) message (¶77). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai, McBride, Fisher, Pathak, and Arcand, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of converting test outputs to standard formats. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Ganai discloses generating and verifying a netlist, which Pathak teaches should be optimized while outputting messages. Arcand teaches that the messages should be converter to standard formats for output. The teachings of Pathak and Arcand are directly applicable to Ganai in the same way, so that Ganai would similarly optimize the netlist while outputting messages in standard formats.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganai in view of McBride and Garlapati (US 8,667,436).
Regarding claim 8, Ganai discloses a system for verifying an electronic circuit design, the system comprising: a memory and a processor communicatively coupled to the memory (¶12), the processor configured to: detect an issue in a register transfer level description of the electronic circuit design using a first electronic design automation (EDA) verification operation (¶8), receiving a selection to waive the issue, capture the selection to waive the issue in a waiver data structure used by a downstream EDA operation (¶¶25-26), controlling a downstream EDA synthesis or implementation operation to bypass invocation of a check for the issue while generating a netlist or gate level description of the electronic circuit design (¶¶25, 26, 53, 65, 66).
If Ganai is found to be unclear regarding bypassing invocation of a check for the issue, persons having ordinary skill in the art would recognize that instead of ignoring issues that have been waived, checks for waived issues could also be bypassed to save time, as evidenced by McBride (col. 7, lines 14-25; col. 8, lines 2-8). Motivation to combine remains consistent with claim 1.
Ganai does not appear to explicitly disclose that the issue is a duplicate label; Garlapati discloses these limitations (col. 2, lines 42-47). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai, McBride, and Garlapati, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of waiving identified issues of duplicate labels. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Ganai teaches waiving an identified issue and then ignoring/skipping subsequent checks of the issue. Garlapati teaches that the identified issue is a duplicate label. The teachings of Garlapati are directly applicable to Ganai in the same way, so that Ganai would similarly skip subsequent checks of waived issues of duplicate labels.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganai in view of McBride, Garlapati, and Fey.
Regarding claim 9, Ganai discloses capturing, in the memory, a location of the issue in the register transfer level description (¶¶27-51); as discussed above with regard to claim 8, Ganai does not appear to explicitly disclose that the issue is a duplicate label, but Garlapati discloses these limitations (¶15). Motivation to combine remains consistent with claim 8.
If Ganai is found to be unclear regarding the location of the issue, Fey discloses the same (¶12). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai, McBride, Garlapati, and Fey, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of indicating locations of identified issues. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Ganai teaches identifying issues and their locations. Fey provides additional explicit disclosure of determining issue locations. The teachings of Fey are directly applicable to Ganai in the same way, so that Ganai would similarly indicate locations of identified issues.
Claim(s) 10-12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganai in view of McBride, Garlapati, and Pathak (US 8,166,427).
Regarding claim 10, Ganai does not appear to explicitly disclose determining a register optimization prior to generating the netlist or gate level description; and adding, to the memory, an indication of the register optimization. Pathak discloses these limitations (Fig. 1; col. 4, lines 19-20; col. 5, lines 41-43; col. 7, lines 20-21). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai, McBride, Garlapati, and Pathak, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of optimizing a netlist while tracking the causes or reasons for optimizations. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Ganai discloses generating a netlist. Pathak teaches that the netlist should be optimized while tracking the causes for each optimization, thus providing useful information to users. The teachings of Pathak are directly applicable to Ganai in the same way, so that Ganai would similarly optimize the netlist while tracking causes.
Regarding claim 11, Ganai does not appear to explicitly disclose that the indication of the register optimization comprises an error message and a label indicating that the error message is for a determined optimization; Pathak discloses these limitations (Fig. 8). Motivation to combine remains consistent with claim 10.
Regarding claim 12, Ganai does not appear to explicitly disclose based on determining that the register optimization is indicated in the memory, noting the register optimization in an output; Pathak discloses these limitations (col. 7, lines 20-21; Fig. 8). Motivation to combine remains consistent with claim 10.
Regarding claim 14, Ganai does not appear to explicitly disclose that the register optimization comprises removal of a register; Pathak discloses these limitations (col. 7, lines 20-21; Fig. 8). Motivation to combine remains consistent with claim 10.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganai in view of McBride, Garlapati, Pathak and Arcand.
Regarding claim 13, Ganai does not appear to explicitly disclose that adding the indication of the register optimization to the memory comprises: converting a message indicating the register optimization to an extensible markup language (XML) message; mapping the XML message to an error message; and adding a label to the error message to produce the indication of the register optimization. Pathak discloses a message indicating the register optimization; mapping the message to an error message and adding a label to the error message to produce the indication of the register optimization (Fig. 8); motivation to combine remains consistent with claim 3.
XML is an industry-standard data format for messages like Pathak’s; Arcand discloses converting a message to an extensible markup language (XML) message (¶77). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Ganai, McBride, Garlapati, Pathak, and Arcand, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of converting test outputs to standard formats. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Ganai discloses generating and verifying a netlist, which Pathak teaches should be optimized while outputting messages. Arcand teaches that the messages should be converter to standard formats for output. The teachings of Pathak and Arcand are directly applicable to Ganai in the same way, so that Ganai would similarly optimize the netlist while outputting messages in standard formats.
Response to Arguments
Applicant's arguments filed 29 May 2026 have been fully considered but they are not persuasive.
Applicant asserts that the claims have been amended to recite specific improvement in the operation and interoperability of electronic design automation (EDA) verification and synthesis systems, and that the claims are patent-eligible because the claimed operations cannot practically be performed mentally or with pen and paper. Remarks 8. The examiner disagrees. The claims are directed to avoiding redundant work by not checking for issues that have previously been waived, either by the same designer or different designers (see Specification at ¶22-23). Certainly, because the claims are implemented using computers, design steps are performed by tools and information is stored and transmitted in data structures, but these do not change the fundamental underlying invention of sharing waiver information to avoid redundant work. Rather, the claimed tools and data structures are simply facets of the generic computer implementation of the otherwise abstract idea. Under Applicant’s reasoning, essentially any computer-implemented claim would be rendered patent-eligible simply by reciting every element in its computer-implemented form (tools, programs, files, etc.), and the current Alice framework for patent-eligibility may as well not exist as far as computer-implemented inventions are concerned.
Applicant asserts that downstream operations consume propagated waiver information to alter verification behavior during netlist or gate-level generation, so the claimed invention is directed to a specific technological solution rooted in EDA verification and synthesis technology, analogous to claims found eligible in Enfish and McRO. Remarks 9. The examiner disagrees. The claimed invention is sharing waiver information between different design stages to avoid redundant/unnecessary work; the same improvement applies to designers conveying or remembering waiver information from earlier design steps to avoid redundant work in later design steps. Couching the improvement in computer-implemented terms does not transform the abstract idea into a patentable technological solution. Controlling operation of the EDA tool based on transmitted information is simply the computer-implemented version of a designer performing design steps according to information they’ve received or remembered, and computer-implemented tools store and transmit information in computer-readable data structures.
Applicant asserts that the claims also recite significantly more than an abstract idea due to the EDA operations and waiver data structures. Remarks 9. The examiner disagrees. Generic computer implementation of the abstract idea does not amount to ‘significantly more’ than the abstract idea itself under Alice. As discussed above, reciting EDA operations is merely generic computer implementation of circuit design steps, and the waiver data structure is simply generic computer implementation of storing/transmitting information. The amended claim remains directed to the abstract idea of sharing waiver information with downstream design steps, recited in computer-implemented terms such as ‘EDA tool’ and ‘data structure’.
Applicant asserts that Ganai fails to teach “capturing a waiver selection in a waiver data structure that uses a downstream EDA synthesis or implementation operation … Rather, Ganai merely discusses migration of CDC waivers and comparison of CDC verification results.” Remarks 10. The examiner disagrees. Applicant’s assertion is directly and explicitly contradicted by Ganai. ¶¶9 and 25-26 explicitly disclose the creation of waiver file 150 during the RTL design phase, and the waiver file is then read by the netlist design clock domain crossing (NCDC) checker during the netlist design phase, which is after the RTL design phase, to determine issues to ignore. It is not clear to the examiner how Ganai could possibly be read as not teaching “capturing a waiver selection in a waiver data structure that uses a downstream EDA synthesis or implementation operation”, as asserted by Applicant.
Applicant further asserts that Li fails to teach waiver data structures or bypassing invocation of downstream EDA verification checks, and does not relate to “EDA verification flows, synthesis operations, implementation operations, waiver propagation, or control of downstream EDA verification operations”. Remarks 10. Applicant further asserts that the combination relies on impermissible hindsight because persons having ordinary skill in the art would not modify Ganai’s CDC verification flow using Li’s memory-remapping operations. Remarks 11. The examiner disagrees. Li is relied upon as evidence that persons having ordinary skill in the art would clearly recognize that ‘not checking an issue’ is a known alternative to ‘ignoring the issue’. This principle is applicable to Ganai even if Li is not specifically directed to waiver propagation or control of downstream EDA verification. Ganai already teaches the waiver propagation and control of downstream EDA verification, as discussed above, so the application of Li to Ganai would clearly suggest controlling Ganai’s downstream EDA verification to refrain from checking Ganai’s waived issue.
Applicant asserts that “none of Ganai, Li, or Fisher teaches or suggests such downstream operational control using a waiver data structure.” Remarks 11. The examiner disagrees. As discussed above, Ganai clearly and explicitly discloses controlling the netlist design phase, downstream of the RTL design phase, using the waiver file.
Analogous arguments apply to the rejections using Garlapati teaching the specific issue of duplicate labels in place of Fisher teaching the issue of unconnected signals.
Conclusion
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20 June 2026
/ARIC LIN/ Examiner, Art Unit 2851
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