DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/13/2025 have been fully considered but they are not persuasive.
Regarding the claim objections to claim 4, Examiner is unclear on where the clarification for the phrase “the first gallium nitride portion” is. However, as the claim 4 is amended, the corresponding objection is withdrawn.
Regarding the 112(b) rejections for claims 1-10, the amendments satisfy the indefiniteness originally present, and the rejection is withdrawn. However, this amendment introduces new matter, as the wafer is referred to as a chip throughout the specification as well as in the drawings (most obviously Fig. 3). So, while the previous 112(b) rejections have been overcome, new rejections under 112 are made in the rejection to follow.
Regarding the 112(b) rejections for claims 11 and 12, the amendments are sufficient to overcome the rejection, they are subsequently withdrawn.
Regarding the argument against the rejection of claim 1 on page 10 of the Response, Applicant argues that Macelwee teaches only one trench that circumvents the die within the inactive area. While there is one continuous trench surrounding an individual die, before singulation, the inactive area spans from the active area of one chip to the active area of an adjacent die. Within the inactive area on the left of Fig. 6 of Macelwee, it can be seen that there are two trenches (grooves) between active areas on chips, or in the non-active area. These trenches are spaced apart, as claim 1 requires. A suggestion for clarification would be some language to indicate that the plurality grooves are surrounding a singular chip on the wafer, as shown in Applicant’s Fig. 3.
Regarding Applicant’s argument against the rejection of claim 4, Examiner is unclear on the description of the GaN and AlGaN layers being treated as design options. Layer 312 (shown in Fig. 6) is described as a GaN/AlGaN heterostructure in paragraph [0085]. Even if this layer is described as merely a design option, it stands that this structure is disclosed in Macelwee, and thus is disclosed before the effective filing date of the instant application. Regarding the argument that “Macelwee does not specifically disclose a GaN layer in both the active and inactive regions”, Examiner points towards Fig. 6, in which layer 312 exists both in the active region as well as the inactive region, which again is a GaN/AlGaN heterostructure. Applicant also argues that claim 4 requires “an AlGaN layer on top of the GaN layer only in the active region”. However, there is no language indicating this is a necessary limitation in claim 4.
Applicant further presents arguments regarding claims 13 and 4 on pages 11-12 of their response. These arguments are the same as those presented regarding claim 1 on page 10, and are not persuasive for the reasons noted above.
Regarding the argument against the rejection of claim 2, Applicant notes that Macelwee teaches a range wider than that required by the instant application and that Macelwee does not necessitate the ratio to be no less than (2/3). While this is a true statement, the range taught by Macelwee overlaps with the claimed range, making a prima facie case for obviousness exist. Overlapping ranges are not patentably distinct over prior art, as stated in the MPEM 2144.05:
“In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997) (Claim reciting thickness of a protective layer as falling within a range of "50 to 100 Angstroms" considered prima facie obvious in view of prior art reference teaching that "for suitable protection, the thickness of the protective layer should be not less than about 10 nm [i.e., 100 Angstroms]." The court stated that "by stating that ‘suitable protection’ is provided if the protective layer is ‘about’ 100 Angstroms thick, [the prior art reference] directly teaches the use of a thickness within [applicant’s] claimed range."). See also In re Bergen, 120 F.2d 329, 332, 49 USPQ 749, 751-52 (CCPA 1941) (The court found that the overlapping endpoint of the prior art and claimed range was sufficient to support an obviousness rejection, particularly when there was no showing of criticality of the claimed range).”
Further, applicant appears to not include a specified range, merely disclosing the ratio is no less than 2/3, which Macelwee does disclose within the range. The applicant again argues the plurality of grooves, which is discussed above. As such, claim 2 is not patentably distinct over Macelwee.
Applicant further presents arguments regarding claims 7-8, and 11-12 on pages 13-15 of their response. These arguments are the same as those presented regarding claim 1 on page 10, and are not persuasive for the reasons noted above.
Specification
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112. Examples of some unclear, inexact or verbose terms used in the specification are: Throughout the Specification and Figures, "chip" and "wafer" appear to be used interchangeably, please correct for consistency.
Claim Objections
Claims 11-12 and 14 objected to because of the following informalities:
Claim 11 is objected to as it states “a gallium nitride component comprises”, this appears to be a typo meant to state “a gallium nitride component comprising”.
Claim 12 is objected to as it states “a gallium nitride component comprises”, this appears to be a typo meant to state “a gallium nitride component comprising”.
Claim 14 is objected to as the status of the claim is not noted in the amendment. It appears to be (original).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-4, 10 and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Macelwee et al. (US 2017/0256638 A1, hereafter Macelwee).
Regarding claim 1, Macelwee discloses a gallium nitride-based wafer (400, [0082]), comprising:
a substrate (302, [0082]); and
a plurality of gallium nitride components (110, [0082]) disposed on the substrate (302) arranged in an array (Fig. 5, [0082]),
each gallium nitride component (110) of the plurality of gallium nitride components comprises an active region (304, [0082]) and a non-active region (306, [0082]) separately disposed on the substrate (302),
the non-active region (306) surrounds a side surface of the active region (304) (see Fig. 5),
the active region (304) comprises at least one heterojunction formed by a gallium nitride layer and an aluminum gallium nitride layer (312, [0085]),
the non-active region (306) comprises a plurality of grooves (388, [0083]) spaced apart (see annotated Fig. 6),
the plurality of grooves (388) penetrate the non-active region (306) and expose the substrate (302), and
the plurality of grooves (388) are used to isolate adjacent gallium nitride components [0086].
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Regarding claim 3, in Fig. 5 Macelwee discloses the wafer according to claim 1, wherein the non-active region (306, [0082]) further comprises a metal stack (seal ring, 280/380/480, [0082] and [0089]), and the metal stack (380) comprises at least one metal layer stacked at intervals in a first direction (M1 and M2 of seal ring 280 in Fig. 4, [0080] [0085]); and each metal layer of the at least one metal layer is annular (around the die, [0082]), and each metal layer is disposed between the plurality of grooves (388, [0083]) and the active region (308, [0082]).
Regarding claim 4, in Figs. 5 and 6 Macelwee discloses the wafer according claim 1, wherein the gallium nitride layer (312, [0085]) comprises a first gallium nitride portion (corresponding to the active area in Fig. 6) and a second gallium nitride portion (corresponding to the inactive area in Fig. 6) that are both disposed on the substrate (302, [0082]), the aluminum gallium nitride layer (312) is disposed on a surface that is of the first gallium nitride portion (312) and that is away from the substrate (302), and the first gallium nitride portion and the aluminum gallium nitride layer form the heterojunction (312, [0085]); and the non-active region (306, [0082]) comprises the second gallium nitride portion, and the groove (388, [0083]) penetrates the second gallium nitride portion.
Regarding claim 10, in Fig. 5 Macelwee discloses the wafer according to claim 1, wherein adjacent two of the gallium nitride components further comprise a cutting area (dicing street, 308, [0082]).
Regarding claim 13, Macelwee discloses a chip preparation method, comprising:
forming a plurality of gallium nitride components (110, [0082]) on a substrate (302, [0082]), wherein the plurality of gallium nitride components (110) are arranged in an array (Fig. 5, [0082]), each gallium nitride component (110) of the plurality of gallium nitride components (110) comprises an active region (304, [0082]) and a non-active region (306, [0082]) separately disposed on the substrate (302), the non-active region (306) surrounds a side surface of the active region (304), and the active region (304) comprises at least one heterojunction (312, [0085]) formed by a gallium nitride layer and an aluminum gallium nitride layer; and
forming a plurality of grooves (388, [0083]) on the non-active region (306), wherein the plurality of grooves (388) penetrate the non-active region (306) and expose the substrate (302), and the plurality of grooves (388) are used to isolate adjacent gallium nitride components [0086].
Regarding claim 14, Macelwee discloses the method according to claim 13, wherein the forming a plurality of grooves (388, [0083]) on the non-active region (306, [0082]) comprises:
forming a patterned photoresist layer [0099] on a surface that is of the non-active region (306) and that is away from the substrate [0099]; and
using the patterned photoresist layer as a mask [0099], etching the non-active region (306), and exposing the substrate (302, [0082]) to obtain the plurality of grooves (388).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 2, 5-6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Macelwee.
Regarding claim 2, Macelwee discloses the wafer according to claim 1, wherein a ratio of a sum of areas of the plurality of grooves (388, [0083]) to an area of the non-active region (304, [0082]) for each component is not less than 2/3.
Macelwee does not explicitly disclose areas, however they do teach the width of the trenches (grooves) to be 15 µm to 20 µm [0086] and the width of the non-active region to be between about 25 µm to 80 µm [0081]. While these widths are from different embodiments, one skilled in the art would know to combine the two as the one disclosing the non-active region is admitted prior art by Macelwee, and the embodiment disclosing the trenches is simply an improvement on the prior art. Further, one skilled in the art can extrapolate from the widths to see the area ratios vary from 0.1875 (15/80) to .8 (20/25). As there is overlap in the range disclosed in the present app and Macelwee, one skilled in the art would know to adjust the widths disclosed in Macelwee in order to achieve a ratio of a sum of areas within the desired parameters.
While Macelwee teaches a range that extends beyond the bounds of that listed in the instant claim, this ratio appears to be a matter of design, and there is no indication within the written disclosure that this specific dimension would affect the performance of the device over Macelwee. MPEP 2144.05 I states “In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists.”
Regarding claim 5, in Figs. 5 and 6 Macelwee discloses the wafer according to claim 4, wherein the active region (304, [0082]) further comprises a source (Source, Fig. 6), a drain (Drain, Fig. 6), and a gate (Gate, Fig. 6), Macelwee fails to explicitly show in Fig. 6 the source and the drain are respectively connected to two ends of the first gallium nitride portion, and the gate is connected to the aluminum gallium nitride layer, as layer 312 is not depicted in great detail. However, Macelwee supplies prior art, particularly Fig. 2, showing the gate electrode being connected to the aluminum gallium nitride layer (108, [0074]) and both the source and drain being connected to two ends of the first gallium nitride portion (106, [0074]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Macelwee to show the layering as depicted in Fig. 2 of Macelwee, as it was already known in the art.
Regarding claim 6, in Figs. 5 and 6 Macelwee discloses the wafer according to claim 4, wherein the active region further comprises a source (Source, Fig. 6), a drain (Drain, Fig. 6), a gate (Gate, Fig. 6).
While Macelwee fails to explicitly show in Fig. 6 a P-type gallium nitride layer, they do disclose prior art describing the inclusion of a P-type gallium nitride layer [0074] that is disposed on a surface that is of the aluminum gallium nitride layer (312, [0085]) and that is away from the first gallium nitride portion (corresponding to the active area in Fig. 6), the source and the drain are respectively connected to two ends of the first gallium nitride portion (as in Fig. 6), and the gate is connected to the P-type gallium nitride layer. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Macelwee with the P-type gallium nitride layer of the prior art disclosed by Macelwee to get the expected result of an enhancement mode HEMT, as disclosed by Macelwee in paragraph [0074].
Regarding claim 9, Macelwee teaches wafer according to claim 1. Macelwee fails to explicitly show the gallium nitride component further comprises a transition layer, the transition layer is disposed between the substrate and the gallium nitride layer, a lattice constant of the transition layer falls between a lattice constant of the substrate and a lattice constant of the gallium nitride layer, and the groove further penetrates the transition layer.
However, Macelwee indicates that it is well known in the art to include transition layers due to the lattice mismatch between the semiconductor layers and the silicon surface [0004]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment shown in Figs. 5 and 6 to include at least one transition layer in order to get the expected result of minimizing cracking during fabrication and defect related reliability issues [0007].
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Macelwee in view of Chang et al. (US 2022/0376066 A1, hereafter Chang).
Regarding claim 7, Macelwee teaches the wafer according to claim 6, wherein the gallium nitride component further comprises a dielectric layer (336 and 338 of BOEL 330 (in the same configuration as 236 and 238), [0085]) that covers the aluminum gallium nitride layer (312, [0085]) and the second gallium nitride portion (corresponding to the non-active region of Fig. 6), the dielectric layer (330) comprises a first dielectric portion (corresponding to the active region of Fig. 6) and a second dielectric portion (corresponding to the non-active region of Fig. 6), the first dielectric portion is a portion that is in the dielectric layer and corresponding to the first gallium nitride portion (corresponding to the active region of Fig. 6), and the second dielectric portion is a portion that is in the dielectric layer (330) and corresponding to the second gallium nitride portion; and the source (Source, Fig. 6) is connected to one end of the first gallium nitride portion through a first hole passing through the dielectric layer (under BRI, the metalizations are filled holes creating an electrical connection between the source/drain and the gallium nitride portion), the drain is connected to the other end of the first gallium nitride portion through a second hole passing through the dielectric layer, the non-active region comprises the second dielectric portion, and the groove (388, [0083]) further penetrates the second dielectric portion (as seen in Fig. 6).
Macelwee fails to show the gate being connected to the P-type gallium nitride layer through a third hole passing through the dielectric layer (in Fig. 6 we see the gate is within the dielectric layer). However, Chang shows a semiconductor device similar to Macelwee in which a gate (26, [0038]) is electrically connected to a p-type gallium nitride layer (14, [0039]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the gate of Macelwee so it extends through the dielectric layer as in Chang in order to get the expected result of creating an electric connection grom the gate to the p-type gallium nitride layer.
Regarding claim 8, Macelwee in view of Chang teaches the wafer according to claim 7. In Figs. 5 and 6, Macelwee fails to show the gallium nitride component further comprises a passivation layer, the passivation layer is disposed on a surface of the dielectric layer that is away from the substrate, and the passivation layer is provided with a hole used to expose the source, the drain, and the gate; and the groove further penetrates the passivation layer.
However, Macelwee teaches another embodiment in Fig. 13 wherein the gallium nitride component further comprises a passivation layer ([0094] discusses the use of more than one passivation layer), the passivation layer is disposed on a surface of the dielectric layer that is away from the substrate, and the passivation layer is provided with a hole (etched through the passivation layer, [0094]) used to expose the source, the drain, and the gate; and the groove further penetrates the passivation layer [0094]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment of Figs. 5 and 6 with the inclusion of the passivation layer as in Fig. 13 in order to seal the exposed surfaces of the overlaying layers of device [0030].
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Macelwee in view of Sriram et al. (US 10,516,043 B1, hereafter Sriram).
Regarding claim 11, Macelwee teaches a gallium nitride-based chip (400, [0082]), comprising:
a substrate (302, [0082]); and
a gallium nitride component (110) comprising an active region (304, [0082]) and a non-active region (306, [0082]) separately disposed on the substrate (302),
the non-active region (306) surrounds a side surface of the active region (304) (see Fig. 5),
the active region (304) comprises at least one heterojunction formed by a gallium nitride layer and an aluminum gallium nitride layer (312, [0085]),
the non-active region (306) comprises a plurality of grooves (388, [0083]) spaced apart (see annotated Fig. 6),
the plurality of grooves (388) penetrate the non-active region (306) and expose the substrate (302), and
the plurality of grooves (388) are used to isolate adjacent gallium nitride components [0086].
Macelwee further teaches each chip being cut into individual dies [0079]. However, Macelwee fails to disclose a power drive circuit or a packaging for the power device that encapsulates a gallium nitride-based die. However, in Fig. 1 Sriram discloses a gallium nitride-based power device including a gallium nitride-based chip (10, column 6 lines 31-34), with the chip being contained in a package (column 6 lines 55-58). This device also can include a power drive circuit (control circuit integrated chip, 30, column 6 lines 41-42). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the individually cut die of Macelwee to put it within packaging and have a power drive circuit, as it is known to be conventional as Sriram states (column 6 line 31).
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Regarding claim 12, Macelwee teaches a gallium nitride-based chip (400, [0082]), comprising:
a substrate (302, [0082]); and
a gallium nitride component (110) comprising an active region (304, [0082]) and a non-active region (306, [0082]) separately disposed on the substrate (302),
the non-active region (306) surrounds a side surface of the active region (304) (see Fig. 5),
the active region (304) comprises at least one heterojunction formed by a gallium nitride layer and an aluminum gallium nitride layer (312, [0085]),
the non-active region (306) comprises a plurality of grooves (388, [0083]) spaced apart (see annotated Fig. 6),
the plurality of grooves (388) penetrate the non-active region (306) and expose the substrate (302), and
the plurality of grooves (388) are used to isolate adjacent gallium nitride components [0086].
Macelwee further teaches each chip being cut into individual dies [0079]. However, Macelwee fails to disclose a circuit or a packaging that encapsulates a gallium nitride-based die. However, in Fig. 1 Sriram discloses a circuit with a gallium nitride-based chip (10, column 6 lines 31-34) being contained in a package (column 6 lines 55-58). This device also can include a power drive circuit (control circuit integrated chip, 30, column 6 lines 41-42). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the individually cut die of Macelwee to put it within packaging and have a power drive circuit, as it is known to be conventional as Sriram states (column 6 line 31).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/ Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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