DETAILED ACTION
This Office Action is in response to the applicant's amendment filed February 9th, 2026. In virtue of this communication, claims 1-7, 9, 10, and 24-27 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 24, and 25 are objected to because of the following informalities: in claim 1, line 9, “dielectric binding film” is understood to be --dielectric bonding film--; claim 24 should end with a period; in claim 25, line 3, “said dielectric bonding film” is understood to be --said first dielectric bonding film--. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9, 10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "said embedded semiconductor die" in line 8. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination this limitation has been understood to be --said semiconductor die--. Claims 2-7, 9, and 10 are also rejected as they depend from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-7, 10, and 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US 6,882,042 B2; hereinafter Zhao) in view of Kim (US 2019/0333895 A1) and further in view of Sunohara et al. (US 2010/0101849 A1; hereinafter Sunohara).
With respect to claim 1, Zhao discloses a flexible substrate embedded die package 600 in at least Fig. 6 with Figs. 1-5 teaching overlapping subject matter comprising:
a multi-layer flexible substrate (comprising 610, 602, 604) comprising a dielectric substrate 610, a top metal layer 602 and a bottom metal layer 604 connected with micro-via interconnection (conductive vias) through said dielectric substrate 610 (see Fig. 6, column 3, line 51-58, and column 5, line 33-56);
a semiconductor die 114 attached by an adhesive (116/110) to said flexible substrate (comprising 610, 602, 604) (see Fig. 6 and column 3, line 43 - column 4, line 2); and
a bonding film 120 surrounding said semiconductor die 114 and sealing said semiconductor die 114 to said flexible substrate (comprising 610, 602, 604) (see Fig. 6 and column 3, line 43 - column 4, line 2) wherein said embedded die package 600 is configured to have electrical connections made between said semiconductor die 114 and other circuitry below said bottom metal layer 604 (see Figs. 6, 7, column 1, line 15-28, column 3, line 19-39, column 5, lines 33-48, 59-67; note solder balls electrically connect to underlaying motherboard / printed circuit board).
Zhao does not explicitly disclose that the bonding film is a dielectric bonding film or wherein the embedded die package is configured to have electrical connections made between said semiconductor die and other circuitry above said dielectric bonding film.
Kim discloses an embedded die package 100 in at least Fig. 1 comprising a dielectric bonding film 118 (see Fig. 1 and paragraph 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the bonding film of Zhao would be a dielectric bonding film because it is well known in the art that such bonding films are well known in the art for providing protection and electrical insulation (see MPEP 2144 I). Additionally, it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
The combination of Zhao and Kim does not disclose wherein the embedded die package is configured to have electrical connections made between said semiconductor die and other circuitry above said dielectric bonding film.
Sunohara disclose a similar package in at least Figs. 1-14 further comprising and embedded die package 2 is configured to have electrical connections made between a semiconductor die 5 and other circuitry 34 above a dielectric bonding film 42 (see Figs. 1-14 and paragraphs 17, 76, 77, 80, 90-92, 99).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the package of Zhao and Kim would have the embedded die package configured to have electrical connections made between said semiconductor die and other circuitry above said dielectric bonding film as taught by Sunohara because by such a configuration the wiring structure can be made simple rather than the related art, a manufacturing cost can be reduced. In addition, since a wiring length can be made short in contrast to the related art, the electric characteristics of the wiring substrate can be improved (see Sunohara: paragraph 18).
With respect to claim 2, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 1 wherein said dielectric substrate 610 comprises polyimide (PI), liquid crystal polymer (LCP), Polyester (PET), polyethylene-naphthalate (PEN), cyclo-olefin polymer (COP), poly tetra fluoro ethylene, or a laminate substrate comprising epoxies and BT, or Teflon or modified Teflon, Syndiotactic Polystyrene (SPS), or Bis Malelmide (BMI) (see Zhao: Fig. 6, column 3, line 51-58, and column 5, line 33-56).
With respect to claim 4, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 1 wherein said adhesive 105 comprises an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), a non- conductive film (NCF), or a non-conductive paste (NCP) (see Kim: Fig. 1 and paragraphs 18, 26, 27; note ACF).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the adhesive of Zhao would comprise an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), a non- conductive film (NCF), or a non-conductive paste (NCP) as taught by Kim because such an ACF layer can connect to hundreds of bond pads on die without shorting each other since it conducts in one direction (see Kim: paragraph 10). Additionally, such adhesive materials are well known in the art and it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
With respect to claim 5, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 1 wherein said dielectric bonding film 118 comprises polyimide, fluoropolymer, polyester, modified epoxy, or thermoset adhesive film such as epoxy, cyanide ester, or acrylic adhesive, reinforced with fibers (see Kim: Fig. 1 and paragraph 24).
With respect to claim 6, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 1 wherein said dielectric bonding film 118 has a glass transition temperature of between about 120 and 170 °C and a coefficient of thermal expansion of between about 10 and 50 at a temperature below the glass transition temperature and between about 70 and 200 at a temperature above the glass transition temperature (see Kim: Fig. 1 and paragraph 24; note same materials for 118 as those of claimed dielectric bonding film; same material same properties MPEP 2112.01 I).
With respect to claim 7, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 1, further comprising circuitry 34 on top of said dielectric bonding film 42 to fan out internal circuitry of said semiconductor die 5 onto said flexible substrate 1 (see Sunohara: Figs. 1-14 and paragraphs 17, 76, 77, 80, 90-92, 99).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the package of Zhao and Kim would further comprise circuitry on top of said dielectric bonding film to fan out internal circuitry of said semiconductor die onto said flexible substrate as taught by Sunohara because by such a configuration the wiring structure can be made simple rather than the related art, a manufacturing cost can be reduced. In addition, since a wiring length can be made short in contrast to the related art, the electric characteristics of the wiring substrate can be improved (see Sunohara: paragraph 18).
With respect to claim 10, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 1, further comprising at least one passive component mounted on top of said dielectric bonding film and connected to internal circuitry of said semiconductor die (see Kim: Figs. 1-5 and paragraphs 21, 23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the package of Zhao, Kim, and Sunohara would further comprise at least one passive component mounted on top of said dielectric bonding film and connected to internal circuitry of said semiconductor die because it is well known in the art that such embedded devices include both passive and active devices (see MPEP 2144 I).
With respect to claim 24, Zhao discloses a flexible substrate embedded die package 600 in at least Fig. 6 with Figs. 1-5 teaching overlapping subject matter comprising:
a first multi-layer flexible substrate (comprising 610, 602, 604) comprising a first dielectric substrate 610, a first top metal layer 602 and a first bottom metal layer 604 connected with first micro-via interconnection (conductive vias) through said first dielectric substrate 610 (see Fig. 6, column 3, line 51-58, and column 5, line 33-56);
a semiconductor die 144 attached by an adhesive (116/110) to said first flexible substrate (comprising 610, 602, 604) (see Fig. 6 and column 3, line 43 - column 4, line 2);
a first bonding film 120 surrounding said semiconductor die 114 and sealing said semiconductor die 114 to said first flexible substrate (comprising 610, 602, 604) (see Fig. 6 and column 3, line 43 - column 4, line 2);
a second multi-layer flexible substrate (comprising 612, 614, 606, 608) comprising a second dielectric substrate 612/614, a second top metal layer 606 and a second bottom metal layer 608 connected with second micro-via interconnection (conductive vias) through said second dielectric substrate 612/614 and attached by a second bonding film (circuit mask 108 and dielectric layers between 604 and 606) to said first multi-layer flexible substrate (comprising 610, 602, 604) with second micro-via interconnection (conductive vias) through said second dielectric substrate 612/614 (see Fig. 6, column 3, line 51-58, and column 5, line 33-48).
Zhao does not explicitly disclose that the first and second bonding films are dielectric bonding films, or circuitry on top of said first dielectric bonding film to fan out internal circuitry of said semiconductor die onto said first flexible substrate.
Kim discloses an embedded die package 100 in at least Fig. 1 comprising a dielectric bonding film 118 (see Fig. 1 and paragraph 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first bonding film of Zhao would be a first dielectric bonding film because it is well known in the art that such bonding films are well known in the art for providing protection and electrical insulation (see MPEP 2144 I). Additionally, it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07). Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second bonding film would be a second dielectric bonding film because metal layers like those of Zhao must be separated by dielectric layer in order to prevent short circuiting (see MPEP 2144 I).
The combination of Zhao and Kim does not disclose circuitry on top of said first dielectric bonding film to fan out internal circuitry of said semiconductor die onto said first flexible substrate.
Sunohara disclose a similar package in at least Figs. 1-14 further comprising circuitry 34 on top of a first dielectric bonding film 42 to fan out internal circuitry of a semiconductor die 5 onto a first substrate 1 (see Figs. 1-14 and paragraphs 17, 76, 77, 80, 90-92, 99).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the package of Zhao and Kim would further comprise circuitry on top of said first dielectric bonding film to fan out internal circuitry of said semiconductor die onto said first flexible substrate as taught by Sunohara because by such a configuration the wiring structure can be made simple rather than the related art, a manufacturing cost can be reduced. In addition, since a wiring length can be made short in contrast to the related art, the electric characteristics of the wiring substrate can be improved (see Sunohara: paragraph 18).
With respect to claim 25, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 24 further comprising: a third micro-via interconnection (comprising 36 in VH2 and 32 in VH1 from top to bottom in Fig. 13) between said circuitry 34 and said first top metal layer 32 through said first dielectric bonding film 42 and said first dielectric substrate 40 (see Sunohara: Figs. 1-13 and paragraphs 71-74, 77, 78, 83-85, 90-92 and note through holes and via holes).
With respect to claim 26, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 24 further comprising: a fourth micro-via interconnection (comprising 36 in VH2, 32 in VH1, and 22 in TH from top to bottom in Fig. 13 ) between said circuitry 34, said first bottom metal layer 32, and said second top metal layer 30 through said first dielectric bonding film 42, said first dielectric substrate 40, and said second dielectric bonding film 42 Sunohara: Figs. 1-13 and paragraphs 71-74, 77, 78, 83-85, 90-92 and note through holes and via holes).
With respect to claim 27, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 24 further comprising: a fifth micro-via interconnection (comprising 36 in VH2, 32 in VH1, 22 in TH, 32 in VH1, and 34 in VH2 from top to bottom in Fig. 13) between said circuitry 34, said first bottom metal layer 32, said second top metal layer 30, and said second bottom metal layer 32 through said first dielectric bonding film 42, said first dielectric substrate 40, said second dielectric bonding film 42, and said second dielectric substrate 40 (Sunohara: Figs. 1-13 and paragraphs 71-74, 77, 78, 83-85, 90-92 and note through holes and via holes).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US 6,882,042 B2; hereinafter Zhao) in view of Kim (US 2019/0333895 A1) and further in view of Sunohara et al. (US 2010/0101849 A1; hereinafter Sunohara) as applied to claim 1 above, and further in view of Kariya et al. (US 2003/0168254 A1; hereinafter Kariya).
With respect to claim 3, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 1.
The combination does not explicitly disclose wherein said flexible substrate has a thickness of between about 10 and 45 µm.
Kariya discloses a similar package in Fig. 1-5 wherein a flexible substrate has a thickness of between about 10 and 45 µm (see Fig. 1-5 and paragraphs 120, 125, 126; note combined thickness of copper foil and insulating resin substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the flexible substrate of the combination of Zhao, Kim, and Sunohara would have a thickness of between about 10 and 45 µm as taught by Kariya since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ordinary skill in the art (see MPEP 2144.05 I).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US 6,882,042 B2; hereinafter Zhao) in view of Kim (US 2019/0333895 A1) and further in view of Sunohara et al. (US 2010/0101849 A1; hereinafter Sunohara) as applied to claim 1 above, and further in view of Nakamura et al. (US 2009/0229862 A1; hereinafter Nakamura).
With respect to claim 9, the combination of Zhao, Kim, and Sunohara discloses the package according to claim 1.
The combination does not explicitly disclose wherein said package has a thickness of less than about 100 µm.
Nakamura discloses a package in at least Figs. 1-3C wherein said package has a thickness of less than about 100 µm (see Figs. 1-3C and paragraphs 67, 69, 76).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the package of the combination of Zhao, Kim, and Sunohara would have a thickness of less than about 100 µm as taught by Nakamura so as to produce a very thin multilayer board that has not been achieved conventionally by combining a film and a multilayer board, and therefore, can be used for reducing the size and thickness of various electronic equipment and portable equipment (see Nakamura: paragraph 130).
Response to Arguments
Applicant's arguments filed February 9th, 2026 have been fully considered but they are not persuasive.
With respect to independent claim 1, the applicant argues that “[n]either Kim nor Zhao teach or suggest that the encapsulant should be flexible, nor do they teach or suggest electrical connection through both the top and the bottom of their packages, as now claimed in Applicants' claim 1.” The examiner respectfully disagrees.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the dielectric bonding film should be flexible) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In response to the applicant’s argument that Kim and Zhao do not teach or suggest electrical connection through both the top and the bottom of their packages, this limitation is taught by new reference Sunohara as outlined above.
With respect to claims 3, 7, and 9, the applicant argues that there is no reason to combine the teachings of Kariya, or Sunohara, or Nakamura into Zhao and Kim. The examiner respectfully disagrees.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). With respect to claim 1, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the flexible substrate of the combination of Zhao, Kim, and Sunohara would have a thickness of between about 10 and 45 µm as taught by Kariya since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ordinary skill in the art (see MPEP 2144.05 I). With respect to claim 7, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the package of Zhao and Kim would further comprise circuitry on top of said dielectric bonding film to fan out internal circuitry of said semiconductor die onto said flexible substrate as taught by Sunohara because by such a configuration the wiring structure can be made simple rather than the related art, a manufacturing cost can be reduced. In addition, since a wiring length can be made short in contrast to the related art, the electric characteristics of the wiring substrate can be improved (see Sunohara: paragraph 18). With respect to claim 9, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the package of the combination of Zhao, Kim, and Sunohara would have a thickness of less than about 100 µm as taught by Nakamura so as to produce a very thin multilayer board that has not been achieved conventionally by combining a film and a multilayer board, and therefore, can be used for reducing the size and thickness of various electronic equipment and portable equipment (see Nakamura: paragraph 130). Additionally, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
With respect to independent claim 24, the applicant argues that “Sunohara does not teach or suggest a die embedded in a flexible substrate. Thus, there would be no reason to combine the teachings of Sunohara regarding a rigid substrate for the flexible substrate of Zhao.” Additionally, the applicant argues that claim 24 has been amended to claim circuitry on the bottom of the second metal layer is configured to be electrically connected to a printed circuit board. The examiner respectfully disagrees.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the package of Zhao and Kim would further comprise circuitry on top of said first dielectric bonding film to fan out internal circuitry of said semiconductor die onto said first flexible substrate as taught by Sunohara because by such a configuration the wiring structure can be made simple rather than the related art, a manufacturing cost can be reduced. In addition, since a wiring length can be made short in contrast to the related art, the electric characteristics of the wiring substrate can be improved (see Sunohara: paragraph 18). Additionally, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., circuitry on the bottom of the second metal layer configured to be electrically connected to a printed circuit board) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claims 1-7, 9, 10, and 24-27 remain rejected as outlined above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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