DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendment with respect to claims 1,2 and 17 overcome the previous rejection under 35 U.S.C 112(b). Thus, the rejection under 35 U.S.C. 112(b) has been withdrawn.
Applicant’s amendment and arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s amendment and arguments with respect to claim 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation “the transmission line” is first introduced in claim 16, and is not defined in claim 15 from which claim 19 depends. Therefore, it is indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et.al. (US-2019/0305428-A1, hereinafter Hwang), in view of Ojefors et.al. (US 2022/0263223-A1, hereinafter Ojefors), and further in view of Yang et. al. (US-2020/0059010-A1, hereinafter Yang) and Ndip et. al. (US-2018/0191053-A1, hereinafter Ndip),
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Regarding Claim 1.
Hwang teaches in Fig.7 A semiconductor package, comprising:
a semiconductor die (#40) having a top surface;
a passivation layer (Fig.7 #200 may be a ceramic/glass/dielectric substrate ) over the top surface;
a first metal layer (#340/#341 interconnect layer) on the first passivation layer (#200);
an antenna (#220) is connected to the first metal layer (#341);
a transmission line (#341) formed in the first metal layer (#340), the transmission line coupling the semiconductor die (#40) to the antenna (#220); and
an insulating material (#520) separating the first metal layer (#340) from a second metal layer (layer above #520, or #211), the second metal layer configured to function as a ground reflector (#211 ground plane) for the antenna (#220). (See Hwang Fig.7 [0043-0051][0059-0065])
Hwang teaches the antenna (#220) is coupled in the first metal layer (#341) but does not explicitly disclose an antenna is formed in the first metal layer.
However, Ojefors teaches an integrated circuit package including an RFIC, at least one antenna array formed in a redistribution metal layer (#25 RDL), and feed lines formed in the RDL and coupled between the antenna and the RFIC (Ojefors, Figs. 1-3, RFIC #21 antenna array #100, crossed dipole antenna #10, feedlines #20a/#20b; first RDL #25). Ojefors expressly teaches that the feed lines may be understood as transmission lines, and the that crossed dipole antennas and their respective feedlines ma be realized in planar transmission-line technology ([0033]), i.e. realized in a single metal layer. Ojefors further teaches that antenna arrays are coupled to the RFIC via the first RDL, and that feed lines extend from the antenna toward the RFIC. (See Ojefors [0029-0035]) It would have been obvious to one of ordinary skill in the art to modify Hwang with the teachings of Ojefors, as identified above, to simplify the antenna feed structure, reduce vertical transitions/vias through the package, reduce form factor, and provide a compact RDL-based antenna feed arrangement suitable for high-frequency IC package.
Hwang modified by Ojefors does not explicitly disclose the antenna having a slot bow-tie configuration and is offset from the semiconductor die.
However, in an analogous art pertaining to semiconductor package with antenna structure, Yang teaches in Fig.6 and in related text: the antenna having a slot bow-tie configuration; (See Yang Fig.6 [0171-0181]) It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Hwang and Ojefors with the teachings of Yang, as identified above, in order to have an antenna design that broadens the bandwidth, enhances performance and robustness, and is suitable for mass production with high repeatability. (Yang [0039])
In addition, Ndip also teaches in an embodiment shown in Fig.5b which arranging the antenna laterally in the redistribution layer such that the antenna’s projection is “offset from” the chip’s projection area and further teaches providing shielding vias between the antenna and the chip to reduce coupling. (Ndip [0013-0018]) It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Hwang and Ojefors with the teachings of Ndip in order to reduce undesired coupling into the silicon, improve radiation efficiency, and provide mechanical/thermal clearance, all well-recognized design objectives with predictable improvement.
Accordingly, the combination of Hwang, Ojefors, Yang and Ndip teaches or renders obvious: A semiconductor package, comprising: a semiconductor die having a top surface; a passivation layer over the top surface; a first metal layer on the first passivation layer; an antenna formed in the first metal layer and offset from the semiconductor die, the antenna having a slot bow-tie configuration; a transmission line formed in the first metal layer, the transmission line coupling the semiconductor die to the antenna; and an insulating material separating the first metal layer from a second metal layer, the second metal layer configured to function as a ground reflector for the antenna. Therefore, claim 1 would have been obvious over Hwang in view of Ojefors, Yang and Ndip.
Regarding Claim 2.
Hwang modified by Ojefors, Yang and Ndip teaches The semiconductor package of claim 1,
Hwang further teaches further comprising:
a conductive pad (Fig.7 #422 contact element) on the top surface of the semiconductor die (#40);
an opening in the passivation layer (#200) to expose the conductive pad;
the transmission line in the first metal layer (#340/#341) in contact with the conductive pad (#422 that connects #40 to first metal layer #341) through the first opening. (Hwang Fig.7)
Regarding Claim 3.
Hwang modified by Ojefors,Yang and Ndip teaches The semiconductor package of claim 1,
Hwang further teaches wherein the transmission line (#341) is a coplanar waveguide. (Hwang Fig.7 [0054] [0059-0065])
Regarding Claim 4.
Hwang modified by Ojefors,Yang and Ndip teaches The semiconductor package of claim 1,
Hwang further teaches wherein the transmission line (#341) comprises three parallel strips in the first metal layer (layer below #520), and wherein the three parallel strips have a ground-signal-ground configuration. (Hwang [0054] Fig.7 ground/signal/ground layout for three coplanar strips)
Regarding Claim 5.
Hwang modified by Ojefors,Yang and Ndip teaches The semiconductor package of claim 1, Hwang further teaches in Fig.7 wherein the second metal layer (layer above #520, including #211) extends below the antenna and the semiconductor die. (Hwang Fig.7 ground layer network including #212/#214 extending below antenna and the die)
Regarding Claim 6.
Hwang modified by Ojefors,Yang and Ndip teaches The semiconductor package of claim 1, Hwang further teaches wherein the antenna is configured to operate in a frequency band having a millimeter wavelength. (Hwang Claim 4 the RF frequency comprises an impedance bandwidth ranging between 76 GHz˜81 GHz.)
Regarding Claim 7.
Hwang modified by Ojefors,Yang and Ndip teaches The semiconductor package of claim 1, Hwang further teaches wherein the antenna is configured in the first metal layer to provide direct air radiation. (Hwang antenna element #220 is exposed to the air in the package and connected to first metal layer)
Regarding Claim 8.
Hwang modified by Ojefors,Yang and Ndip teaches The semiconductor package of claim 1, Hwang does not explicitly disclose wherein the transmission line has a 50Ω impedance.
However, Hwang teaches a coplanar RF frequency with an impedance bandwidth ranging between 76 GHz˜81 GHz. It is routine and industry-standard for RF interconnects to be designed at ~ 50Ω system impedance to interface with front-end IC’s, test equipment and matching networks. These limitations would have been obvious to one of ordinary skill in the art at the time of the invention because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Regarding Claim 12.
Hwang modified by Ojefors,Yang and Ndip teaches The semiconductor package of claim 1, Hwang further teaches in an embodiment shown in Fig.7 further comprising:
a first dielectric layer (#200) covering the first metal layer (layer at the bottom of #520);
a third metal layer (layer at the bottom of #200) covering the first dielectric layer (#200); and
a first via (via within #200 layer) in the first dielectric layer, the first via coupling the first metal layer (layer at the top of #200) to the third metal layer (layer at the bottom of #200). (Hwang Fig.7 [0058-0072])
Regarding Claim 13.
Hwang modified by Ojefors,Yang and Ndip teaches The semiconductor package of claim 12, Hwang further teaches in Fig.7 further comprising:
a second dielectric layer (#540) covering the second metal layer (top metal layer of #520);
a fourth metal layer (layer at the top of #540, including #220/#222) covering the second dielectric layer (#540); and
a second via (via within #540) in the second dielectric layer, the second via coupling the second metal layer to the fourth metal layer. (Hwang Fig.7 [0058-0072])
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et.al. (US-2019/0305428-A1, hereinafter Hwang), in view of Ojefors et.al. (US 2022/0263223-A1, hereinafter Ojefors), further in view of Yang et. al. (US-2020/0059010-A1, hereinafter Yang) and Ndip et. al. (US-2018/0191053-A1, hereinafter Ndip), and further in view of Chen et. al. (US-20040212088, hereinafter Chen)
Regarding Claim 14.
Hwang modified by Ojefors, Yang and Ndip teaches The semiconductor package of claim 1,
Hwang modified by Ojefors, Yang and Ndip does not explicitly disclose further comprising:
a first solder mask layer above the first metal layer; and a second solder mask layer below the second metal layer.
However, Chen teaches in Fig.4E the first/top and second/bottom solder mask layers on respective metal layers and the patterning of mask openings. It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Hwang, Ojefors, Yang and Ndip with the teachings of Chen in order to achieve known packaging advantage with predictable results.
Claims 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hurwitz et. al. (US-2017/0213793-A1, hereinafter Hurwitz), in view of Hwang et.al. (US-2019/0305428-A1, hereinafter Hwang) and Ndip et. al. (US-2018/0191053-A1, hereinafter Ndip), and further in view of Yang et. al. (US-2020/0059010-A1, hereinafter Yang)
Regarding Claim 15.
Hurwitz teaches in Fig.1 and Fig. 6 an IC package comprising an embedded die structure including die #12 positioned in a socket/opening #72 of polymer frame #18 with packaging material #26 filling the space between die #12 and frame #18. Hurwitz further teaches feature layer #28 directly attached to terminal face #14 of die #12 and fanning out from terminal contacts #30 over frame #18, thereby teaching a first RDL structure above the die and electrically connected to a die contact. Hurwitz also teaches copper layer #36 and additional metal/routing layers on the opposite side of the die, thereby teaching or suggesting a second RDL/metal structure below the die.
Hurwitz therefore teaches
An integrated circuit (IC), comprising:
an embedded die structure, including:
an organic panel frame, including an opening,
a semiconductor die positioned within the opening;
a filling material that embeds the semiconductor die in the opening of the organic panel frame;
a first redistribution layer (RDL) structure positioned above the semiconductor die and having a conductive structure electrically connected to a contact on the semiconductor die;
Hurwitz does not explicitly disclose
an antenna formed in the first RDL structure and offset from the semiconductor die, the antenna having a slot bow-tie configuration; or
a second RDL structure as a ground reflector for the antenna.
However, Hwang teaches in Fig.7 an antenna-in-package structure including radiative antenna element #220, ground plan #211, functioning as a reflector, and RF/mm-wave signal feeding through transmission line #341 and via #432/#431. (See Hwang [0058-0065]) Ndip teaches in Fig.5a-5b an integrated antenna (#42) formed in a redistribution layer (#40), laterally offset from the chip (#38), connected to the chip by a line in the redistribution layer, and opposed by a reflector in a contacting layer (See Ndip [0013-0018]). Furthermore, Yang teaches in Fig.6 bowtie antenna geometry suitable for wideband and millimeter-wave antenna applications. (See Yang Fig.6 [0171-0181])
It would have been obvious to modify Hurwitz’s embedded-die fan-out package to include the RDL antenna and reflector arrangement taught by Hwang and Ndip, and to use the bowtie/slit antenna configuration suggested by Ndip and Yang, in order to provide a compact antenna-in-package structure, reduce chip-to-antenna interconnection distance, improve high-frequency signal integrity, reduce interference between the antenna and chip, and to provide predictable wideband/mm-wave antenna performance. Accordingly, Hurwitz in view of Hwang, Ndip, and Yang teaches or renders obvious the IC of claim 15.
Regarding Claim 16.
Hurwitz modified by Hwang, Ndip and Yang teaches The IC of claim 15,
Hwang also teaches in Fig.7 further comprising:
a transmission line (#341) formed in the first RDL structure, the transmission line coupling the semiconductor die (#40) to the antenna (#220). (Hwang Fig.7 RDL structure above die #40)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Hurwitz, Hwang, Ndip and Yang with the teachings of Hwang, as identified above, in order to simplify RF feed structure, reduce vertical transitions, reduces signal loss, and provide compact high-frequency antenna integration.
Regarding Claim 17.
Hurwitz modified by Hwang, Ndip and Yang teaches The IC of claim 15,
Hwang also teaches further comprising:
a waveguide in the first RDL structure, the waveguide having three parallel strips in the first RDL structure, and wherein the three parallel strips have a ground-signal-ground configuration. (Hwang Fig.7 ground/signal/ground parallel waveguide structures in #210)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Hurwitz, Hwang, Ndip and Yang with the teachings of Hwang, as identified above, in order to provide controlled impedance, shielding, reduced coupling, and reliable high-frequency signal transmission.
Regarding Claim 18.
Hurwitz modified by Hwang, Ndip and Yang teaches The IC of claim 15,
Hwang teaches a ground plane below the radiative antenna element and RF/mm-wave antenna operation. Ndip teaches a reflector arranged opposite the antenna and an antenna laterally offset from the chip, and further teaches antenna radiation out of the package layer. Yang teaches bowtie antennas suitable for millimeter-wave/high-frequency operation.
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Hurwitz, Hwang, Ndip and Yang with the teachings of Hwang, Ndip and Yang, therefore extending the second RDL/reflector structure below both the antenna and semiconductor die, in order to provide improved reflection, shielding, return-current continuity, and package grounding, and to configure the antenna for millimeter-wavelength direct-air radiation. Therefore, claim 18 is obvious over Hurwitz in view of Hwang, Ndip, and Yang.
Regarding Claim 20.
Hwang modified by Yang and Ndip teaches The IC of claim 15,
Hwang also teaches in Fig.7 further comprising:
a first dielectric layer (#520) covering the first RDL structure (layer below #520);
a third RDL structure (layer above #520)) covering the first dielectric layer;
a first via (#432) in the first dielectric layer (#520), the first via coupling the first RDL (top part of #210) structure to the third RDL structure (#540);
a second dielectric layer (#520) covering the second RDL structure (layer below #40, including #214);
a fourth RDL structure (layer including #224) covering the second RDL structure; and
a second via (via within #520) in the second dielectric layer (#520), the second via coupling the second RDL structure to the fourth RDL structure. (Hwang Fig.7 [0058-0060])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Hurwitz, Hwang, Ndip and Yang with the teachings of Hwang, as identified above, in order to provide additional routing, shielding, interconnection density, and package design flexibility in a fan-out/embedded-die semiconductor package.
Allowable Subject Matter
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19 rejected. Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AlA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 9 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein …an impedance transformer formed in the first metal layer, wherein the impedance transformer is coupled between an antenna feed and the transmission line. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 10 contain allowable subject matter because they depend from claim 9 .
Claim 11 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein the antenna comprises a metal plane having two triangular openings, the openings each having a vertex positioned near an antenna feed and a base side opposite the vertex, and wherein the distance between the base sides determines a resonant frequency of the antenna. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 19 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein … an impedance transformer formed in the first RDL structure, wherein the impedance transformer is coupled between an antenna feed and the transmission line. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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