DETAILED ACTION
Claims 1, 3-9, and 16 are pending.
Claim 3 has been withdrawn. This claim has only been partially examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 14, 2025, has been entered.
Specification
In the title, the examiner recommends inserting --(SIMR)-- after “REQUEST”. This has basis in paragraph [0007] and also helps to distinguish from SIMD/SIMT.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
The replacement FIGs submitted on July 14, 2025, are blurry/pixelated. This is not an objection, but the examiner recommends improving quality, including removing all blur, and using only true black and white, to improve print quality.
Replacement FIG.11 submitted on July 14, 2025, are objected to because of the following minor informalities:
Replace both instances of “Memcahched” with --Memcached--.
A corrected drawing sheet in compliance with 37 CFR 1.121(d) is required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 3, line 3, both instances of “the requests” since this could refer to the plurality in claim 1, line 7, or to those of the plurality that are grouped in a batch (claim 1, line 8). The examiner recommends inserting --portion of the-- before both of the aforementioned instances of “requests”.
In claim 4, the last instance of “the requests” for similar reasoning.
In claim 16, last line, “the CPU”. In line 2, applicant isn’t claiming a CPU, but a CPU core. Please insert --core-- before the period.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Agrawal et al., “Massively Parallel Server Processors” (as cited by applicant), in view of Kumar et al., U.S. Patent Application Publication No. 2013/0074090, Deneau, U.S. Patent No. 6,684,305, Gutierrez et al., U.S. Patent Application Publication No. 2020/0089528, and Cloutier, “SYSCALL - Fast System Call”.
Referring to claim 1, Agrawal has taught a system, comprising:
a central processing unit (CPU) (see FIG.1, one or more conventional cores); and
a request processing unit (RPU) (see FIG.1, one or more SIMT cores) having an Out-of-Order (see FIG.1, Out-of-Order (OoO) Select) Single Instruction Multiple Thread (SIMT) execution model (see FIG.1, SIMT core(s) and SIMT lanes), wherein the CPU is configured to:
receive a plurality of requests (see the abstract and p.76, first full paragraph. The scheduler, which is in the CPU, receives requests);
group a portion of the requests in a batch (see the abstract and p.76, first full paragraph. The scheduler examines the requests and bundles/groups similar requests into a group/batch); and
cause the RPU to execute instructions corresponding to each request in the batch (see p.76, first full paragraph, and note that the scheduler dispatches the grouped requests to the RPU’s SIMT circuitry for execution), and wherein the RPU is configured to:
execute, with a plurality of threads, the instructions corresponding to the batch of requests in lockstep (see p.75, third to last paragraph),
Agrawal has not taught the CPU having a Simultaneous Multi-Threading (SMT) thread/execution model. That is, Agrawal has not taught the architecture of the conventional cores of FIG.1. However, Kumar has taught a server processing server workloads with an SMT architecture (see the abstract and FIG.2 and the description thereof). SMT improves overall efficiency by allowing multiple independent threads (assigned to different workloads) to better utilize resources by executing in parallel. This could speed up processing of multiple tasks in the CPU that are not offloaded to the SIMT logic. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agrawal’s CPU to have a Simultaneous Multi-Threading (SMT) thread/execution model.
Agrawal has also not explicitly taught wherein the CPU and the RPU are configured to execute instructions of a same instruction set architecture. However, there are only two options - (1) the RPU having the same ISA as the CPU, and (2) the RPU having a different ISA than the CPU. Deneau has taught that a processor and its coprocessor can use the same or different ISAs (see column 6, lines 17-28). One of ordinary skill in the art would have recognized that implementing the same ISA on both the RPU and CPU would simplify execution because there would be no need for extra translation logic to translate between instruction sets. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agrawal such that the CPU and the RPU are configured to execute instructions of a same instruction set architecture.
Agrawal has also not taught that the RPU is configured to execute system calls under the same instruction set architecture as the CPU. Instead, per the first full paragraph on p.76, the conventional cores (CPU, not RPU) are responsible for handling system calls. However, Gutierrez has taught that a co-processor may execute an operating system (OS) microkernel so that it can execute system calls (see paragraph [0064]). A system call, as is known, is a call to an operating system to perform a privileged function that is not directly accessible by the user. Per Cloutier, a system call can be simply executed with minimal software, i.e., a single SYSCALL instruction of an ISA. One of ordinary skill in the art would have recognized that if a number of server requests involve system calls, then those, too, could benefit from being grouped together for efficient SIMT processing in Agrawal. As a result, in order to more efficiently perform multiple similar system calls with minimal software, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agrawal’s co-processor (RPU) to include a micro-OS so that it can execute system calls to the micro-OS using a SYSCALL instruction (an instruction that would be in the ISA of both the conventional cores and SIMT cores of Agrawal). The combination would include the CPU detecting multiple system call requests (e.g. multiple SYSCALL instructions), grouping them together, and offloading them to the RPU so that the grouped requests can be executed efficiently by the SIMT lanes.
Referring to claim 4, Agrawal, as modified, has taught the system of claim 1, wherein to group the portion of the requests in the batch, the CPU is further configured to: group the portion of the requests based on the number of arguments in the requests, respectively (see section 1, paragraph 1 and the paragraph starting at the bottom of the left column on p.75. If there are multiple repeated tasks with similar parameters, the tasks may be grouped).
Referring to claim 5, Agrawal, as modified, has taught the system of claim 1, wherein the plurality of requests are received at a data center over a communications network (see the abstract and section 1, first two paragraphs. Basically, the requests are web requests to a web server, which would receive the requests over a communications network (e.g. the Internet)).
Referring to claim 6, Agrawal, as modified, has taught the system of claim 1, wherein the plurality of requests are received according to a communications protocol (all communications occur according to some protocol. For web requests, HTTP is used as an example).
Referring to claim 7, Agrawal, as modified, has taught the system of claim 6, wherein the communications protocol is Hypertext Transfer Protocol (HTTP) (again, web requests to a web server are made according to HTTP) or Remote Procedure Call (RPC).
Referring to claim 8, Agrawal, as modified, has taught the system of claim 1, wherein the CPU is further configured to: assign a warp of threads to the portion of the requests in the batch, wherein each thread of the warp corresponds to a request (as is known in SIMT, a group of threads corresponding to respective requests is called a warp. Thus, by grouping/bundling the similar requests, the CPU is assigning a warp to these requests for parallel execution on the SIMT circuitry).
Referring to claim 9, Agrawal, as modified, has taught the system of claim 7, wherein the CPU is further configured to: coalesce stack segments of the threads in physical address space to minimize memory divergence (see section 4, particularly the last paragraph, where the thread stacks are interleaved (coalesced) to coordinate accesses thereto to minimize divergence).
Claim 16 is rejected for similar reasoning as claim 1.
Response to Arguments
On page 7 of applicant’s response, applicant again argues the title objection.
The argument is persuasive and the objection is withdrawn.
On pages 9-10 of the response, applicant argues that Agrawal is silent regarding the CPU cores and SIMT cores sharing an instruction set.
After further consideration, the examiner agrees that there is no explicit teaching of using the same ISA. However, this is deemed obvious as set forth in the rejection above.
On page 10 of applicant’s response, applicant argues that Agrawal does not implement the same ISA as a CPU because the CPU can implement system calls while the GPUs cannot.
The examiner is not sure “cannot” is correct. It may simply be an implementation choice by Agrawal to have the CPU handle the system calls. However, based on the newly discovered prior art, the examiner asserts it would have been obvious to modify Agrawal to allow SYSCALLs to be grouped and offloaded for SIMT processing similar to how other requests are grouped and offloaded. That is, if multiple similar requests are sent to the server that call the OS to action, then one of ordinary skill in the art would realize that efficient processing of these calls could be improved by performing them in parallel in the SIMT logic.
On pages 10-11, the arguments related to Jones are moot since Jones is no longer used in the rejection due to applicant’s amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights