DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHANG (US 20160190013).
Regarding claim 1, CHANG discloses an integrated circuit structure, comprising:
a first fin (the back fin 112 in fig 3A which is the top fin 112 in fig 3B, see fig 3, para 23);
a first gate trench over the first fin (the trench T1 which contains the gate G1 over the back fin 112, see fig 2 and 3, para 43), the first gate trench having a first width (the trench T1 has a width W1, see fig 2 and 3, para 43-44);
a second fin (the middle fin 112 in fig 3A which is the middle fin 112 in fig 3B, see fig 3, para 23);
a second gate trench over the second fin (the trench T2 which contains the gate G2 over the middle fin 112, see fig 2 and 3, para 43), the second gate trench having a second width greater than the first width (the trench T2 has a width W2 which is greater than W1, see fig 2 and 3, para 43-44); and
a gate electrode layer (gate layers 180 and 190 are part of the gate electrode, see fig 2 and 3, para 50) having a first portion along a bottom and partially along sidewalls of the first trench (a portion of 180 and 190 extends along the bottom and sidewalls of the trench T1, see fig 2G and 3, para 50), and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench (a second portion of 180 and 190 extends along the bottom and sidewalls of the trench T2, see fig 2G and 3, para 50), wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench (the bottom and top surfaces of 180 and 190 are level in T1 and T2, so the extents are the same, see fig 3A).
Regarding claim 2, CHANG discloses the integrated circuit structure of claim 1, wherein a differential between a height of a top of the first portion of the gate electrode layer from a top of the first fin and a height of a top of the second portion of the gate electrode layer from a top of the second fin is less than 10% of the height of the top of the first portion of the gate electrode layer from the top of the first fin (there is no difference between the differentials because the top surfaces of the fins and the gate electrodes are at the same level in both trenches, see fig 2G and 3).
Regarding claim 3, CHANG discloses the integrated circuit structure of claim 1, wherein the second width is twice the first width (W1 can be 50 nm and W2 can be 100 nm, which would be a ratio of 2, see fig 2-3, para 44).
Regarding claim 4, CHANG discloses the integrated circuit structure of claim 1, wherein the gate electrode layer is a work function gate electrode layer (190 can be a work function metal layer, see fig 2 and 3, para 52).
Regarding claim 5, CHANG discloses the integrated circuit structure of claim 4, wherein the gate electrode layer comprises a metal material and a dipole material (190 can be a metal, see para 51, and 180 can include Al2O3 which is a dipole layer, see para 47)
Claim(s) 6-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by YEH (US 20230282699).
Regarding claim 6, YEH discloses an integrated circuit structure, comprising:
a first stack of nanowires (the stack 110T-4, see fig 12, para 36);
a first gate trench (gate trench G4, see fig 12, para 35) over the first stack of nanowires, the first gate trench having a first width (the width W4 of G4, see fig 7 and 12, para 35);
a second stack of nanowires (the stack 110T-5, see fig 7 and 12, para 36);
a second gate trench (gate trench G5, see fig 7 and 12, para 36) over the second stack of nanowires, the second gate trench having a second width greater than the first width (G5 has width W5 which can be 100 nm whereas the width W4 of G4 can be 50 nm, see fig 7 and 12, para 35); and
a gate electrode layer (gate layer 136 and 138, see fig 10 and 12, para 32) having a first portion along a bottom and partially along sidewalls of the first trench (the portion of 136 and 138 along the bottom and side surfaces of G4, see fig 10 and 12, para 32), and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench (the portions of 136 and 138 along the bottom and side surfaces of G5, see fig 10 and 12, para 32), wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench (the extend is the same since the top surfaces 139Bt and 139Ct are level, see fig 10 and 12, para 43).
Regarding claim 7, YEH discloses the integrated circuit structure of claim 6, wherein a differential between a height of a top of the first portion of the gate electrode layer from a top of the first stack of nanowires and a height of a top of the second portion of the gate electrode layer from a top of the second stack of nanowires is less than 10% of the height of the top of the first portion of the gate electrode layer from the top of the first stack of nanowires (there is no difference between the differentials because the top surfaces of the fins and the gate electrodes are at the same level in both trenches, see fig 10 and 12).
Regarding claim 8, YEH discloses the integrated circuit structure of claim 6, wherein the second width is twice the first width (G5 has width W5 which can be 100 nm whereas the width W4 of G4 can be 50 nm, see fig 7 and 12, para 35).
Regarding claim 9, YEH discloses the integrated circuit structure of claim 6, wherein the gate electrode layer is a work function gate electrode layer (138 can be Ti which can be a work function material, see fig 12, para 32).
Regarding claim 10, YEH discloses the integrated circuit structure of claim 9, wherein the gate electrode layer comprises a metal material (138 can be Ti, see fig 12, para 32) and a dipole material (138 can be Al2O3 which is a dimple material, see fig 12, para 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY 14 (US 20140008700) in view of CHANG (US 20160190013).
Regarding claim 11, RACHMADY 14 discloses a computing device, comprising:
a board (board 802, see fig 8, para 71); and
a component (the processor 804, see fig 8, para 74) coupled to the board,
the component including an integrated circuit structure (804 can include a finFET device such as the one in fig 4A, see fig 8 and 4, para 74).
RACHMADY 14 fails to explicitly disclose a device wherein the component including an integrated circuit structure,
comprising:
a first fin;
a first gate trench over the first fin, the first gate trench having a first width;
a second fin;
a second gate trench over the second fin, the second gate trench having a second width greater than the first width; and
a gate electrode layer having a first portion along a bottom and partially along sidewalls of the first trench, and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.
CHANG teaches a device wherein the component including an integrated circuit structure (the structure of the FET device in fig 3, see para 56),
comprising:
a first fin (the back fin 112 in fig 3A which is the top fin 112 in fig 3B, see fig 3, para 23);
a first gate trench over the first fin (the trench T1 which contains the gate G1 over the back fin 112, see fig 2 and 3, para 43), the first gate trench having a first width (the trench T1 has a width W1, see fig 2 and 3, para 43-44);
a second fin (the middle fin 112 in fig 3A which is the middle fin 112 in fig 3B, see fig 3, para 23);
a second gate trench over the second fin (the trench T2 which contains the gate G2 over the middle fin 112, see fig 2 and 3, para 43), the second gate trench having a second width greater than the first width (the trench T2 has a width W2 which is greater than W1, see fig 2 and 3, para 43-44); and
a gate electrode layer (gate layers 180 and 190 are part of the gate electrode, see fig 2 and 3, para 50) having a first portion along a bottom and partially along sidewalls of the first trench (a portion of 180 and 190 extends along the bottom and sidewalls of the trench T1, see fig 2G and 3, para 50), and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench (a second portion of 180 and 190 extends along the bottom and sidewalls of the trench T2, see fig 2G and 3, para 50), wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench (the bottom and top surfaces of 180 and 190 are level in T1 and T2, so the extents are the same, see fig 3A).
RACHMADY 14 and CHANG are analogous art because they both are directed towards finFET semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of RACHMADY with the finFET structure of CHANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of RACHMADY with the finFET structure of CHANG in order to improve the yield (see CHANG para 75).
Regarding claim 12, RACHMADY 14 and CHANG disclose the computing device of claim 11.
RACHMADY 14 further discloses a device, further comprising: a memory coupled to the board (a memory can be coupled to board 802, see fig 8, para 72).
Regarding claim 13, RACHMADY 14 and CHANG disclose the computing device of claim 11.
RACHMADY 14 further discloses a device, further comprising: a communication chip coupled to the board (communication chip 806 can be coupled to 802, see fig 8, para 73).
Regarding claim 14, RACHMADY 14 and CHANG disclose the computing device of claim 11.
RACHMADY 14 further discloses a device, wherein the component is a packaged integrated circuit die (the processor 804 can be a packaged integrated circuit, see fig 8, para 74).
Regarding claim 15, RACHMADY 14 and CHANG disclose the computing device of claim 11.
RACHMADY 14 further discloses a device, wherein the component is selected from the group consisting of a processor (804 can be a processor, see fig 8, para 71), a communications chip, and a digital signal processor.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY 13 (US 20130341704) in view of YEH (US 20230282699).
Regarding claim 16, RACHMADY 13 discloses a computing device, comprising:
a board (the board 602, see fig 6, para 76); and
a component coupled to the board (the processor 604, see fig 6, para 77),
the component including an integrated circuit structure (the processor 604 can have an integrated circuit comprising a gate all around transistor as in fig 1, see fig 6, para 77).
RACHMADY 13 fails to explicitly disclose a device wherein the component including an integrated circuit structure,
comprising:
a first stack of nanowires;
a first gate trench over the first stack of nanowires, the first gate trench having a first width;
a second stack of nanowires;
a second gate trench over the second stack of nanowires, the second gate trench having a second width greater than the first width; and
a gate electrode layer having a first portion along a bottom and partially along sidewalls of the first trench, and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.
YEH teaches a device wherein the component including an integrated circuit structure (the structure of fig 12, see para 47),
comprising:
a first stack of nanowires (the stack 110T-4, see fig 12, para 36);
a first gate trench (gate trench G4, see fig 12, para 35) over the first stack of nanowires, the first gate trench having a first width (the width W4 of G4, see fig 7 and 12, para 35);
a second stack of nanowires (the stack 110T-5, see fig 7 and 12, para 36);
a second gate trench (gate trench G5, see fig 7 and 12, para 36) over the second stack of nanowires, the second gate trench having a second width greater than the first width (G5 has width W5 which can be 100 nm whereas the width W4 of G4 can be 50 nm, see fig 7 and 12, para 35); and
a gate electrode layer (gate layer 136 and 138, see fig 10 and 12, para 32) having a first portion along a bottom and partially along sidewalls of the first trench (the portion of 136 and 138 along the bottom and side surfaces of G4, see fig 10 and 12, para 32), and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench (the portions of 136 and 138 along the bottom and side surfaces of G5, see fig 10 and 12, para 32), wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.
RACHMADY 13 and YEH are analogous art because they both are directed towards nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of RACHMADY 13 with the nanowire FET structure of YEH because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of RACHMADY 13 with the nanowire FET structure of YEH in order to improve electrical performance (see YEH para 57).
Regarding claim 17, RACHMADY 13 and YEH disclose the computing device of claim 16.
RACHMADY 13 further discloses a device, further comprising: a memory (a memory can be coupled to 602, see fig 6, para 75) coupled to the board.
Regarding claim 18, RACHMADY 13 and YEH disclose the computing device of claim 16.
RACHMADY 13 further discloses a device, further comprising: a communication chip coupled to the board (communication chip 606 can be coupled to the board 602, see fig 6, para 76).
Regarding claim 19, RACHMADY 13 and YEH disclose the computing device of claim 16.
RACHMADY 13 further discloses a device, wherein the component is a packaged integrated circuit die (604 can be a packaged IC device, see fig 6, para 77).
Regarding claim 20, RACHMADY 13 and YEH disclose the computing device of claim 16.
RACHMADY 13 further discloses a device, wherein the component is selected from the group consisting of a processor (604 can be a processor, see fig 6, para 77), a communications chip, and a digital signal processor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811