DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHANG (US 20160190013).
Regarding claim 1, CHANG discloses an integrated circuit structure, comprising:
a first fin (the back fin 112 in fig 6A which is the top fin 112 in fig 6B, see fig 6, 4G-1 and 4G-2, para 23);
a first gate trench (the trench T1 which contains gate G1 in fig 4G and 6, see fig 78-79, para 43) over the first fin, the first gate trench having a first width (the width of G1, see fig 4G and 6, para 43-44);
a second fin (the middle fin 112 in fig 6A which is the middle fin 112 in fig 6B, see fig 6 and 4G, para 23);
a second gate trench over the second fin (the trench T2 which contains the gate G2 over the middle fin 112, see fig 4G and 6, para 43), the second gate trench having a second width greater than the first width (the trench T2 has a width W2 which is greater than W1, see fig 2-3, 4G and 6, para 43-44); and
a gate electrode layer (the layer comprising 180 and 190 is part of the gates G1 and G2, see fig 4G and 6, para 50) having a first portion (the portion of 190 that is part of G1, see fig 4G and 6, para 50) along a bottom and only partially along sidewalls of the first trench (190 extends along the bottom of trench T1, and also only partially up the sidewalls, see fig 4G-1 and 6) such that the first portion has an uppermost surface below an uppermost surface of the first trench (the uppermost surface of 190 in G1 is lower that the uppermost surface of 170 that surrounds the trench T1, see fig 4G-1 and 6), and the gate electrode layer having a second portion (the portion of 190 that is part of the gate G2, see fig 4G and 6, para 50) along a bottom and only partially along sidewalls of the second trench (190 extends along the bottom of trench T2, and also only partially up the sidewalls, see fig 4G-1 and 6) such that the second portion has an uppermost surface below an uppermost surface of the second trench (the uppermost surface of 190 in G2 is lower that the uppermost surface of 170 that surrounds the trench T2, see fig 4G-1 and 6), wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench (the top surface of 190 in G1 and G2 are approximately level, see fig 4G-1).
Regarding claim 2, CHANG discloses the integrated circuit structure of claim 1, wherein a differential between a height of a top of the first portion of the gate electrode layer from a top of the first fin and a height of a top of the second portion of the gate electrode layer from a top of the second fin is less than 10% of the height of the top of the first portion of the gate electrode layer from the top of the first fin (the height of the fin 112 under both gates G1 and G2 is the same, see fig 4G-1, and the heights of the two portions of 190 in G1 and G2 are level, see fig 4G-1, so the difference will be zero, see fig 4G-1).
Regarding claim 3, CHANG discloses the integrated circuit structure of claim 1, wherein the second width is twice the first width (W1 can be 50 nm and W2 can be 100 nm, which would be a ratio of 2, see fig 4 and 6, para 44).
Regarding claim 4, CHANG discloses the integrated circuit structure of claim 1, wherein the gate electrode layer is a workfunction gate electrode layer (190 can be a work function metal layer, see fig 2 and 3, para 52).
Regarding claim 5, CHANG discloses the integrated circuit structure of claim 4, wherein the gate electrode layer comprises a metal material and a dipole material (190 can be a metal, see para 51, and 180 can include Al2O3 which is a dipole layer, see para 47)
Claim(s) 6-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by YEH (US 20230282699).
Regarding claim 6, YEH discloses an integrated circuit structure, comprising:
a first stack of nanowires (the stack 110T-4, see fig 12, para 36);
a first gate trench (gate trench G4 in insulator 132 which contains the gate 136 and 138, see fig 12, para 35) over the first stack of nanowires, the first gate trench having a first width (the width W4 of G4, see fig 7 and 12, para 35);
a second stack of nanowires (the stack 110T-5, see fig 7 and 12, para 36);
a second gate trench (gate trench G5 which contains the gate 136 and 138, see fig 7 and 12, para 36) over the second stack of nanowires, the second gate trench having a second width greater than the first width (G5 has width W5 which can be 100 nm whereas the width W4 of G4 can be 50 nm, see fig 7 and 12, para 35); and
a gate electrode layer (gate layer 136 and 138, see fig 10 and 12, para 32) having a first portion along a bottom and only partially along sidewalls of the first trench (the portion of136 and 138 in G4 extend to the bottom of the trench G4 and does not extend to the top of 132, see fig 12) such that the first portion has an uppermost surface below an uppermost surface of the first trench (the uppermost surface of 136 and 138 are below the topmost surface of 132 on either side of the trench, see fig 12), and the gate electrode layer having a second portion along a bottom and only partially along sidewalls of the second trench (the portion of136 and 138 in G5 extend to the bottom of the trench G5 and does not extend to the top of 132, see fig 12) such that the second portion has an uppermost surface below an uppermost surface of the second trench (the uppermost surface of 136 and 138 are below the topmost surface of 132 on either side of the trench, see fig 12), wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench (the top surface of 136 and 138 in G4 and G5 are level, see fig 12).
Regarding claim 7, YEH discloses the integrated circuit structure of claim 6, wherein a differential between a height of a top of the first portion of the gate electrode layer from a top of the first stack of nanowires and a height of a top of the second portion of the gate electrode layer from a top of the second stack of nanowires is less than 10% of the height of the top of the first portion of the gate electrode layer from the top of the first stack of nanowires (there is no difference between the differentials because the top surfaces of the nanowires 110T-4 and 110T-5 and the gate layers 136 and 138 are at the same level in both trenches, see fig 10 and 12).
Regarding claim 8, YEH discloses the integrated circuit structure of claim 6, wherein the second width is twice the first width (G5 has width W5 which can be 100 nm whereas the width W4 of G4 can be 50 nm, see fig 7 and 12, para 35).
Regarding claim 9, YEH discloses the integrated circuit structure of claim 6, wherein the gate electrode layer is a workfunction gate electrode layer (138 can be Ti which can be a work function material, see fig 12, para 32).
Regarding claim 10, YEH discloses the integrated circuit structure of claim 9, wherein the gate electrode layer comprises a metal material (138 can be Ti, see fig 12, para 32) and a dipole material (138 can be Al2O3 which is a dipole material, see fig 12, para 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY 14 (US 20140008700) in view of CHANG (US 20160190013).
Regarding claim 11, RACHMADY 14 discloses a computing device, comprising:
a board (board 802, see fig 8, para 71); and
a component (the processor 804, see fig 8, para 74) coupled to the board,
the component including an integrated circuit structure (804 can include a finFET device such as the one in fig 4A, see fig 8 and 4, para 74).
RACHMADY 14 fails to explicitly disclose a device wherein the component including an integrated circuit structure,
comprising:
a first fin;
a first gate trench over the first fin, the first gate trench having a first width;
a second fin;
a second gate trench over the second fin, the second gate trench having a second width greater than the first width; and
a gate electrode layer having a first portion along a bottom and only partially along sidewalls of the first trench such that the first portion has an uppermost surface below an uppermost surface of the first trench, and the gate electrode layer having a second portion along a bottom and only partially along sidewalls of the second trench such that the second portion has an uppermost surface below an uppermost surface of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.
CHANG teaches a device wherein the component including an integrated circuit structure (the integrated circuit device shown in fig 4G and 6, para 79),
comprising:
a first fin (the back fin 112 in fig 6A which is the top fin 112 in fig 6B, see fig 6, 4G-1 and 4G-2, para 23);
a first gate trench (the trench T1 which contains gate G1 in fig 4G and 6, see fig 78-79, para 43) over the first fin, the first gate trench having a first width (the width of G1, see fig 4G and 6, para 43-44);
a second fin (the middle fin 112 in fig 6A which is the middle fin 112 in fig 6B, see fig 6 and 4G, para 23);
a second gate trench over the second fin (the trench T2 which contains the gate G2 over the middle fin 112, see fig 4G and 6, para 43), the second gate trench having a second width greater than the first width (the trench T2 has a width W2 which is greater than W1, see fig 2-3, 4G and 6, para 43-44); and
a gate electrode layer (the layer comprising 180 and 190 is part of the gates G1 and G2, see fig 4G and 6, para 50) having a first portion (the portion of 190 that is part of G1, see fig 4G and 6, para 50) along a bottom and only partially along sidewalls of the first trench (190 extends along the bottom of trench T1, and also only partially up the sidewalls, see fig 4G-1 and 6) such that the first portion has an uppermost surface below an uppermost surface of the first trench (the uppermost surface of 190 in G1 is lower that the uppermost surface of 170 that surrounds the trench T1, see fig 4G-1 and 6), and the gate electrode layer having a second portion (the portion of 190 that is part of the gate G2, see fig 4G and 6, para 50) along a bottom and only partially along sidewalls of the second trench (190 extends along the bottom of trench T2, and also only partially up the sidewalls, see fig 4G-1 and 6) such that the second portion has an uppermost surface below an uppermost surface of the second trench (the uppermost surface of 190 in G2 is lower that the uppermost surface of 170 that surrounds the trench T2, see fig 4G-1 and 6), wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench (the top surface of 190 in G1 and G2 are approximately level, see fig 4G-1).
RACHMADY 14 and CHANG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of RACHMADY 14 with the finFET configuration of CHANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of RACHMADY 14 with the finFET configuration of CHANG in order to improve the yield (see CHANG para 75).
Regarding claim 12, RACHMADY 14 and CHANG disclose the computing device of claim 11.
RACHMADY 14 further discloses a device, further comprising: a memory coupled to the board (a memory can be coupled to board 802, see fig 8, para 72).
Regarding claim 13, RACHMADY 14 and CHANG disclose the computing device of claim 11.
RACHMADY 14 further discloses a device, further comprising: a communication chip coupled to the board (communication chip 806 can be coupled to 802, see fig 8, para 73).
Regarding claim 14, RACHMADY 14 and CHANG disclose the computing device of claim 11.
RACHMADY 14 further discloses a device, wherein the component is a packaged integrated circuit die (the processor 804 can be a packaged integrated circuit, see fig 8, para 74).
Regarding claim 15, RACHMADY 14 and CHANG disclose the computing device of claim 11.
RACHMADY 14 further discloses a device, wherein the component is selected from the group consisting of a processor (804 can be a processor, see fig 8, para 71), a communications chip, and a digital signal processor.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY 13 (US 20130341704) in view of YEH (US 20230282699).
Regarding claim 16, RACHMADY 13discloses a computing device, comprising:
a board (the board 602, see fig 6, para 76); and
a component coupled to the board (the processor 604, see fig 6, para 77),
the component including an integrated circuit structure (the processor 604 can have an integrated circuit comprising a gate all around transistor as in fig 1, see fig 6, para 77).
RACHMADY 13 fails to explicitly disclose a device wherein the component including an integrated circuit structure,
comprising:
a first stack of nanowires;
a first gate trench over the first stack of nanowires, the first gate trench having a first width;
a second stack of nanowires;
a second gate trench over the second stack of nanowires, the second gate trench having a second width greater than the first width; and
a gate electrode layer having a first portion along a bottom and only partially along sidewalls of the first trench such that the first portion has an uppermost surface below an uppermost surface of the first trench, and the gate electrode layer having a second portion along a bottom and only partially along sidewalls of the second trench such that the second portion has an uppermost surface below an uppermost surface of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.
YEH teaches a device wherein the component including an integrated circuit structure (the structure of fig 12, see para 47),
comprising:
a first stack of nanowires (the stack 110T-4, see fig 12, para 36);
a first gate trench (gate trench G4 in insulator 132 which contains the gate 136 and 138, see fig 12, para 35) over the first stack of nanowires, the first gate trench having a first width (the width W4 of G4, see fig 7 and 12, para 35);
a second stack of nanowires (the stack 110T-5, see fig 7 and 12, para 36);
a second gate trench (gate trench G5 which contains the gate 136 and 138, see fig 7 and 12, para 36) over the second stack of nanowires, the second gate trench having a second width greater than the first width (G5 has width W5 which can be 100 nm whereas the width W4 of G4 can be 50 nm, see fig 7 and 12, para 35); and
a gate electrode layer (gate layer 136 and 138, see fig 10 and 12, para 32) having a first portion along a bottom and only partially along sidewalls of the first trench (the portion of136 and 138 in G4 extend to the bottom of the trench G4 and does not extend to the top of 132, see fig 12) such that the first portion has an uppermost surface below an uppermost surface of the first trench (the uppermost surface of 136 and 138 are below the topmost surface of 132 on either side of the trench, see fig 12), and the gate electrode layer having a second portion along a bottom and only partially along sidewalls of the second trench (the portion of136 and 138 in G5 extend to the bottom of the trench G5 and does not extend to the top of 132, see fig 12) such that the second portion has an uppermost surface below an uppermost surface of the second trench (the uppermost surface of 136 and 138 are below the topmost surface of 132 on either side of the trench, see fig 12), wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench (the top surface of 136 and 138 in G4 and G5 are level, see fig 12).
RACHMADY 13 and YEH are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of RACHMADY 13 with the nanowire device configuration of YEH because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of RACHMADY 13 with the nanowire device configuration of YEH in order to improve electrical performance (see YEH para 57).
Regarding claim 17, RACHMADY 13 and YEH disclose the computing device of claim 16.
RACHMADY 13 further discloses a device, further comprising: a memory (a memory can be coupled to 602, see fig 6, para 75) coupled to the board.
Regarding claim 18, RACHMADY 13 and YEH disclose the computing device of claim 16.
RACHMADY 13 further discloses a device, further comprising: a communication chip coupled to the board (communication chip 606 can be coupled to the board 602, see fig 6, para 76).
Regarding claim 19, RACHMADY 13 and YEH disclose the computing device of claim 16.
RACHMADY 13 further discloses a device, wherein the component is a packaged integrated circuit die (604 can be a packaged IC device, see fig 6, para 77).
Regarding claim 20, RACHMADY 13 and YEH disclose the computing device of claim 16.
RACHMADY 13 further discloses a device, wherein the component is selected from the group consisting of a processor (604 can be a processor, see fig 6, para 77), a communications chip, and a digital signal processor.
Response to Arguments
Applicant's arguments filed 4/8/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 11, the applicant argues that the cited prior art does not fully disclose the claimed inventions because CHANG does not disclose a device comprising “a gate electrode layer having a first portion along a bottom and only partially along sidewalls of the first trench such that the first portion has an uppermost surface below an uppermost surface of the first trench, and the gate electrode layer having a second portion along a bottom and only partially along sidewalls of the second trench such that the second portion has an uppermost surface below an uppermost surface of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench” since the device of figure 3 of CHANG has gate electrode layers 180 and 190 that extend along entire and not partial sidewalls of the gate trenches and reach the same level as the top surface of the insulating layer 17 on either side of the trench (see CHANG fig 3A). This may be true, but CHANG also discloses, in figure 6, a device wherein the gate electrode layers 180 and 190 only extend partially up the sides of the gate trench, and whose top surfaces are below the level of the top surface of the insulating layer 170 surrounding the trench (see CHANG fig 6A). For this reason, and those given in the rejection above, the applicants arguments regarding CHANG and claims 1 and 11 are not persuasive.
Regarding claims 6 and 16, the applicant argues that the cited prior art does not fully disclose the claimed inventions because CHANG does not disclose a device comprising “a gate electrode layer having a first portion along a bottom and only partially along sidewalls of the first trench such that the first portion has an uppermost surface below an uppermost surface of the first trench, and the gate electrode layer having a second portion along a bottom and only partially along sidewalls of the second trench such that the second portion has an uppermost surface below an uppermost surface of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench” since the device of figure 3 of CHANG has gate electrode layers 180 and 190 that extend along entire and not partial sidewalls of the gate trenches and reach the same level as the top surface of the insulating layer 17 on either side of the trench (see CHANG fig 3A). This argument is not persuasive, since CHANG was not relied upon in the rejection of those claims. YEH et al (US 20230282699) was used instead. The applicant presents no arguments with respect to the applicability of YEH. For at least these reasons, and those given in the rejection above, the applicants arguments regarding claims 6 and 16 are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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