DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8, 11 and 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. US 2023/0345691 A1.
Regarding claims 1-3, Xie discloses:
An integrated circuit structure (Figs. 9C and 11C as supported by Figs. 1-9 and 11), comprising:
a plurality of gate lines (510, 520, 530, 540) extending over a plurality of semiconductor nanowire stack channel structures (para 0032; 210, 220, 310, 320, 410, 420, nanosheets transistors);
a plurality of trench contacts (610, 620) extending over a plurality of source or drain structures (211, 311), wherein a first one of the plurality of trench contacts has a recess therein (610 recessed inside 211 and 311);
a backside metal routing layer (930) extending beneath the plurality of gate lines and beneath the plurality of trench contacts; and
a conductive structure coupling the backside metal routing layer to a second one of the plurality of trench contacts (620), the conductive structure comprising a pillar portion (752) in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion (862/871), the line portion in contact with and extending along the backside metal routing layer (862/871 extending along 930).
(claim 2) a backside power delivery line (para 0047; 930 backside power distribution network (BSPDN).
(claim 3) a recessed deep boundary via structure (752).
Regarding claims 6-8, Xie discloses:
An integrated circuit structure (Figs. 9C and 11C as supported by Figs. 1-9 and 11), comprising:
a plurality of gate lines (510, 520, 530, 540) extending over a plurality of semiconductor fin structures (para 0032; 210, 220, 310, 320, 410, 420, fin-type transistors);
a plurality of trench contacts (610, 620) extending over a plurality of source or drain structures (211, 311), wherein a first one of the plurality of trench contacts has a recess therein (610 recessed inside 211 and 311);
a backside metal routing layer (930) extending beneath the plurality of gate lines and beneath the plurality of trench contacts; and
a conductive structure coupling the backside metal routing layer to a second one of the plurality of trench contacts (620), the conductive structure comprising a pillar portion (752) in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion (862/871), the line portion in contact with and extending along the backside metal routing layer (862/871 extending along 930).
(claim 7) a backside power delivery line (para 0047; 930 backside power distribution network (BSPDN).
(claim 8) a recessed deep boundary via structure (752).
Regarding claim 11, Xie discloses:
A computing device (paras 0052-0053; CPU), comprising:
a board (para 0052-0053; motherboard); and
a component coupled to the board (para 0052-0053), the component including an integrated circuit structure (Figs. 9C and 11C as supported by Figs. 1-9 and 11), comprising:
a plurality of gate lines (510, 520, 530, 540) extending over a plurality of semiconductor nanowire stack channel structures (para 0032; 210, 220, 310, 320, 410, 420, nanosheets transistors);
a plurality of trench contacts (610, 620) extending over a plurality of source or drain structures (211, 311), wherein a first one of the plurality of trench contacts has a recess therein (610 recessed inside 211 and 311);
a backside metal routing layer (930) extending beneath the plurality of gate lines and beneath the plurality of trench contacts; and
a conductive structure coupling the backside metal routing layer to a second one of the plurality of trench contacts (620), the conductive structure comprising a pillar portion (752) in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion (862/871), the line portion in contact with and extending along the backside metal routing layer (862/871 extending along 930).
Regarding claims 16, Xie discloses:
A computing device (paras 0052-0053; CPU), comprising:
a board (para 0052-0053; motherboard); and
a component coupled to the board (para 0052-0053), the component including an integrated circuit structure (Figs. 9C and 11C as supported by Figs. 1-9 and 11), comprising:
a plurality of gate lines (510, 520, 530, 540) extending over a plurality of semiconductor fin structures (para 0032; 210, 220, 310, 320, 410, 420, fin-type transistors);
a plurality of trench contacts (610, 620) extending over a plurality of source or drain structures (211, 311), wherein a first one of the plurality of trench contacts has a recess therein (610 recessed inside 211 and 311);
a backside metal routing layer (930) extending beneath the plurality of gate lines and beneath the plurality of trench contacts; and
a conductive structure coupling the backside metal routing layer to a second one of the plurality of trench contacts (620), the conductive structure comprising a pillar portion (752) in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion (862/871), the line portion in contact with and extending along the backside metal routing layer (862/871 extending along 930).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. US 2023/0345691 A1.
Regarding claims 12-15 and 17-20, although Xie does not specifically disclose “(claims 12 and 17) further comprising: a memory coupled to the board; (claims 13 and 18) further comprising: a communication chip coupled to the board; (claims 14 and 19) further comprising: a camera coupled to the board; (claims 15 and 20) wherein the component is a packaged integrated circuit die”, Xie does give insight into the various exemplary devices and components (paras 0052-0053) that may be determined and benefit from the application of Xie’s structure including power delivery in a finer footprint. Furthermore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the specific claimed components based on Xie’s disclosure relating the invention to a reduction in overall device size, thereby increasing functionality and performance, in various applications.
Claims 5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. US 2023/0345691 A1 in view of Xie et al. US 2023/0215767 A1.
Regarding claims 5 and 10, Xie ‘691 does not disclose:
further comprising a dielectric liner along sides of the pillar portion and the line portion of the conductive structure.
Xie ‘767 discloses a publication from a similar field of endeavor in which:
further comprising a dielectric liner along sides of a back side contact (para 0003; dielectric liner).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the dielectric liner of Xie ‘767 on the sides of the pillar and line portions of Xie ‘691 to further confine the back side contact thereby maintaining electrical integrity.
Allowable Subject Matter
Claims 4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations of claims 4 and 9 stating “wherein the pillar portion of the conductive structure extends between a pair of N-type source or drain structures of plurality of source or drain structures or extends between a pair of P-type source or drain structures of plurality of source or drain structures”. In light of these limitations in the disclosure (i.e. refer to applicant’s Figs. 2A-2D) amongst others, the previously applied references do not anticipate or obviate the context of the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERROL V FERNANDES/Primary Examiner, AU 2893