DETAILED ACTION
This application, 18/072702, attorney docket T101719US02, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Texas Instruments Incorporated, and claims priority from Provisional Application 63323616, filed 03/25/2022.
Applicant's election without traverse of Group I, claims 1-14 in the reply filed on 7/30/2025 is acknowledged. Claims 15-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-14 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Ito et al. (U.S. 6,057,572).
As for Claim 1,
Ito teaches in figure 3, an integrated circuit comprising:
a transistor having:
a transistor well (8) extending into a semiconductor substrate having a first dopant concentration (2e17, [co7 ln29]);
a gate electrode (25/24/9, [co8 ln16]) over the transistor well;
a gate insulating layer (8) between the transistor well and the gate electrode, the gate insulating layer having a first thickness (9nm, [co7 ln53]);
and a capacitor having:
a capacitor well (7) extending into the semiconductor substrate having a second dopant concentration greater (2e18, [co7 ln40]) than the first dopant concentration;
a capacitor electrode (12/14/15) over the capacitor well;
and a homogeneous capacitor insulating layer (11) between the capacitor well and the capacitor electrode having a greater thickness (35nm [co7 ln64]) than the gate insulating layer.
As for Claim 2,
Ito teaches the integrated circuit of claim 1, wherein a thickness of the homogeneous capacitor insulating layer is at least 50% greater than a thickness of the gate insulating layer (35nm is 400% bigger).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Liao et al. (U.S. 5,407,841).
As for Claim 3,
Ito teaches the integrated circuit of claim 1, but doesn’t teach comprising a trench isolation surrounding the capacitor.
However, Liao teaches in figure 3 isolating components using trench isolation.
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute an STI for the field oxide of Ito because STI reduces bird’s beak defect, allows planarization and increases device density. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 4,
Ito in view of Liao makes obvious the integrated circuit of claim 3, and it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the space between the well and isolation because it is a result dependent variable because the distance is designed to minimize the wasted space without doping the region under the STI. Therefore, because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
As for Claim 5,
Ito in view of Liao makes obvious the integrated circuit of claim 3, and in the combination, Liao teaches that the trench isolation includes a dielectric material (28) extending from a surface of the semiconductor substrate.
As for Claim 6,
Ito in view of Liao makes obvious the integrated circuit of claim 5, and in the combination, Liao teaches that the trench isolation further includes polycrystalline silicon, the dielectric material separating the polycrystalline silicon from the semiconductor substrate.
As for Claim 7,
Ito in view of Liao makes obvious the integrated circuit of claim 1, and in the combination, Ito teaches that the capacitor electrode includes polycrystalline silicon (34, [co5 ln1]).
Claim 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Cheng et al (U.S. 2013/0146953).
As for Claim 8,
Ito teaches an integrated circuit comprising:
an epitaxial layer having a first conductivity type over a semiconductor substrate;
a buried layer having the first conductivity type between the epitaxial layer and the substrate;
a first doped region (5) having the first conductivity type and a first dopant concentration extending into the epitaxial layer toward the buried layer;
a second doped region (7) having the first conductivity type and a second greater dopant concentration extending into the first doped region toward the buried layer ((2e18, [co7 ln40] vs (2e17, [co7 ln29])
an electrode over the second doped region; and a dielectric layer between the electrode and the second doped region.
Ito does not teach an epitaxial layer having a first conductivity type over a semiconductor substrate or a buried layer having the first conductivity type between the epitaxial layer and the substrate;
However, Cheng teaches in figures 2 and 6A, forming a transistor and capacitor on an epitaxial layer (20) having a first conductivity type [0035] over a semiconductor substrate (10) or a buried layer having the first conductivity type between the epitaxial layer and the substrate;
It would have been obvious to one skilled in the art at the effective filing date of this application to use an SOI substrate in the device of Ito because “SOI technology allows the formation of high-speed, shallow junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance” Cheng [0005]) One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 9,
Ito in view of Cheng makes obvious the integrated circuit of claim 8, and Ito teaches that the dopant concentration of the capacitor well is 5 x 1018 atoms/cm3.(2e18 [[co7 ln40]).
As for Claim 10
Ito in view of Cheng makes obvious the integrated circuit of claim 8, and in the combination, Cheng teaches that the epitaxial layer is crystalline silicon [0006].
As for Claim 11,
Ito in view of Cheng makes obvious the integrated circuit of claim 8, fand in the combination, Cheng teaches a trench isolation surrounding the capacitor.
It would have been obvious to one skilled in the art at the effective filing date of this application to use a trench isolation instead of the field oxide of Ito because STI reduces bird’s beak defect, allows planarization and increases device density. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 12,
Ito in view of Cheng makes obvious the integrated circuit of claim 11, and Ito makes obvious the capacitor well is spaced 2-4 um from the trench isolation. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the space between the well and isolation because it is a result dependent variable. because the distance is designed to minimize the wasted space without doping the region under the STI. Therefore, because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
As for Claim 13
Ito in view of Cheng makes obvious the integrated circuit of claim 11, and in the combination, Cheng teaches in figure 3 that the trench isolation includes a dielectric material ([0032]) extending from the surface of the epitaxial layer to the buried insulating layer.
It would have been obvious to one skilled in the art at the effective filing date of this application to extend the STI to the BOX to completely isolate the epi region. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 14
Ito in view of Cheng makes obvious the integrated circuit of claim 8, and in the combination, Ito teaches that the capacitor electrode includes polycrystalline silicon (34, [co5 ln1]).
Conclusion
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893