DETAILED ACTION
This application, 18/072702, attorney docket T101719US02, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Texas Instruments Incorporated, and claims priority from Provisional Application 63323616, filed 03/25/2022. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/13/2026 has been entered. Claims 1-14 and new claims 22-27 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Response to Arguments
In his response filed 7/13/26, Applicant argues that the objection to the drawings for a transistor and capacitor with a same well on the same substrate is not shown. Applicant is correct the objection did not accurately describe the claim. So, the previous objection is withdrawn and a more specific objection the drawing is presented below.
Applicant points to 112 and 150 as the first and second doped regions respectively, and correctly argues that objection was improper and so the drawing objection is withdrawn.
Applicant points to paragraphs [0011, 0030 and 0034] as support for a transistor well and argues that building a transistor on the well described in [0034] is adequate support for the element “transistor well” and examiner agrees that it would be obvious to one skilled, so the §112a rejection is withdrawn.
Applicant correctly argues that the §112 a rejection of claims 1-12 is improper because the claim does not recite “for a transistor and capacitor on a substrate that share a well but have separate dielectrics.” The §112 rejection is withdrawn.
Applicant has amended claim 1 and argues that art of record Anmo does not teach a capacitor well extending into the semiconductor substrate and having the first dopant concentration, which corresponds to the concentration of the transistor well.
However, remapping Anmo from the previous office action accommodated the amended claim because well 85A has the same dopant concentration as transistor well 85C.
Applicant has amended claim 8 and correctly argues that art of record Anmo does not teach “the first doped layer being spaced apart from the buried layer.” As required by the amended claim 8, so the previous rejections of claims 8-14 are withdrawn.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the transistor and capacitor on the same substrate recited in claims 1 and 8 and the two capacitors of claim 22, must be shown or the feature(s) canceled from the claim(s).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Anmo (U.S. 5,055,905) in view of Ito et al. (U.S. 6,057,572).
As for Claim 1,
Anmo teaches in figure 3 an integrated circuit comprising:
a transistor (89) having:
a transistor well (85c) extending into a semiconductor substrate and having a first dopant concentration (N-);
a gate electrode (66) over the transistor well;
a gate insulating layer (65) between the transistor well and the gate electrode,
the gate insulating layer having a first thickness; and
a capacitor (87) having:
a capacitor well (85A) extending into the semiconductor substrate and having the first dopant concentration (N-);
a doped region (46) extending into the capacitor well and having a second dopant concentration (N+) greater than the first dopant concentration;
a capacitor electrode (51) over the doped region; and
a homogeneous capacitor insulating layer (49) between the doped region and the capacitor electrode,
Anmo does not teach that the homogeneous capacitor insulating layer has a greater thickness than the gate insulating layer.
However, Ito teaches in figure 3, a homogeneous capacitor insulating layer (11) between the capacitor well and the capacitor electrode having a greater thickness of 35nm Ito [co9 ln59]) than the gate insulating layer of 9nm, (Ito [co9 ln66+]).
It would have been obvious to one skilled in the art at the effective filing date of this application to design the thickness of the capacitor insulation to be greater than the thickness of the gate oxide because “it allows the MOS capacitor to have a smaller coefficient of voltage while maintaining the channel performance of the transistor by separately controlling the gate oxide thickness. Ito [co1 ln55+]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 2,
Anmo in view of Ito makes obvious the integrated circuit of claim 1, in the suggested combination, Ito teaches that thickness of the homogeneous capacitor insulating layer is at least 50% greater than a thickness of the gate insulating layer (35nm is 389% bigger than the 9nm formed for the gate oxide). The motivation for the thicknesses is discussed above.
As for Claim 7,
Anmo in view of Ito makes obvious the integrated circuit of claim 1, and in the combination, Ito teaches that the capacitor electrode includes polycrystalline silicon (34, [co5 ln1]).
It would have been obvious to one skilled in the art at the effective filing date of this application to use a polysilicon electrode taught by Ito because doped polysilicon is one of a limited number of conductors used by semiconductor engineers and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable.
Claim 3-6 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Anmo in view of Ito and in further view of Liao et al. (U.S. 5,407,841).
As for Claim 3,
Anmo in view of Ito makes obvious the integrated circuit of claim 1, but the combination doesn’t teach comprising a trench isolation surrounding the capacitor (Anmo and Ito both teach LOCOS).
However, Liao teaches in figure 3 isolating components using trench isolation.
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute an STI for the field oxide of Anmo because STI reduces bird’s beak defect, allows planarization and increases device density. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 4,
Anmo in view of Ito and Liao makes obvious the integrated circuit of claim 3, and it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the space between the well and isolation because it is a result dependent variable because the distance is designed to minimize the wasted space without doping the region under the STI. Therefore, because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
As for Claim 5,
Anmo in view of Ito and Liao makes obvious the integrated circuit of claim 3, and in the combination, Liao teaches that the trench isolation includes a dielectric material (oxide 28) extending from a surface of the semiconductor substrate .
As for Claim 6,
Anmo in view of Ito and Liao makes obvious the integrated circuit of claim 5, and in the combination, Liao teaches that the trench isolation further includes polycrystalline silicon 34) , the dielectric material separating the polycrystalline silicon from the semiconductor substrate. (Liao [co4 ln50, ln65])
As for claim 22,
Anmo in view of Ito makes obvious the integrated circuit of claim 1, but doesn’t teach comprising a trench isolation surrounding the transistor. (Anmo and Ito teach LOCOS).
However, Liao teaches in figure 3 isolating components using trench isolation.
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute an STI for the field oxide of Anmo because STI reduces bird’s beak defect, allows planarization and increases device density. One skilled in the art would have combined these elements with a reasonable expectation of success.
Allowable Subject Matter
Claims 8-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not teach or make obvious the device claimed that includes an epitaxial layer over a semiconductor substrate, a buried layer between the epitaxial layer and the substrate; and a first doped region all having a first conductivity type the first doped region extending into the epitaxial layer but spaced apart from the buried layer; a second doped region having the first conductivity type and a greater dopant concentration, the second doped region extending into the first doped region toward the buried layer, an dielectric and electrode over the second doped region.
Claims 9-14 depend form claim 8 and include the same novel limitations.
Claims 23-27 are allowed
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach or make obvious the device claimed that includes a first MIS capacitor with dielectric of a first thickness over a well of a first conductivity type, and a second MIS capacitor with dielectric of a second thickness less than the first thickness over a well of a first conductivity type having a lower dopant level than the first capacitor.
Claims 24-27 depend from claim 23 and include the same limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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