DETAILED ACTION
This application, 18/072702, attorney docket T101719US02, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Texas Instruments Incorporated, and claims priority from Provisional Application 63323616, filed 03/25/2022.
Claims 1-14 and new claims 22-27 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Response to Arguments
Applicant has amended claim 1 and correctly argues that art of record Ito, has not been shown to teach "a doped region extending into the capacitor well and having a second dopant concentration greater than the first dopant concentration," as recited in amended claim 1. Region 7 maps to the doped region, and the n-doped region 1 maps to both the capacitor well and the transistor well. Ito is silent on the concentration of the n-well, so does not teach the limitation, so the rejections of claims 1-7 are withdrawn.
Applicant has amended claim 8 and correctly argues that art of record Ito has not been shown to teach “second doped region having the first conductivity type and a second greater dopant concentration, the second doped region extending into the first doped region toward the buried layer, so the rejections of claims 8-14 are withdrawn.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the transistor and capacitor with a common well on the same substrate recited in claim 1 must be shown or the feature(s) canceled from the claim(s).
The first doped region must be shown or the feature(s) canceled from the claim(s).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-7 are rejected under 35 U.S.C. 112(a) because the specification, while being enabling for a transistor or a capacitor, does not reasonably provide enablement for a transistor and capacitor on a substrate that share a well but have separate dielectrics. In addition, It is not clear what regions form the claimed wells, and the claimed “transistor well” is not defined in the specification or drawings. The specification does not enable any person skilled in the art to which it pertains, a semiconductor device designer, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Anmo (U.S. 5,055,905) in view of Ito et al. (U.S. 6,057,572).
As for Claim 1,
Anmo teaches in figure 3 an integrated circuit comprising:
a transistor (89) having:
a transistor well (85c) extending into a semiconductor substrate and having a first dopant concentration (N-);
a gate electrode (66) over the transistor well;
a gate insulating layer (65) between the transistor well and the gate electrode,
the gate insulating layer having a first thickness; and
a capacitor (87) having:
a capacitor well (46) extending into the semiconductor substrate and having a second dopant concentration (N+) greater than the first dopant concentration;
a doped region (45) extending into the capacitor well and having a second dopant concentration (N+) greater than the first dopant concentration;
a capacitor electrode (51) over the capacitor well doped region; and
a homogeneous capacitor insulating layer (49) between the capacitor well doped region and the capacitor electrode,
Anmo does not teach that the homogeneous capacitor insulating layer has a greater thickness than the gate insulating layer.
However, Ito teaches in figure 3, a homogeneous capacitor insulating layer (11) between the capacitor well and the capacitor electrode having a greater thickness of 35nm [co9 ln59]) than the gate insulating layer of 9nm, (Ito[co9 ln66+]).
It would have been obvious to one skilled in the art at the effective filing date of this application to design the thickness of the capacitor insulation to be greater than the thickness of the gate oxide because “it allows the MOS capacitor to have a smaller coefficient of voltage while maintaining the channel performance of the transistor by separately controlling the gate oxide thickness. Ito [co1 ln55+]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 2,
Anmo in view of Ito makes obvious the integrated circuit of claim 1, in the suggested combination, Ito teaches that thickness of the homogeneous capacitor insulating layer is at least 50% greater than a thickness of the gate insulating layer (35nm is 389% bigger than the 9nm formed for the gate oxide).
As for Claim 7,
Anmo in view of Ito makes obvious the integrated circuit of claim 1, and in the combination, Ito teaches that the capacitor electrode includes polycrystalline silicon (34, [co5 ln1]).
It would have been obvious to one skilled in the art at the effective filing date of this application to use a polysilicon electrode taught by Ito because doped polysilicon is one of a limited number of conductors used by semiconductor engineers and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable.
Claim 3-6 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Anmo in view of Ito and in further view of Liao et al. (U.S. 5,407,841).
As for Claim 3,
Anmo in view of Ito makes obvious the integrated circuit of claim 1, but doesn’t teach comprising a trench isolation surrounding the capacitor (Anmo and Ito teach LOCOS).
However, Liao teaches in figure 3 isolating components using trench isolation.
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute an STI for the field oxide of Anmo because STI reduces bird’s beak defect, allows planarization and increases device density. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 4,
Anmo in view of Ito and Liao makes obvious the integrated circuit of claim 3, and it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the space between the well and isolation because it is a result dependent variable because the distance is designed to minimize the wasted space without doping the region under the STI. Therefore, because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
As for Claim 5,
Anmo in view of Ito and Liao makes obvious the integrated circuit of claim 3, and in the combination, Liao teaches that the trench isolation includes a dielectric material (28) extending from a surface of the semiconductor substrate .
As for Claim 6,
Anmo in view of Ito and Liao makes obvious the integrated circuit of claim 5, and in the combination, Liao teaches that the trench isolation further includes polycrystalline silicon, the dielectric material separating the polycrystalline silicon from the semiconductor substrate. (Liao [co4 ln50])
As for claim 22,
Anmo in view of Ito makes obvious the integrated circuit of claim 1, but doesn’t teach comprising a trench isolation surrounding the transistor. (Anmo and Ito teach LOCOS).
However, Liao teaches in figure 3 isolating components using trench isolation.
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute an STI for the field oxide of Anmo because STI reduces bird’s beak defect, allows planarization and increases device density. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 8, 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Anmo in view of Cheng et al. (U.S. 2013/0146953).
As for Claim 8,
Anmo teaches in figure 6 teaches an integrated circuit comprising:
an epitaxial layer (24) having a first conductivity type (n) over a semiconductor substrate (22);
a buried layer (23) having the first conductivity type between the epitaxial layer and the substrate;
a first doped region (34) having the first conductivity type and a first dopant concentration (N+) the first doped region extending into the epitaxial layer toward the buried layer;
a second doped region (28) having the first conductivity type and a second greater dopant concentration (N+, undiffuse), the second doped region extending into the first doped region toward the buried layer
an electrode (30) over the second doped region; and a dielectric layer (29) between the electrode and the second doped region.
Anmo does not teach an epitaxial layer having a first conductivity type over a semiconductor substrate;
However, Cheng teaches in figures 2 and 6A, forming a transistor and capacitor on an epitaxial layer (20) having a first conductivity type [0035] over a semiconductor substrate (10);
It would have been obvious to one skilled in the art at the effective filing date of
this application to use an SOI substrate in the device of Ito because "SOI technology allows the formation of high-speed, shallow junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance" Cheng [0005]) One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 10,
Anmo in view of Cheng makes obvious the integrated circuit of claim 8, and in the combination, Cheng teaches that the epitaxial layer is crystalline silicon [0006].
As for Claim 11,
Anmo in view of Cheng makes obvious the integrated circuit of claim 8, and in the combination, Cheng teaches a trench isolation (STI25) surrounding each element.
It would have been obvious to one skilled in the art at the effective filing date of this application to use a trench isolation instead of the field oxide of Ito because STI reduces bird's beak defect, allows planarization and increases device density. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 12,
Anmo in view of Cheng makes obvious the integrated circuit of claim 11,
And Anmo makes obvious the capacitor well is spaced 2-4 um from the trench isolation.
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the space between the well and isolation because it is a result dependent variable because the distance is designed to minimize the wasted space without doping the region under the STI. Therefore, because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
As for Claim 13
Anmo in view of Cheng makes obvious the integrated circuit of claim 11, and in the combination, Cheng teaches in figure 3 that the trench isolation includes a dielectric material ([0032]) extending from the surface of the epitaxial layer to the buried insulating layer.
It would have been obvious to one skilled in the art at the effective filing date of
this application to extend the STI to the BOX to completely isolate the epi region. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Anmo in view of Cheng and further in view of Ito.
As for Claim 9,
Anmo in view of Cheng makes obvious the integrated circuit of claim 8, but Anmo does not teach that the dopant concentration of the capacitor well is 5 X 1018 atoms/cm3.
However, Ito teaches that the dopant concentration of the capacitor well is 5 X 1018 atoms/cm3.(2e18 [co7 In40]).
It would have been obvious to one skilled in the art at the effective filing date of this application use the dopant concentration of Ito in the well of Anmo because one of ordinary skill in the art could have used the specific dopant level in the same way of Ito and the results would have been predictable to one of ordinary skill in the art .
As for Claim 14
Anmo in view of Cheng makes obvious the integrated circuit of claim 8, and in the combination, but does not teach hat the capacitor electrode includes polycrystalline silicon.
However, Ito teaches that the capacitor electrode includes polycrystalline silicon (34,[co5 In1]).
It would have been obvious to one skilled in the art at the effective filing date of this application to use a polysilicon electrode taught by Ito because doped polysilicon is one of a limited number of conductors used by semiconductor engineers and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable.
Claim 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Anmo in view of Ito and in further view of Iyer et al (U.S. 2022/0392893).
As for claim 23,
Anmo teaches an integrated circuit comprising:
a first capacitor having (87):
a first capacitor well (85a) extending into a semiconductor substrate and having a first dopant concentration;
a first capacitor electrode (51) over the first capacitor well;
a first capacitor insulating layer (49) between the first capacitor electrode and the first capacitor well, the first capacitor insulating layer having a first thickness; and
Anmo does not teach a second capacitor with a thinner capacitor insulation layer.
However, Iyer teaches multiple MOS capacitors formed on a substrate having different insulation thicknesses Iyer [0046].
It would have been obvious to one skilled in the art at the effective filing date of this application add the second capacitor of Iyer to the device of Anmo in order to build an electrostatic discharge circuit. Iyer [0046]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 24,
Anmo in view of Iyer makes obvious the integrated circuit of claim 23, and in the combination, Anmo teaches that the first capacitor further comprises a doped region (46) extending into the first capacitor well and having a second dopant concentration greater than the first dopant concentration (N+ vs N-), and
wherein the first capacitor insulating layer is disposed between the first capacitor electrode and the doped region. Shown in figure 3.
Claim 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Anmo in view of Iyer and in further view of Liao et al. (U.S. 5,407,841).
As for Claim 25,
Anmo in view of Iyer makes obvious the integrated circuit of claim 24s, but doesn’t teach comprising a trench isolation surrounding the capacitor (Anmo teaches LOCOS).
However, Liao teaches in figure 3 isolating components using trench isolation.
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute an STI for the field oxide of Anmo because STI reduces bird’s beak defect, allows planarization and increases device density. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 26,
Anmo in view of Iyer and Liao makes obvious the integrated circuit of claim 25, and in the combination Liao teaches at least one of the first trench isolation or the second trench isolation includes a dielectric material extending from a surface of the semiconductor substrate.(“an oxide layer 32 is grown within the trench to a thickness of about 2,000 Angstroms. This is followed by the deposition of undoped polysilicon 34, to a thickness of about 1.5 microns, over the entire substrate and filling the trench 26.” Liao [co4 ln67].
As for claim 27,
Anmo in view of Iyer and Liao makes obvious the integrated circuit of claim 26, and in the combination, Liao teaches that the at least one of the first trench isolation or the second trench isolation further includes polycrystalline silicon, the dielectric material separating the polycrystalline silicon from the semiconductor substrate.(“an oxide layer 32 is grown within the trench to a thickness of about 2,000 Angstroms. This is followed by the deposition of undoped polysilicon 34, to a thickness of about 1.5 microns, over the entire substrate and filling the trench 26.” Liao [co4 ln67].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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