Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election without traverse of Invention I and Species I (claims 1-11 and previously added claims 21-28) in the reply filed on March 5.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on November 25, 2025 and February 23, 2026 are being considered by the examiner.
The reference Jaffe et al (US 2013/0337886 A1) in the IDS submitted February 23, 2026 does not appear relevant to the instant application and has not been considered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed October 21, 2025 and entered with the request for continued examination dated November 3, 2025. Claims 1, 5, 7, 9, 21, 24, 26, and 28 are amended. The Examiner notes that claims 1-11 and 21-28 are examined.
Claim Rejections - 35 USC § 103
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0242092 A1) in view of Michizuki (2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020), Liaw (US 2021/0083054 A1), and Ando (US 10,490,559 B1).
With respect to claim 1, Chen teaches in Figs. 1A and 23:
a wafer (substrate 10),
and at least a first transistor of a first polarity and a second transistor of a second polarity on the wafer (see annotated Fig. 1A below. Para. 13, “although the IC device 90 as illustrated is a three-dimensional FinFET device, the concepts of the present disclosure may also apply to planar FET devices or GAA devices.” Fig. 23 teaches a GAA device that can be used with the embodiment of Fig. 1, Para. 79 teaches that the GAA devices may be an NFET or a PFET. Para. 22 teaches “the gate structures 200A-200F may be formed on the same wafer” and 200A-200C correspond to NFETs while 200D-200F correspond to PFETs. It would be obvious to the ordinary artisan to combine these teachings to make a device 90 that includes one NFET GAA transistor and one PFET GAA transistor.)
wherein the first transistor (PFET GAA according to the embodiment of Fig. 23 which may be a PFET per para. 79) and the second transistor (NFET GAA according to the embodiment of Fig. 23 which may be an NFET per para. 79) each comprises multiple channels (channels 830-833),
and wherein the multiple channels of the first transistor comprise first portions and second portions (see annotated Fig. 23 below)
Chen fails to teach:
with the first portions having cores and a cladding layer fully surrounding the cores,
wherein a first gate material of the first transistor is in direct contact with a second gate material of the second transistor.
wherein the first transistor further includes a first gate dielectric layer and a dielectric cap, wherein the dielectric cap is in direct contact with the first gate dielectric layer, wherein the first gate material is in direct contact with the dielectric cap, wherein the second transistor includes a second gate dielectric layer, wherein the second gate material is in direct contact with the second gate dielectric layer, wherein the dielectric cap is not in contact with the second dielectric layer.
Mochizuki teaches in Fig. 1:
with the first portions (thinned portions) having cores (Si part that has been thinned in “Si NS trimming” step) and a cladding layer fully (SiGe part added in the “SiGe cladding growth” step) surrounding the cores (see “SiGe cladding growth” section of Fig. 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Mochizuki into the device of Chen to add a cladding layer around the core of the channel. The ordinary artisan would have been motivated to modify Chen in the manner set forth above for the purpose of causing an “uplift in peak hole mobility with a corresponding channel resistance reduction” (Conclusions of Mochizuki).
Liaw teaches in Fig. 9B:
wherein a first gate material (p-type metal gate stack 211-2) of the first transistor (transistor on right) is in direct contact with a second gate material (n-type metal gate stack 211-1) of the second transistor (transistor on left).
Chen/Mochizuki discloses the claimed invention except for the first and second gate materials being in direct contact with each other. Liaw discloses that it is known in the art to provide a first gate material and second gate material in contact with each other. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the dual transistor structure of Chen/Mochizuki with the gate material layout of Liaw in order to simplify the manufacturing process and increase integration of the devices. See MPEP 2144.
Ando teaches in Fig. 13:
wherein the first transistor (pFET region 770) further includes a first gate dielectric layer (conformal gate dielectric 772) and a dielectric cap (ALD pFET WFM 874, made of for example TiN (col. 12, lns. 38-39) which is the material taught in para. [0074] of the instant application to comprise the dielectric cap),
wherein the dielectric cap (874) is in direct contact with the first gate dielectric layer (772),
wherein the first gate material (CVD PFET WFM 902) is in direct contact with the dielectric cap (874),
wherein the second transistor (nFET region 760) includes a second gate dielectric layer (gate dielectric layer 762),
wherein the second gate material (NFET WFM 1302) is in direct contact with the second gate dielectric layer (762),
wherein the dielectric cap (874) is not in contact with the second dielectric layer (762).
Chen/Mochizuki/Liaw discloses the claimed invention except for the dielectric cap in direct contact with the first dielectric layer but not the second gate dielectric layer. Ando teaches that it is known to include a TiN layer over the first dielectric layer that can be considered a dielectric cap as claimed. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chen/Mochizuki/Liaw to include a TiN dielectric cap layer over the first gate dielectric but not the second gate dielectric as taught by Ando for the purpose of setting the workfunction of the gate of the first transistors. See MPEP 2144.
With respect to claim 2, Chen further teaches:
wherein the first transistor comprises a p-channel field-effect transistor (PFET version of Fig. 23, para. 79) and the second transistor comprises an n-channel field-effect transistor (NFET version of Fig. 23, para. 79).
With respect to claim 3, Mochizuki further teaches:
wherein the cores comprise silicon (Si) (Si part that has been thinned in “Si NS trimming” step of Fig. 1 of Mochizuki), and wherein the cladding layer comprises silicon germanium (SiGe) (SiGe part added in the “SiGe cladding growth” step of Fig. 1 of Mochizuki).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Chen in view of Mochizuki as explained above
With respect to claim 4, Chen further teaches:
a first gate (gate structure that includes gate dielectric layers 850, work function metal layers 860, and fill metals 880) surrounding the first portions of the multiple channels (thin parts of 830-833) of the first transistor (PFET GAA as described above);
and a second gate (gate structure that includes gate dielectric layers 850, work function metal layers 860, and fill metals 880) surrounding the multiple channels (830-833) of the second transistor (NFET GAA as described above),
wherein the first gate comprises at least one first workfunction-setting metal (860 of PFET) and the second gate comprises at least one second workfunction-setting metal (860 of NFET),
and wherein the at least one first workfunction- setting metal (para. 85 “In embodiments where the GAA device 800 is a PFET, the one or more work function metal layers 860 include P-type work function metal layers, such as TiN) is different from the at least one second workfunction-setting metal (para. 85 “In embodiments where the GAA device 800 is an NFET, the one or more work function metal layers 860 include N-type work function metal layers, such as TiAlC.”)
With respect to claim 5, Chen further teaches:
a first interfacial layer (interfacial layer 840 of PFET) disposed on the first portions of the multiple channels (narrow part of 830-833) of the first transistor (PFET) (para 84. “A plurality of interfacial layers (ILs) 840 are formed on the upper and lower surfaces of the channels 830-833”)
wherein the first gate dielectric layer (gate dielectric layer 850 of PFET) is also disposed on the first interfacial layer (840 of PFET);
a second interfacial layer (interfacial layer 840 of NFET) disposed on the multiple channels (830-833 of NFET) of the second transistor (NFET);
and wherein the second gate dielectric (gate dielectric layer 850 of NFET) layer is also disposed on the second interfacial layer (840 of NFET)
With respect to claim 6, Chen further teaches:
wherein the first interfacial layer (840 of PFET) has at least one of a different composition (abstract “first interfacial layer contains a different amount of a dipole material than the second interfacial layer”) and a different thickness from the second interfacial layer (840 of NFET).
With respect to claim 7, Chen teaches:
wherein the first gate dielectric layer (850 of PFET) has at least one of a different composition (para. 85 “the gate dielectric layers 850 may also have dipole-penetrated portions near their interfaces with the ILs”, para. 85, “gate dielectric layers 850, which may be similar to the gate dielectric layer 430”, para. 49 “the annealing process may cause further diffusion of the dipole material from the dipole-penetrated portion 210A to the gate dielectric layer 430”, para. 74 “The IL 210 for the NFET gate structure 760 and the IL 210 for the PFET gate structure 770 may also contain different types of dipole materials”) and a different thickness from the second gate dielectric (850 of NFET)
Alternatively, Chen also teaches that gate dielectric layers 850 may be similar to the gate dielectric layer 430 and in para. 45 teaches “the gate dielectric layer 430 includes a high-k dielectric material, which may refer to dielectric materials having a high dielectric constant that is greater than a dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO.sub.2, Al.sub.2O.sub.3, HfO.sub.2—Al.sub.2O.sub.3, TiO.sub.2, Ta.sub.2O.sub.5, La.sub.2O.sub.3, Y.sub.2O.sub.3, or combinations thereof.” It would be obvious to the ordinary artisan to use different compositions for the first and second gate dielectric layers because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 8, Chen teaches:
wherein the first interfacial layer (840 of PFET) comprises at least one different dipole dopant (para. 84 “The ILs 840 may be substantially similar to the IL 210”, para. 74 “The IL 210 for the NFET gate structure 760 and the IL 210 for the PFET gate structure 770 may also contain different types of dipole materials”) from the second interfacial layer (840 of NFET).
With respect to claim 9, Chen further teaches:
wherein the first gate dielectric layer comprises (850 of PFET) at least one different dipole dopant (para. 85 “the gate dielectric layers 850 may also have dipole-penetrated portions near their interfaces with the ILs”, para. 85, “gate dielectric layers 850, which may be similar to the gate dielectric layer 430”, para. 49 “the annealing process may cause further diffusion of the dipole material from the dipole-penetrated portion 210A to the gate dielectric layer 430”, para. 74 “The IL 210 for the NFET gate structure 760 and the IL 210 for the PFET gate structure 770 may also contain different types of dipole materials”) from the second gate dielectric (850 of NFET).
With respect to claim 10, Chen/Mochizuki/Liaw further teaches in Fig. 23 of Chen:
first source/drain regions (source drain 820 of PFET of Chen) on opposite sides of the first gate (gate structure of PFET GAA that comprises 850, 860, and 880 of Chen);
and second source/drain regions (source drain 820 of NFET of Chen) on opposite sides of the second gate (gate structure of NFET GAA that comprises 850, 860, and 880),
wherein the first portions (see annotated Fig. 23 below) of the multiple channels (830-833) of the first transistor (PFET) are connected to the first source/drain regions (820 of PFET) by the second portions (see annotated Fig. 23 below),
and wherein the second portions have a same composition as the cores (the second part and the first part of an individual channel together comprise one of channels 830-833, Para. 81, “the channels 830-833 each include a semiconductive material, for example silicon” Mochizuki teaches in Fig. 1 that the cores are made of silicon.)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Chen in view of Mochizuki as explained above
With respect to claim 11, Chen further teaches:
wherein the multiple channels (830-833 of NFET of Chen) of the second transistor (NFET GAA of Chen) comprise the same composition (the channels 830-833 each include a semiconductive material, for example silicon”) as the cores (Mochizuki teaches in Fig. 1 that the cores are made of silicon).
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Claims 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0242092 A1) in view of Michizuki (2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020) and Ando (US 10,490,559 B1).
With respect to claim 21, Chen teaches in Figs. 1A and 23:
a wafer (substrate 10),
and a first transistor of a first polarity and a second transistor of a second polarity on the wafer (see annotated Fig. 1A below. Para. 13, “although the IC device 90 as illustrated is a three-dimensional FinFET device, the concepts of the present disclosure may also apply to planar FET devices or GAA devices.” Fig. 23 teaches a GAA device that can be used with the embodiment of Fig. 1, Para. 79 teaches that the GAA devices may be an NFET or a PFET. Para. 22 teaches “the gate structures 200A-200F may be formed on the same wafer” and 200A-200C correspond to NFETs while 200D-200F correspond to PFETs. It would be obvious to the ordinary artisan to combine these teachings to make a device 90 that includes one NFET GAA transistor and one PFET GAA transistor.)
wherein the first transistor (PFET GAA according to the embodiment of Fig. 23 which may be a PFET per para. 79) and the second transistor (NFET GAA according to the embodiment of Fig. 23 which may be an NFET per para. 79) each comprises multiple channels (channels 830-833),
and wherein the multiple channels of the first transistor comprise first portions and second portions (see annotated Fig. 23 below)
Chen fails to teach:
with the first portions having cores and a cladding layer fully surrounding the cores.
wherein a first dielectric layer and a dielectric cap are located beneath a first gate material of the first transistor,
wherein the dielectric cap is in direct contact with the first dielectric layer, wherein the first gate material is in direct contact with the dielectric cap,
wherein a second dielectric layer is located beneath a second gate material of the second transistor
wherein the second gate material is in direct contact with the second dielectric layer, wherein the dielectric cap is not in contact with the second dielectric layer.
Mochizuki teaches in Fig. 1:
with the first portions (thinned portions) having cores (Si part that has been thinned in “Si NS trimming” step) and a cladding layer fully (SiGe part added in the “SiGe cladding growth” step) surrounding the cores (see “SiGe cladding growth” section of Fig. 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Mochizuki into the device of Chen to add a cladding layer around the core of the channel. The ordinary artisan would have been motivated to modify Chen in the manner set forth above for the purpose of causing an “uplift in peak hole mobility with a corresponding channel resistance reduction” (Conclusions of Mochizuki).
Ando teaches in Fig. 13:
wherein a first dielectric layer (gate dielectric 772) and a dielectric cap (ALD pFET WFM 874) are located beneath a first gate material (CVD pFET WFM 902) of the first transistor (pFET),
wherein the dielectric cap (874) is in direct contact with the first dielectric layer (772), wherein the first gate material (902) is in direct contact with the dielectric cap (874),
wherein a second dielectric layer (gate dielectric 762) is located beneath a second gate material (nFET WFM 1302) of the second transistor (nFET)
wherein the second gate material (1302) is in direct contact with the second dielectric layer (762), wherein the dielectric cap (874) is not in contact with the second dielectric layer (762).
Chen/Mochizuki discloses the claimed invention except for the dielectric layer and dielectric cap beneath the gate materials. Ando discloses that it is known in the art to provide a dielectric layers and dielectric caps beneath the gate material of a first transistor while there is not dielectric cap below the second transistor. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the dual transistor structure of Chen/Mochizuki with the gate dielectric and dielectric cap layers of Ando in order to create a dual transistor device in which the devices are tuned with different WF metals. See MPEP 2144.
With respect to claim 22, Mochizuki further teaches:
wherein the cores comprise silicon (Si) (Si part that has been thinned in “Si NS trimming” step of Fig. 1 of Mochizuki), and wherein the cladding layer comprises silicon germanium (SiGe) (SiGe part added in the “SiGe cladding growth” step of Fig. 1 of Mochizuki).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Chen in view of Mochizuki as explained above
With respect to claim 23, Chen further teaches:
a first gate (gate structure that includes gate dielectric layers 850, work function metal layers 860, and fill metals 880) surrounding the first portions of the multiple channels (thin parts of 830-833) of the first transistor (PFET GAA as described above);
and a second gate (gate structure that includes gate dielectric layers 850, work function metal layers 860, and fill metals 880) surrounding the multiple channels (830-833) of the second transistor (NFET GAA as described above),
wherein the first gate comprises at least one first workfunction-setting metal (860 of PFET) and the second gate comprises at least one second workfunction-setting metal (860 of NFET),
and wherein the at least one first workfunction- setting metal (para. 85 “In embodiments where the GAA device 800 is a PFET, the one or more work function metal layers 860 include P-type work function metal layers, such as TiN) is different from the at least one second workfunction-setting metal (para. 85 “In embodiments where the GAA device 800 is an NFET, the one or more work function metal layers 860 include N-type work function metal layers, such as TiAlC.”)
With respect to claim 24, Chen further teaches:
a first interfacial layer (interfacial layer 840 of PFET) disposed on the first portions of the multiple channels (narrow part of 830-833) of the first transistor (PFET) (para 84. “A plurality of interfacial layers (ILs) 840 are formed on the upper and lower surfaces of the channels 830-833”)
wherein the first gate dielectric layer (gate dielectric layer 850 of PFET) is also disposed on the first interfacial layer (840 of PFET);
a second interfacial layer (interfacial layer 840 of NFET) disposed on the multiple channels (830-833 of NFET) of the second transistor (NFET);
and wherein the second gate dielectric layer (gate dielectric layer 850 of NFET) is also disposed on the second interfacial layer (840 of NFET)
With respect to claim 25, Chen further teaches:
wherein the first interfacial layer (840 of PFET) has at least one of a different composition (abstract “first interfacial layer contains a different amount of a dipole material than the second interfacial layer”) and a different thickness from the second interfacial layer (840 of NFET).
With respect to claim 26, Chen teaches:
wherein the first gate dielectric layer (850 of PFET) has at least one of a different composition (para. 85 “the gate dielectric layers 850 may also have dipole-penetrated portions near their interfaces with the ILs”, para. 85, “gate dielectric layers 850, which may be similar to the gate dielectric layer 430”, para. 49 “the annealing process may cause further diffusion of the dipole material from the dipole-penetrated portion 210A to the gate dielectric layer 430”, para. 74 “The IL 210 for the NFET gate structure 760 and the IL 210 for the PFET gate structure 770 may also contain different types of dipole materials”) and a different thickness from the second gate dielectric (850 of NFET)
Alternatively, Chen also teaches that gate dielectric layers 850 may be similar to the gate dielectric layer 430 and in para. 45 teaches “the gate dielectric layer 430 includes a high-k dielectric material, which may refer to dielectric materials having a high dielectric constant that is greater than a dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO.sub.2, Al.sub.2O.sub.3, HfO.sub.2—Al.sub.2O.sub.3, TiO.sub.2, Ta.sub.2O.sub.5, La.sub.2O.sub.3, Y.sub.2O.sub.3, or combinations thereof.” It would be obvious to the ordinary artisan to use different compositions for the first and second gate dielectric layers because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 27, Chen teaches:
wherein the first interfacial layer (840 of PFET) comprises at least one different dipole dopant (para. 84 “The ILs 840 may be substantially similar to the IL 210”, para. 74 “The IL 210 for the NFET gate structure 760 and the IL 210 for the PFET gate structure 770 may also contain different types of dipole materials”) from the second interfacial layer (840 of NFET).
With respect to claim 28, Chen further teaches:
wherein the first gate dielectric layer comprises (850 of PFET) at least one different dipole dopant (para. 85 “the gate dielectric layers 850 may also have dipole-penetrated portions near their interfaces with the ILs”, para. 85, “gate dielectric layers 850, which may be similar to the gate dielectric layer 430”, para. 49 “the annealing process may cause further diffusion of the dipole material from the dipole-penetrated portion 210A to the gate dielectric layer 430”, para. 74 “The IL 210 for the NFET gate structure 760 and the IL 210 for the PFET gate structure 770 may also contain different types of dipole materials”) from the second gate dielectric (850 of NFET).
Response to Arguments
Applicant’s arguments with respect to claims 1-11 and 21-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897