Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 9/15/2025 has been entered. Claims 1-2, 5, 8-14, and 16 remain pending.
The amendments to claims 12-14 and the cancellation of claim 15 overcomes the objections to these claims. Thus, Examiner withdraws these objections.
Response to Arguments
Applicant’s arguments with respect to claims 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Please see claim rejections below.
Applicant’s argument with respect to claim 16 is dealt with in the claim rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US9196575B1 (Lee) in view of CN112447625A (Fei) and US5646828A (Degani).
Regarding Claim 1, Lee discloses a packaging structure (Fig. 2C, el. 202, Col. 4, ll. 17-18), comprising: a first chip (Figs. 1 and 2C, el. 104B, Col. 2, ll. 34-35), comprising a first connecting surface (Figs. 1 and 2C, Col. 2, ll. 38-40) and a first heat-conducting surface (Figs. 1 and 2C, Col. 2, ll. 44-46) that face away from each other (see Figs. 1 and 2C); a second chip (Figs. 1 and 2C, el. 104A, Col. 2, ll. 34-35) disposed on a side of the first connecting surface (Figs. 1 and 2C, Col. 2, ll. 38-40) and electrically connected to the first chip (Fig. 2C, Cols. 6-7 ,ll. 67-4) wherein a side of the second chip distal from the first chip comprises a second heat-conducting surface (Figs. 1 and 2C, Col. 2, ll. 50-53); and a first heat conductor (Fig. 2C, el. 106, Col. 4, ll. 29-31) and a second heat conductor (Fig. 1, el. 101, Col. 2, ll. 48-50), the first heat conductor being connected to the first heat-conducting surface (Figs. 1 and 2C, Col. 2, ll. 44-46) and the second heat conductor being connected to the second heat-conducting surface (Figs. 1 and 2C, Col. 2, ll. 48-50); the packaging structure further comprising a first substrate (Fig. 2C, el. 102, Col. 4, ll. 29-31) having a cavity (see Fig. 2C, el. 301, ll. 29-31) in which the first chip is placed (Fig. 2C, Col. 4, ll. 46-49), the cavity is a through hole running through the first substrate (Figs. 2C and 3A, Col. 4, ll. 42-43), and the first heat-conducting surface is exposed from the through hole (Fig. 2C, Col. 4, ll. 46-49), and connected to the first heat-conducting surface exposed from the through hole (Fig. 2C).
Lee does not disclose that the first heat conductor is disposed on a side of the first substrate distal from the second chip, and does not disclose that the first heat conductor does not extend into the through hole.
Fei discloses a package (Fig. 2, Para. [0066]) where a first heat conductor (Fig. 2, el. 40, Para. [0066]) extends through a substrate (Fig. 2) to connect to a chip (Fig. 2, el. 10, Para. [0066]). Degani discloses a package (Fig. 9) with a substrate (Fig. 9, el. 85, Col. 7, ll: 59-62) that has a cavity (Fig. 8, el. 87, Col. 7, ll: 63-65) that extends through the substrate (Fig. 9). A heat dissipation structure (Fig. 9, el. 88, Col. 7, ll. 65-66) is attached to the bottom of a semiconductor chip in the cavity (Fig. 9), such that the heat dissipation structure does not extend into the cavity (Fig. 9).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the first heat conductor disclosed by Lee, and move it down below a second substrate (Lee, Fig. 2C, el. 305) by creating notch in the second substrate so that it is disposed on a side of the first substrate 102 that is distal from the second chip 104A. Doing so would have the advantage of allowing for greater heat transfer by allowing the heat conductor to be larger. Further, it would have been obvious to not allow the first heat conductor to extend into the cavity, as disclosed by Degani, for the purpose of saving space and creating a smaller package (the size of the substrate 102 in Lee can be reduced if the heat dissipation structure is moved into the substrate 305). The motivation for doing so is disclosed in Degani (Col. 3, ll: 64-67 and Col. 4, ll: 1 – 17).
Regarding Claim 2, Lee in view of Fei and Degani discloses the packaging structure according to claim 1, wherein a gap between the first chip and the cavity is filled with a bonding material (Lee, Figs 1 and 2C, el. 105, Col. 2, ll. 46-48).
Regarding Claim 5, Lee in view of Fei and Degani discloses the packaging structure according to claim 1, further comprising: a second substrate (Lee, Fig. 2C, el. 305), disposed on a side of the first substrate distal from the second chip (Lee, see Fig. 2C) and electrically connected to the first substrate (Lee, Col. 3, ll. 52-57); and the first heat conductor (Fei, Fig. 2, el. 40, Para. [0066])) comprises a heat-conducting back plate (Fei, Para. [0066])) and an extension (Fei, el. 20, Para. [0066]) extending from the heat-conducting back plate (Para. [0066]); wherein the second substrate is provided with a notch for the extension (see claim 4), the extension is inserted into the notch to be connected to the first heat conducting surface (see claim 4), and the second substrate is sandwiched between the first substrate and the heat conducting back plate (when the heat conducting plate is moved down below the second substrate, the second substrate is sandwiched between the first substrate and the heat conducting back plate).
Regarding Claim 8, Lee in view of Fei and Degani discloses the packaging structure according to claim 2, wherein a size of the second chip is larger than a size of the first chip (Fig. 1, where a size of the second chip 104A is larger than a size of the first chip 104B), and a metal bump protrudes from a second connecting surface of the second chip facing the first substrate (Fig. 2C), and is electrically connected to a corresponding first bonding pad on the first substrate (Fig. 2C, Col. 3, ll. 12-17).
Regarding Claim 12, Lee in view of Fei and Degani discloses the packaging structure according to claim 2, wherein the first connecting surface of the first chip protrudes from or is flush with a first connecting surface of the first substrate (Lee, Fig. 2C, where the first connecting surface of the first chip is flush with the third connecting surface of the first substrate).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Fei and Degani.
Regarding Claim 11, Lee in view of Fei and Degani discloses the packaging structure according to claim 2, and that the second chip is electrically connected to the first chip and the first substrate (see claims 1 and 2).
Lee in view of Fei and Degani does not disclose that side of the second chip facing the first chip comprises an interconnecting structural layer, and the interconnecting structural layer is electrically connected to the first chip and the first substrate.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add an interconnecting structural layer to the second chip of Lee. Doing so would have the benefit of adding a dedicated layer to the second chip for ease of interconnecting it to the first chip and first substrate, and any other elements that might be added.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Fei and Degani.
Regarding Claim 16, Lee in view of Fei and Degani discloses the packaging structure according to claim 5.
Lee in view of Fei and Degani does not disclose that the extension and the heat-conducting back plate are of an integral structure.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to take the heat conducting back plate (Fei, Fig. 2, el. 40) of Fei and make it integral with the extension (Fei, Fig. 2, el. 20) for the purpose of avoiding adding a TIM layer between the two for better heat transfer.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Fei, Degani, and US8519537B2 (Jeng).
Regarding Claim 9, Lee in view of Fei and Degani discloses the packaging structure according to claim 2.
Lee in view of Fei and Degani does not disclose that the packaging structure further comprises an interposer, wherein the interposer is electrically connected to the first chip and the first substrate.
Jeng discloses a packaging structure (Fig. 1A) with an interposer (Fig. 1A, el. 102, Col. 2, ll. 34-43), wherein the interposer is electrically connected to a first chip (Fig. 1A, el. 108, Col. 2, ll. 34-43) and a first substrate (Fig. 1A, el. 112, Col. 2, ll. 44-47).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the interposer disclosed by Jeng and add it to the package disclosed by Lee such that the interposer is electrically connected to the first chip and the first substrate, as disclosed by Jeng. Further, the second chip disclosed by Lee could be moved over to make room for the interposer. Doing so would have the benefit, as disclosed by Jeng, of enabling further interconnections between the first chip and substrate and other elements (Col. 2, ll. 47-56).
Regarding Claim 10, Lee in view Fei, Degani, and Jeng discloses the packaging structure according to claim 9, wherein a part of a heat-conducting area of the second heat conductor covers a side of the interposer distal from the first substrate (see Fig. 2C, where the second heat conductor, which is a lid covers the entire package, and so would cover an interposer attached to the first chip 104B and the first substrate 102).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Degani.
Regarding Claim 13, Lee discloses a method of manufacturing a packaging structure (Fig. 6, Col. 6, ll. 60-62), comprising: providing a first chip and a second chip that are electrically connected (Fig. 6, el. 601, Col. 6, ll. 64-66, Col. 7, ll. 1-4), the first chip comprising a first heat-conducting surface distal from the second chip (Fig. 2C), and the second chip comprising a second heat-conducting surface distal from the first chip (Fig. 2C); connecting a first heat conductor to the first heat-conducting surface (Fig. 6, el. 604, Col. 7, ll. 13-18); and connecting a second heat conductor to the second heat-conducting surface (Fig. 6, el. 606, Col. 7, ll. 21-25), wherein prior to connecting the first heat conductor to the first heat-conducting surface, the manufacturing method further comprises: providing a first substrate having a cavity, the cavity being a through-hole (Fig. 6, el. 602, Col. 7, ll. 5; Fig. 3A, el. 301, Col. 7, ll. 5-8), placing the first chip into the through hole (Fig. 6, el. 604, Col. 7, ll: 13-20), and exposing the first heat-conducting surface from the through-hole (Fig. 6, el. 603, Col. 7, ll: 5-12).
Lee does not disclose that the first heat conductor does not extend into the through hole.
Degani discloses a package (Fig. 9) with a substrate (Fig. 9, el. 85, Col. 7, ll: 59-62) that has a cavity (Fig. 8, el. 87, Col. 7, ll: 63-65) that extends through the substrate (Fig. 9). A heat dissipation structure (Fig. 9, el. 88, Col. 7, ll. 65-66) is attached to the bottom of a semiconductor chip in the cavity (Fig. 9), such that the heat dissipation structure does not extend into the cavity (Fig. 9).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the method disclosed by Lee, and not allow the first heat conductor to extend into the cavity, as disclosed by Degani, for the purpose of saving space and creating a smaller package (the size of the substrate 102 in Lee can be reduced if the heat dissipation structure is moved into the substrate 305). The motivation for doing so is disclosed in Degani (Col. 3, ll: 64-67 and Col. 4, ll: 1 – 17).
Regarding Claim 14, Lee in view of Degani discloses the method of manufacturing a package structure according to Claim 13, wherein the manufacturing method further comprises: filling a gap between the first chip and the cavity with a bonding material, and fixing the first chip to the first substrate (Col. 2, ll. 46-48).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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