Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Drawings Objection
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “the first via is arranged at a position overlapping with the third upper electrode in a plan view” in Claim 18 must be shown or the feature(s) canceled from the claim(s). FIG. 2 clearly shows the first vias 7 are NOT overlap with the third upper electrode 5 in a plan view. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections Withdrawal
Applicant’s argument with respect to 112 rejection is persuasive. Thus, the rejection under 35 U.S.C. 112(a) is withdrawn.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 20 and 21 rejected under 35 U.S.C. 102(a)(1) as being anticipated Shih (U.S. Patent Pub. No. 2017/0018550) of record.
Regarding Claim 20
FIG. 1 of Shih discloses a semiconductor device, comprising: a lower electrode (11); a first dielectric layer (21 and portion of 40 extended from 21) provided on the lower electrode; a first upper electrode (12) provided on the first dielectric layer; a second dielectric layer (22 and portion of 40 extended from 22) provided on the first upper electrode; a second upper electrode (13) provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer (23 and portion of 40 extended from 23) provided on the second upper electrode; and a third upper electrode (14) provided on the third dielectric layer and electrically connected to the first upper electrode; and a protective film (portion of 40 above 240) provided on the third upper electrode, wherein a first capacitor (C1) between the lower electrode and the first upper electrode, a second capacitor (C2) between the first upper electrode and the second upper electrode, and a third capacitor (C3) between the second upper electrode and the third upper electrode are connected in parallel with each other, and wherein the protective film has an opening to expose a portion of the third upper electrode, the exposed portion of the third upper electrode serving as a pad area (32) capable of wire bonding (allowing interconnections, also see [0040]). Bonding pad is defined as a small, exposed, conductive surface to allow interconnections.
Regarding Claim 21
FIG. 1 of Shih discloses a semiconductor substrate (10) provided under the lower electrode [0026].
Claims 20 and 21 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lo (U.S. Patent Pub. No. 2022/0285263) of record.
Regarding Claim 20
FIG. 15 of Lo discloses a semiconductor device, comprising: a semiconductor substrate (105, FIG. 1); a lower electrode (300A) in, on, or over the semiconductor substrate; a first dielectric layer (310) provided on the lower electrode; a first upper electrode (315A) provided on the first dielectric layer; a second dielectric layer (320) provided on the first upper electrode; a second upper electrode (325A) provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer (330) provided on the second upper electrode; and a third upper electrode (335A) provided on the third dielectric layer and electrically connected to the first upper electrode; and a protective film (350) provided on the third upper electrode, wherein a first capacitor (370A) between the lower electrode and the first upper electrode, a second capacitor (370B) between the first upper electrode and the second upper electrode, and a third capacitor (370C) between the second upper electrode and the third upper electrode are connected in parallel with each other (FIG. 16), and wherein the protective film has an opening (360, FIG. 14) to expose a portion (portion of 335A connection to 365A) of the third upper electrode, the exposed portion of the third upper electrode serving as a pad area capable of wire bonding (bonding to 365A and VSS, FIG. 16 and [0054]). Bonding pad is defined as a small, exposed, conductive surface to allow interconnections.
Regarding Claim 21
FIG. 1 of Lo discloses a semiconductor substrate (105) provided under the lower electrode.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5, 10-14 rejected under 35 U.S.C. 103 as being unpatentable over Lo, in view of Zhang (CN 108140643) of record.
Regarding Claim 1
FIG. 15 of Lo discloses a semiconductor device, comprising: a semiconductor substrate (105, FIG. 1); a lower electrode (300A) in, on, or over the semiconductor substrate; a first dielectric layer (310) provided on the lower electrode; a first upper electrode (315A) provided on the first dielectric layer; a second dielectric layer (320) provided on the first upper electrode; a second upper electrode (325A) provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer (330) provided on the second upper electrode; and a third upper electrode (335A) provided on the third dielectric layer and electrically connected to the first upper electrode, wherein a first capacitor (370A) between the lower electrode and the first upper electrode, a second capacitor (370B) between the first upper electrode and the second upper electrode, and a third capacitor (370C) between the second upper electrode and the third upper electrode are connected in parallel with each other (FIG. 16).
Lo is silent with respect to “a semiconductor substrate disposed as a vertical resistive element for current flowing therein generally vertically; a back electrode provided at a bottom of the semiconductor substrate to be electrically connected to the bottom of the semiconductor substrate” and “a top of the semiconductor substrate is electrically connected to the lower electrode so that the semiconductor substrate as the vertical resistive element is connected in series with said first to third capacitors”.
FIG. 73 of Zhang discloses a similar semiconductor device, comprising a semiconductor substrate (a supporting base material onto which semiconductor devices are fabricated or attached, also see text: “the substrate material layer 138”) disposed as a vertical resistive element (vertically aligned element with resistance, resistive element is a component that impedes the flow of electric current) for current flowing therein generally vertically (current is inherently allowed to vertically flow through the substrate material 138, I = V/R); a back electrode (136) provided at a bottom of the semiconductor substrate to be electrically connected to the bottom of the semiconductor substrate; and a top of the semiconductor substrate is electrically connected to the lower electrode (146).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Zhang such that the semiconductor substrate as the vertical resistive element is connected in series with said first to third capacitors. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of improving thermal management and electrical conductivity, providing mechanical strength, and enabling backside power delivery networks (BSPDNs) for more efficient power distribution and denser frontside signal routing.
Regarding Claim 2
FIG. 15 of Lo discloses a first via penetrating the first dielectric layer and the second dielectric layer and electrically connecting the lower electrode and the second upper electrode; and a second via penetrating the second dielectric layer and the third dielectric layer and electrically connecting the first upper electrode and the third upper electrode.
Regarding Claim 3
FIG. 15 of Lo discloses a lateral end of the first upper electrode is spaced apart from the first via, and a lateral end of the second upper electrode is spaced apart from the second via.
Regarding Claim 5
FIG. 15 of Lo discloses a protective film (350) provided on the third upper electrode (335A), wherein the protective film has an opening to expose a portion of the third upper electrode, the exposed portion of the third upper electrode serving as a pad area capable of wire bonding (bonding to 365A and VSS, FIG. 16 and [0054]).
Regarding Claim 10
FIG. 73 of Zhang discloses the lower electrode (136) is made of a high-impurity semiconductor region provided on an upper part of the semiconductor substrate (text: the blanket conductor layer 136 may include a metal, a metal alloy, a conductive metal nitride, a metal-semiconductor alloy (such as silicide) or more heavily doped with conductivity 1.0 * 105S/cm of semiconductor material).
Regarding Claim 11
FIG. 73 of Zhang discloses the lower electrode (136) is the semiconductor substrate.
Regarding Claim 12
FIG. 15 of Lo discloses a fourth dielectric layer (340) provided on the third upper electrode; a fourth upper electrode (345A) provided on the fourth dielectric layer and electrically connected to the second upper electrode; a fifth dielectric layer (350) provided on the fourth upper electrode; and a fifth upper electrode provided on the fifth dielectric layer and electrically connected to the third upper electrode, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04.
Regarding Claim 13
FIG. 15 of Lo discloses a first via (365B) penetrating the first dielectric layer and the second dielectric layer and electrically connecting the lower electrode (300A) and the second upper electrode (325A); and a second via (365A) penetrating the second dielectric layer and the third dielectric layer and electrically connecting the first upper electrode and the third upper electrode; a third via penetrating the third dielectric layer and the fourth dielectric layer and electrically connecting the second upper electrode and the fourth upper electrode; and a fourth via penetrating through the fourth dielectric layer and the fifth dielectric layer and electrically connecting the third upper electrode and the fifth upper electrode.
Regarding Claim 14
FIG. 15 of Lo discloses the first via and the third via are arranged at positions overlapping each other in a plan view, and the second via and the fourth via are arranged at positions overlapping each other in the plan view.
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Lo, in view of Nakayama (JP 2004119767, machine-translation provided).
Regarding Claim 1
FIG. 15 of Lo discloses a semiconductor device, comprising: a semiconductor substrate (105, FIG. 1); a lower electrode (300A) in, on, or over the semiconductor substrate; a first dielectric layer (310) provided on the lower electrode; a first upper electrode (315A) provided on the first dielectric layer; a second dielectric layer (320) provided on the first upper electrode; a second upper electrode (325A) provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer (330) provided on the second upper electrode; and a third upper electrode (335A) provided on the third dielectric layer and electrically connected to the first upper electrode, wherein a first capacitor (370A) between the lower electrode and the first upper electrode, a second capacitor (370B) between the first upper electrode and the second upper electrode, and a third capacitor (370C) between the second upper electrode and the third upper electrode are connected in parallel with each other (FIG. 16).
Lo is silent with respect to “a semiconductor substrate disposed as a vertical resistive element for current flowing therein generally vertically; a back electrode provided at a bottom of the semiconductor substrate to be electrically connected to the bottom of the semiconductor substrate” and “a top of the semiconductor substrate is electrically connected to the lower electrode so that the semiconductor substrate as the vertical resistive element is connected in series with said first to third capacitors”.
FIG. 23 of Nakayama discloses a similar semiconductor device, comprising a semiconductor substrate (1) disposed as a vertical resistive element [0008] for current flowing therein generally vertically (current is inherently allowed to flow through the substrate 1); a back electrode (38) provided at a bottom of the semiconductor substrate to be electrically connected to the bottom of the semiconductor substrate; and a top of the semiconductor substrate is electrically connected to the lower electrode (11B) of capacitor C [0025].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Nakayama such that the semiconductor substrate as the vertical resistive element is connected in series with said first to third capacitors. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of reducing device size and manufacturing cost ([0004] of Nakayama).
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Lo, in view of Hayashi (JP 2014241434, machine-translation provided).
Regarding Claim 1
FIG. 15 of Lo discloses a semiconductor device, comprising: a semiconductor substrate (105, FIG. 1); a lower electrode (300A) in, on, or over the semiconductor substrate; a first dielectric layer (310) provided on the lower electrode; a first upper electrode (315A) provided on the first dielectric layer; a second dielectric layer (320) provided on the first upper electrode; a second upper electrode (325A) provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer (330) provided on the second upper electrode; and a third upper electrode (335A) provided on the third dielectric layer and electrically connected to the first upper electrode, wherein a first capacitor (370A) between the lower electrode and the first upper electrode, a second capacitor (370B) between the first upper electrode and the second upper electrode, and a third capacitor (370C) between the second upper electrode and the third upper electrode are connected in parallel with each other (FIG. 16).
Lo is silent with respect to “a semiconductor substrate disposed as a vertical resistive element for current flowing therein generally vertically; a back electrode provided at a bottom of the semiconductor substrate to be electrically connected to the bottom of the semiconductor substrate” and “a top of the semiconductor substrate is electrically connected to the lower electrode so that the semiconductor substrate as the vertical resistive element is connected in series with said first to third capacitors”.
FIG. 19 of Hayashi discloses a similar semiconductor device, comprising a semiconductor substrate (11) disposed as a vertical resistive element (functions as a resistor R) for current flowing therein generally vertically (current is inherently allowed to flow through R); a back electrode (14) provided at a bottom of the semiconductor substrate to be electrically connected to the bottom of the semiconductor substrate; and a top of the semiconductor substrate is electrically connected to the lower electrode (1004).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Hayashi. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of forming a semiconductor snubber (text of Hayashi).
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Lo and Zhang, in view of Mizuno (U.S. Patent Pub. No. 2012/0007241) of record.
Regarding Claim 8
Lo as modified by Zhang discloses Claim 1 comprising a resistance layer (185, FIG. 1) provided on the semiconductor substrate via an insulating film (175) and below the lower electrode via another insulating film, the resistance layer extending horizontally and overlapping with the lower electrode thereabove in a plan view (obvious to one of ordinary skill in the art), wherein one end of the resistance layer is connected to the top of the semiconductor substrate and another end of the resistance layer is connected to the lower electrode so that the top of the semiconductor substrate is electrically connected to the lower electrode via the resistance layer, the resistance layer and the semiconductor substrate thereby constituting serially connected resistive elements that are connected in series with said first to third capacitors.
Lo as modified by Zhang is silent with respect to “the lower electrode being separate from the semiconductor substrate”.
FIG. 1 of Mizuno discloses a similar semiconductor device, wherein the lower electrode (12) being separate from the semiconductor substrate (113).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Mizuno. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of forming a buffer region ([0021] of Mizuno).
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Lo, Zhang and Mizuno, in view of Fujisawa (JP 2003347303) of record.
Regarding Claim 9
Lo as modified by Zhang and Mizuno discloses Claim 8.
Lo as modified by Zhang and Mizuno is silent with respect to “said resistance layer functions as a fuse”.
FIG. 1 of Fujisawa discloses a similar semiconductor device, comprising a resistance layer (22) provided on the semiconductor substrate (1) via an insulating film (15), wherein the resistance layer is electrically connected between the semiconductor substrate and the lower electrode (13), wherein said resistance layer functions as a fuse.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Fujisawa. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of preventing damage to an insulating film (Abstract of Fujisawa).
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Lo and Zhang, in view of Shih (U.S. Patent Pub. No. 2017/0018550) of record.
Regarding Claim 15
Lo as modified by Zhang discloses Claim 13.
Lo as modified by Zhang is silent with respect to “at least some of the first, second, third and the fourth vias are arranged on different sides of a rectangle formed by the lower electrode in a plan view”.
FIG. 9 of Shih discloses a similar semiconductor device, wherein at least some of the first, second, third and the fourth vias are arranged on different sides of a rectangle formed by the lower electrode in a plan view.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Shih. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of improving integration in semiconductor package ([0004] of Shih).
Claims 16 and 17 rejected under 35 U.S.C. 103 as being unpatentable over Lo and Zhang, in view of Lee (KR 20030057935) of record.
Regarding Claim 16
Lo as modified by Zhang discloses Claim 1.
Lo as modified by Zhang is silent with respect to “each of the first, second and third dielectric layers is a multilayered film made of a first dielectric film and a second dielectric film on the first dielectric film”.
Lee discloses a similar semiconductor device, wherein the dielectric layer is a multilayered film made of a first dielectric film and a second dielectric film on the first dielectric film (Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Lee. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of securing aiming capacitance (Abstract of Lee).
Regarding Claim 17
Lee discloses the first dielectric film is a TEOS film, and the second dielectric film is a PSG film (Abstract). With respect to “with a thickness of about 3 µm”, said thickness determines the capacitance. Therefore, said thickness is considered to be a result effective variable. The claim to a specific thickness therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Claims 4, 18 and 19 rejected under 35 U.S.C. 103 as being unpatentable over Lo, in view of Yokota (JP 2019040152, machine-translation provided).
Regarding Claim 4
Lo discloses Claim 2
Lo is silent with respect to “the first via is arranged at a position overlapping with the third upper electrode in a plan view”.
FIG. 13 of Yokota discloses a similar semiconductor device, wherein the first via (37) is arranged at a position overlapping with the third upper electrode (16m) in a plan view.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Yokota, because said configuration is a matter of choice. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of improving capacitance value (text of Yokota).
Regarding Claim 18
FIG. 15 of Lo discloses a semiconductor device, comprising: a semiconductor substrate (105, FIG. 1); a lower electrode (300A) in, on, or over the semiconductor substrate; a first dielectric layer (310) provided on the lower electrode; a first upper electrode (315A) provided on the first dielectric layer; a second dielectric layer (320) provided on the first upper electrode; a second upper electrode (325A) provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer (330) provided on the second upper electrode; and a third upper electrode (335A) provided on the third dielectric layer and electrically connected to the first upper electrode; a first via (365B) penetrating the first dielectric layer and the second dielectric layer and electrically connecting the lower electrode and the second upper electrode; and a second via (365A) penetrating the second dielectric layer and the third dielectric layer and electrically connecting the first upper electrode and the third upper electrode, wherein a first capacitor (370A) between the lower electrode and the first upper electrode, a second capacitor (370B) between the first upper electrode and the second upper electrode, and a third capacitor (370C) between the second upper electrode and the third upper electrode are connected in parallel with each other (FIG. 16).
Lo is silent with respect to “the first via is arranged at a position overlapping with the third upper electrode in a plan view”.
FIG. 13 of Yokota discloses a similar semiconductor device, wherein the first via (37) is arranged at a position overlapping with the third upper electrode (16m) in a plan view.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Yokota, because said configuration is a matter of choice. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of improving capacitance value (text of Yokota).
Regarding Claim 19
FIG. 1 of Lo discloses a semiconductor substrate (105) provided under the lower electrode.
Claims 18 and 19 rejected under 35 U.S.C. 103 as being unpatentable over Shih, in view of Nakagawa (U.S. Patent Pub. No. 2009/0040447).
Regarding Claim 18
FIG. 1 of Shih discloses a semiconductor device, comprising: a lower electrode (11); a first dielectric layer (21 and portion of 40 extended from 21) provided on the lower electrode; a first upper electrode (12) provided on the first dielectric layer; a second dielectric layer (22 and portion of 40 extended from 22) provided on the first upper electrode; a second upper electrode (13) provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer (23 and portion of 40 extended from 23) provided on the second upper electrode; and a third upper electrode (14) provided on the third dielectric layer and electrically connected to the first upper electrode; a first via (32) penetrating the first dielectric layer and the second dielectric layer and electrically connecting the lower electrode and the second upper electrode; and a second via (31) penetrating the second dielectric layer and the third dielectric layer and electrically connecting the first upper electrode and the third upper electrode, wherein a first capacitor (C2) between the lower electrode and the first upper electrode, a second capacitor (C3) between the first upper electrode and the second upper electrode, and a third capacitor (C4) between the second upper electrode and the third upper electrode are connected in parallel with each other (FIG. 1A).
Shih is silent with respect to “the first via is arranged at a position overlapping with the third upper electrode in a plan view”.
FIG. 6 of Nakagawa discloses a similar semiconductor device, wherein the first via (82) is arranged at a position overlapping with the third upper electrode (300a) in a plan view (FIGS. 4-5).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Shih, as taught by Nakagawa. The ordinary artisan would have been motivated to modify Shih in the above manner for purpose of improving the function of capacitive element ([0036] of Nakagawa).
Regarding Claim 19
FIG. 1 of Shih discloses a semiconductor substrate (10) provided under the lower electrode [0026] discloses a semiconductor substrate (105) provided under the lower electrode.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Lo, in view of Li (CN 109755387) of record.
Regarding Claim 18
FIG. 15 of Lo discloses a semiconductor device, comprising: a semiconductor substrate (105, FIG. 1); a lower electrode (300A) in, on, or over the semiconductor substrate; a first dielectric layer (310) provided on the lower electrode; a first upper electrode (315A) provided on the first dielectric layer; a second dielectric layer (320) provided on the first upper electrode; a second upper electrode (325A) provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer (330) provided on the second upper electrode; and a third upper electrode (335A) provided on the third dielectric layer and electrically connected to the first upper electrode, wherein a first capacitor (370A) between the lower electrode and the first upper electrode, a second capacitor (370B) between the first upper electrode and the second upper electrode, and a third capacitor (370C) between the second upper electrode and the third upper electrode are connected in parallel with each other (FIG. 16).
Lo is silent with respect to “the first via is arranged at a position overlapping with the third upper electrode in a plan view”.
FIG. 11 of Li discloses a similar semiconductor device, wherein the first via (contacts between stacked and parallelly connected capacitors 9, text: “stacked together in parallel by a plurality of contact”) is arranged at a position overlapping with the third upper electrode in a plan view (these contacts are directly attached to the capacitors, they are inherently overlapping with the capacitor electrodes in a plan view).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lo, as taught by Li. The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of forming stacking capacitor structure (Abstract of Li).
Pertinent Art
Pertinent art includes U.S. Patent Pub. No. 2002/0150777, Kuo (U.S. Patent Pub. No. 2023/0068481), Liang (U.S. Patent Pub. No. 2011/0260231), RE50102, CN 103034001, JP 2006250985, and Stephan (JP H09505944).
Response to Arguments
Applicant’s arguments with respect to Claim 20 have been considered but they are not persuasive. The protective film 350 of Lo has an opening (filled with 365A) to expose a portion (portion of 335A connection 365A) of the third upper electrode, the exposed portion of the third upper electrode serving as a pad area capable of wire bonding (bonding to VSS, FIG. 16). FIG. 4 of Hayashi (JP 2014241534) also discloses the exposed portion of the upper electrode 13 serving as a pad area capable of wire bonding. Bonding pad is defined as a small, exposed, conductive surface to allow interconnections. Applicant’s arguments with respect to Claim 1 have been considered but they are not persuasive. Element 38 of Zhang is a semiconductor substrate (defined as a supporting base material onto which semiconductor devices are fabricated or attached, also see text: “the substrate material layer 138”) disposed as a vertical resistive element (vertically aligned element with resistance) for current flowing therein generally vertically (current is inherently allowed to flow through the substrate material 138); a back electrode (136) provided at a bottom of the semiconductor substrate to be electrically connected to the bottom of the semiconductor substrate; and a top of the semiconductor substrate is electrically connected to the lower electrode (146). The ordinary artisan would have been motivated to modify Lo in the above manner for purpose of, e.g., improving thermal management and electrical conductivity, providing mechanical strength, and enabling backside power delivery networks (BSPDNs) for more efficient power distribution and denser frontside signal routing. Applicant’s arguments with respect to Claim 18 have been considered but they are not persuasive. FIG. 11 of Li discloses the first via (contacts between stacked and parallelly connected capacitors, text: “stacked together in parallel by a plurality of contact”) is arranged at a position overlapping with the third upper electrode in a plan view (these contacts are directly attached to the capacitors, they are inherently overlapping with the capacitor electrodes in a plan view).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897