DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (US 2022/0328647).
Regarding claim 1, Liu discloses, in at least figures 26-26D and related text, an integrated circuit structure, comprising:
a sub-fin structure (204, [19]) over a stack of nanowires (206, [24]);
a gate structure (230, [47]) vertically around the stack of nanowires (206, [24]);
an internal gate spacer (226, [42]) between vertically adjacent ones of the nanowires (206, [24]) and adjacent to the gate structure (230, [47]);
a trench contact structure (290, [54]) laterally adjacent to a side of the gate structure (230, [47]); and
a cavity spacer (280, [50]) laterally between the gate structure (230, [47]) and the trench contact structure (290, [54]).
Regarding claim 2, Liu discloses the integrated circuit structure of claim 1 as described above.
Liu further discloses, in at least figures 26-26D and related text, a dielectric layer (215, [38]) sealing the cavity spacer (280, [50]).
Regarding claim 3, Liu discloses the integrated circuit structure of claim 2 as described above.
Liu further discloses, in at least figures 26-26D and related text, the dielectric layer (215, [38]) is laterally adjacent to the sub-fin structure (204, [19]).
Regarding claim 4, Liu discloses the integrated circuit structure of claim 1 as described above.
Liu further discloses, in at least figures 26-26D and related text, the sub-fin structure (204, [19]) is a semiconductor sub-fin structure ([19]).
Claim(s) 11-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (US 2020/0381531).
Regarding claim 11, Chung discloses, in at least figures 17B, 19A-19B, and related text, an integrated circuit structure, comprising:
a stack of nanowires (208, [18]);
a gate structure (1300 (1304/1306), [50]) vertically around the stack of nanowires (208, [18]);
a source or drain structure (902, [39]) coupled to an end of the stack of nanowires (208, [18]), the source or drain structure (902, [39]) adjacent to a side of the gate structure (1300 (1304/1306), [50]);
a plurality of internal cavity spacers (1602, [54]) between vertically adjacent ones of the nanowires (208, [18]), the plurality of internal cavity spacers (1602, [54]) laterally between the gate structure (1300 (1304/1306), [50]) and the source or drain structure (902, [39]); and
a dipole layer (1304, [48]) lining individual one of the plurality of internal cavity spacers (1602, [54]).
Regarding claim 12, Liu discloses the integrated circuit structure of claim 11 as described above.
Chung further discloses, in at least figures 17B, 19A-19B, and related text, the gate structure (1300 (1304/1306), [50]) includes an N-type gate electrode ([50]), and wherein the source or drain structure (902, [39]) is an N-type source or drain structure ([39]).
Regarding claim 13, Liu discloses the integrated circuit structure of claim 12 as described above.
Chung further discloses, in at least figures 17B, 19A-19B, and related text, the dipole layer (1304, [48]) includes a material selected from the group consisting of Al2O3 ([48]), TiO2 ([48]), NbO and ZrO2 ([48]).
Regarding claim 14, Liu discloses the integrated circuit structure of claim 11 as described above.
Chung further discloses, in at least figures 17B, 19A-19B, and related text, the gate structure (1300 (1304/1306), [50]) includes a P-type gate electrode ([50]), and wherein the source or drain structure (902, [39]) is a P-type source or drain structure ([39]).
Regarding claim 15, Liu discloses the integrated circuit structure of claim 14 as described above.
Chung further discloses, in at least figures 17B, 19A-19B, and related text, the dipole layer (1304, [48]) includes a material selected from the group consisting of La2O3, Y2O3 ([48]), MgO, SrO and Lu2O3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2022/0328647) in view of Guler (US 2020/0219978).
Regarding claim 5, Liu discloses the integrated circuit structure of claim 1 as described above.
Liu does not explicitly disclose the sub-fin structure is an insulator sub-fin structure.
Guler teaches, in at least figure 4J and related text, the device comprising the sub-fin structure (498, [55]) is an insulator sub-fin structure ([55]), for the purpose of providing oxide sub-fin structure for transistor isolation from sub-fin conduction thereby reducing leakage ([22]).
Liu and Guler are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liu with the specified features of Guler because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Liu to have the sub-fin structure being an insulator sub-fin structure, as taught by Guler, for the purpose of providing oxide sub-fin structure for transistor isolation from sub-fin conduction thereby reducing leakage ([22], Guler).
Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guler (US 2020/0219978) in view of Liu (US 2022/0328647).
Regarding claim 6, Guler discloses, in at least figures 4J, 9, and related text, a computing device (the limitation of "a computing device" has not patentable weight because it is interpreted as intended use), comprising:
a board (902, [121]); and
a component (904, [124]) coupled to the board (902, [121]), the component (904, [124]) including an integrated circuit structure ([124]), comprising:
a sub-fin structure (498, [55]) over a stack of nanowires (406’, [55]);
a gate structure (428/426, [54]) vertically around the stack of nanowires (406’, [55]);
an internal gate spacer (416, [52]) between vertically adjacent ones of the nanowires (406’, [55]) and adjacent to the gate structure (428/426, [54]);
a trench contact structure (436, [57]) laterally adjacent to a side of the gate structure (428/426, [54]).
Guler does not explicitly disclose a cavity spacer laterally between the gate structure and the trench contact structure.
Liu teaches, in at least figures 26-26D and related text, the device comprising a cavity spacer (280, [50]) laterally between the gate structure (230, [47]) and the trench contact structure (290, [54]), for the purpose of providing air gap along gate spacers and around the fins to reduce the parasitic capacitance of the IC structure ([16]).
Guler and Liu are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Guler with the specified features of Liu because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Guler to have the cavity spacer laterally between the gate structure and the trench contact structure, as taught by Liu, for the purpose of providing air gap along gate spacers and around the fins to reduce the parasitic capacitance of the IC structure ([16], Liu).
Regarding claim 7, Guler in view of Liu discloses the computing device of claim 6 as described above.
Guler further discloses, in at least figures 4J, 9, and related text, a memory ([122]) coupled to the board (902, [121]).
Regarding claim 8, Guler in view of Liu discloses the computing device of claim 6 as described above.
Guler further discloses, in at least figures 4J, 9, and related text, a communication chip (906, [123]) coupled to the board (902, [121]).
Regarding claim 9, Guler in view of Liu discloses the computing device of claim 6 as described above.
Guler further discloses, in at least figures 4J, 9, and related text, the component (904, [124]) is a packaged integrated circuit die ([124]).
Regarding claim 10, Guler in view of Liu discloses the computing device of claim 6 as described above.
Guler further discloses, in at least figures 4J, 9, and related text, the component is selected from the group consisting of a processor (904, [124]), a communications chip (906, [123]), and a digital signal processor ([122]).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guler (US 2020/0219978) in view of Chung (US 2020/0381531).
Regarding claim 16, Guler discloses, in at least figures 4J, 9, and related text, a computing device (the limitation of "a computing device" has not patentable weight because it is interpreted as intended use), comprising:
a board (902, [121]); and
a component (904, [124]) coupled to the board (902, [121]), the component (904, [124]) including an integrated circuit structure ([124]), comprising:
a stack of nanowires (406’, [55]);
a gate structure (428/426, [54]) vertically around the stack of nanowires (406’, [55]);
a source or drain structure (422, [53]) coupled to an end of the stack of nanowires (406’, [55]), the source or drain structure (422, [53]) adjacent to a side of the gate structure (428/426, [54]);
a plurality of internal cavity spacers (416, [52]) between vertically adjacent ones of the nanowires (406’, [55]), the plurality of internal cavity spacers (416, [52]) laterally between the gate structure (428/426, [54]) and the source or drain structure (422, [53]).
Guler does not explicitly disclose a dipole layer lining individual one of the plurality of internal cavity spacers.
Chung teaches, in at least figures 17B, 19A-19B, and related text, the device comprising a dipole layer (1304, [48]) lining individual one of the plurality of internal cavity spacers (1602, [54]), for the purpose of providing air gaps as inner spacer elements for GAA devices ([12]) thereby providing better isolation between gate and source/drain structures.
Guler and Chung are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Guler with the specified features of Chung because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Guler to have the dipole layer lining individual one of the plurality of internal cavity spacers, as taught by Chung, for the purpose of providing air gaps as inner spacer elements for GAA devices ([12], Chung) thereby providing better isolation between gate and source/drain structures.
Regarding claim 17, Guler in view of Chung discloses the computing device of claim 16 as described above.
Guler further discloses, in at least figures 4J, 9, and related text, a memory ([122]) coupled to the board (902, [121]).
Regarding claim 18, Guler in view of Chung discloses the computing device of claim 16 as described above.
Guler further discloses, in at least figures 4J, 9, and related text, a communication chip (906, [123]) coupled to the board (902, [121]).
Regarding claim 19, Guler in view of Chung discloses the computing device of claim 16 as described above.
Guler further discloses, in at least figures 4J, 9, and related text, the component (904, [124]) is a packaged integrated circuit die ([124]).
Regarding claim 20, Guler in view of Chung discloses the computing device of claim 16 as described above.
Guler further discloses, in at least figures 4J, 9, and related text, the component is selected from the group consisting of a processor (904, [124]), a communications chip (906, [123]), and a digital signal processor ([122]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811